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2021-03-06hw/sh4/sh7750_regs: Replace link to license by its full contentPhilippe Mathieu-Daudé1-2/+22
This file is borrowed from the RTEMS source code, which comes with a GPL-2.0-or-later license with a header exception. Expand the GPL-2.0-or-later license in place to not be dependent on a 3rd party website. This also fix the misleading comment "The license and distribution terms for this file may be found in the file LICENSE in this distribution" referring to the RTEMS distribution and not to the QEMU one. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210222185605.2714192-1-f4bug@amsat.org>
2021-03-06hw/sh4: Remove now unused CONFIG_SH4 from KconfigPhilippe Mathieu-Daudé1-5/+0
As replaced the generic CONFIG_SH4 by more fine-grained selectors, we can remove this now unused config variable. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-9-f4bug@amsat.org>
2021-03-06hw/pci-host: Introduce SH_PCI Kconfig entryPhilippe Mathieu-Daudé6-1/+7
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_PCI selector for the SH4 PCI controller. Move the file with the other PCI host devices in hw/pci-host and add its missing MAINTAINERS entries. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-8-f4bug@amsat.org>
2021-03-06hw/block: Introduce TC58128 eeprom Kconfig entryPhilippe Mathieu-Daudé4-1/+6
Add more fine-grained selection by adding a CONFIG_TC58128 selector for the TC58128 eeprom. As this device is only used by the Shix machine, add an entry to the proper section in MAINTAINERS. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-7-f4bug@amsat.org>
2021-03-06hw/timer: Introduce SH_TIMER Kconfig entryPhilippe Mathieu-Daudé4-2/+8
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_TIMER selector for the SH4 timer control unit. Add the missing MAINTAINERS entries. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-6-f4bug@amsat.org>
2021-03-06hw/char: Introduce SH_SCI Kconfig entryPhilippe Mathieu-Daudé4-1/+7
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_SCI selector for the SH4 serial controller. Add the missing MAINTAINERS entries. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-5-f4bug@amsat.org>
2021-03-06hw/intc: Introduce SH_INTC Kconfig entryPhilippe Mathieu-Daudé3-1/+5
We want to be able to use the 'SH4' config for architecture specific features. Add more fine-grained selection by adding a CONFIG_SH_INTC selector for the SH4 interrupt controller. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-4-f4bug@amsat.org>
2021-03-06hw/sh4: Add missing Kconfig dependency on SH7750 for the R2D boardPhilippe Mathieu-Daudé1-0/+1
r2d_init() calls sh7750_init() so depends on SH7750.Harmless at the moment because nothing actually uses CONFIG_SH7750 (hw/sh4/meson.build always compiles sh7750.c and sh7750_regnames.c unconditionally). Fixes: 7ab58d4c841 ("sh4-softmmu.mak: express dependencies with Kconfig") Reported-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-3-f4bug@amsat.org>
2021-03-06hw/sh4: Add missing licensePhilippe Mathieu-Daudé2-3/+54
This code was introduced in commit 27c7ca7e775, ("SHIX board emulation (Samuel Tardieu)"). Use the same license. Cc: Samuel Tardieu <sam@rfc1149.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20210222141514.2646278-2-f4bug@amsat.org>
2021-03-06target/sh4: Remove unused definitionsPhilippe Mathieu-Daudé1-11/+0
Remove these confusing and unused definitions. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210127232151.3523581-6-f4bug@amsat.org>
2021-03-06target/sh4: Let get_physical_address() use MMUAccessType access_typePhilippe Mathieu-Daudé1-10/+10
superh_cpu_tlb_fill() already provides a access_type variable of type MMUAccessType, and it is passed along, but casted as integer and renamed 'rw'. Simply replace 'int rw' by 'MMUAccessType access_type'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210127232151.3523581-5-f4bug@amsat.org>
2021-03-06target/sh4: Remove unused 'int access_type' argumentPhilippe Mathieu-Daudé1-8/+7
get_mmu_address() and get_physical_address() don't use their 'int access_type' argument: remove it along with ACCESS_INT in superh_cpu_tlb_fill(). Suggested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2021-03-06target/sh4: Replace magic value by MMUAccessType definitionsPhilippe Mathieu-Daudé1-8/+8
Replace the 0/1/2 magic values by the corresponding MMUAccessType. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210127232151.3523581-3-f4bug@amsat.org>
2021-03-06target/sh4: Fix code style for checkpatch.plPhilippe Mathieu-Daudé1-41/+41
We are going to move this code, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210127232151.3523581-2-f4bug@amsat.org>
2021-03-05Merge remote-tracking branch 'remotes/cohuck-gitlab/tags/s390x-20210305' ↵Peter Maydell8-17/+48
into staging some accumulated s390x fixes # gpg: Signature made Fri 05 Mar 2021 15:50:00 GMT # gpg: using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF # gpg: issuer "cohuck@redhat.com" # gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown] # gpg: aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full] # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full] # gpg: aka "Cornelia Huck <cohuck@kernel.org>" [unknown] # gpg: aka "Cornelia Huck <cohuck@redhat.com>" [unknown] # Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0 18CE DECF 6B93 C6F0 2FAF * remotes/cohuck-gitlab/tags/s390x-20210305: target/s390x/kvm: Simplify debug code vfio-ccw: Do not read region ret_code after write css: SCHIB measurement block origin must be aligned virtio-ccw: commands on revision-less devices s390x/pci: restore missing Query PCI Function CLP data hw/s390x: fix build for virtio-9p-ccw target/s390x/arch_dump: Fix warning for the name field in the PT_NOTE section s390x/cpu_model: disallow unpack for --only-migratable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2021-03-05' into ↵Peter Maydell6-56/+45
staging QAPI patches patches for 2021-03-05 # gpg: Signature made Fri 05 Mar 2021 14:42:18 GMT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-qapi-2021-03-05: qapi: Fix parse errors for removal of null from schema language qapi: Remove QMP events and commands from user-mode builds qga: Utilize QAPI_LIST_APPEND in qmp_guest_network_get_interfaces error: Fix "Converting to ERRP_GUARD()" doc on "valid at return" Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-05qapi: Fix parse errors for removal of null from schema languageMarkus Armbruster3-6/+6
Commit 9d55380b5a "qapi: Remove null from schema language" (v4.2.0) neglected to update two error messages. Do that now. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210224101442.1837475-1-armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>
2021-03-05qapi: Remove QMP events and commands from user-mode buildsPhilippe Mathieu-Daudé1-4/+8
We removed the QMP loop in user-mode builds in commit 1935e0e4e09 ("qapi/meson: Remove QMP from user-mode emulation"), now commands and events code is unreachable. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210224171642.3242293-1-philmd@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-03-05qga: Utilize QAPI_LIST_APPEND in qmp_guest_network_get_interfacesEric Blake1-45/+30
I found another spot that can benefit from using our macros instead of open-coding qapi list creation. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20210205171634.1491258-1-eblake@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2021-03-05error: Fix "Converting to ERRP_GUARD()" doc on "valid at return"Markus Armbruster1-1/+1
Setting errp = NULL is wrong: the automatic error propagation still propagates the dangling pointer _auto_errp_prop.local_err. We need to set *errp = NULL to clear the dangling pointer. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20210125132635.1253219-1-armbru@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2021-03-05Merge remote-tracking branch ↵Peter Maydell29-64/+1285
'remotes/alistair/tags/pull-riscv-to-apply-20210304' into staging RISC-V PR for 6.0 This PR is a collection of RISC-V patches: - Improvements to SiFive U OTP - Upgrade OpenSBI to v0.9 - Support the QMP dump-guest-memory - Add support for the SiFive SPI controller (sifive_u) - Initial RISC-V system documentation - A fix for the Goldfish RTC - MAINTAINERS updates - Support for high PCIe memory in the virt machine # gpg: Signature made Thu 04 Mar 2021 14:44:31 GMT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * remotes/alistair/tags/pull-riscv-to-apply-20210304: hw/riscv: virt: Map high mmio for PCIe hw/riscv: virt: Limit RAM size in a 32-bit system hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() hw/riscv: Drop 'struct MemmapEntry' MAINTAINERS: Add a SiFive machine section goldfish_rtc: re-arm the alarm after migration docs/system: riscv: Add documentation for sifive_u machine docs/system: Add RISC-V documentation docs/system: Sort targets in alphabetical order hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal value hw/riscv: sifive_u: Add QSPI2 controller and connect an SD card hw/riscv: sifive_u: Add QSPI0 controller and connect a flash hw/ssi: Add SiFive SPI controller support hw/block: m25p80: Add various ISSI flash information hw/block: m25p80: Add ISSI SPI flash support target-riscv: support QMP dump-guest-memory roms/opensbi: Upgrade from v0.8 to v0.9 hw/misc: sifive_u_otp: Use error_report() when block operation fails target/riscv: Declare csr_ops[] with a known size Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04hw/riscv: virt: Map high mmio for PCIeBin Meng1-2/+33
Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Limit RAM size in a 32-bit systemBin Meng1-0/+10
RV32 supports 34-bit physical address hence the maximum RAM size should be limited. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init()Bin Meng1-7/+7
`link_up` is never used in gpex_pcie_init(). Drop it. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210220144807.819-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: Drop 'struct MemmapEntry'Bin Meng6-37/+19
There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20210220144807.819-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04MAINTAINERS: Add a SiFive machine sectionAlistair Francis1-0/+9
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Acked-by: Bin Meng <bin.meng@windriver.com> Acked-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 6bc077e5ae4a9512c8adf81ae194718f2f17c402.1612836645.git.alistair.francis@wdc.com
2021-03-04goldfish_rtc: re-arm the alarm after migrationLaurent Vivier1-0/+2
After a migration the clock offset is updated, but we also need to re-arm the alarm if needed. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20201220112615.933036-7-laurent@vivier.eu Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04docs/system: riscv: Add documentation for sifive_u machineBin Meng2-0/+346
This adds detailed documentation for RISC-V `sifive_u` machine, including the following information: - Supported devices - Hardware configuration information - Boot options - Machine-specific options - Running Linux kernel - Running VxWorks kernel - Running U-Boot, and with an alternate configuration Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 20210126060007.12904-10-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04docs/system: Add RISC-V documentationBin Meng2-0/+63
Add RISC-V system emulator documentation for generic information. `Board-specific documentation` and `RISC-V CPU features` are only a placeholder and will be added in the future. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-9-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04docs/system: Sort targets in alphabetical orderBin Meng1-7/+12
Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-8-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Change SIFIVE_U_GEM_IRQ to decimal valueBin Meng1-1/+1
All other peripherals' IRQs are in the format of decimal value. Change SIFIVE_U_GEM_IRQ to be consistent. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI2 controller and connect an SD cardBin Meng3-2/+45
This adds the QSPI2 controller to the SoC, and connects an SD card to it. The generation of corresponding device tree source fragment is also added. Specify machine property `msel` to 11 to boot the same upstream U-Boot SPL and payload image for the SiFive HiFive Unleashed board. Note subsequent payload is stored in the SD card image. $ qemu-system-riscv64 -nographic -M sifive_u,msel=11 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=sdcard.img,if=sd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/riscv: sifive_u: Add QSPI0 controller and connect a flashBin Meng3-0/+58
This adds the QSPI0 controller to the SoC, and connects an ISSI 25WP256 flash to it. The generation of corresponding device tree source fragment is also added. Since the direct memory-mapped mode is not supported by the SiFive SPI model, the <reg> property does not populate the second group which represents the memory mapped address of the SPI flash. With this commit, upstream U-Boot for the SiFive HiFive Unleashed board can boot on QEMU 'sifive_u' out of the box. This allows users to develop and test the recommended RISC-V boot flow with a real world use case: ZSBL (in QEMU) loads U-Boot SPL from SPI flash to L2LIM, then U-Boot SPL loads the payload from SPI flash that is combined with OpenSBI fw_dynamic firmware and U-Boot proper. Specify machine property `msel` to 6 to allow booting from the SPI flash. U-Boot spl is directly loaded via `-bios`, and subsequent payload is stored in the SPI flash image. Example command line: $ qemu-system-riscv64 -nographic -M sifive_u,msel=6 -smp 5 -m 8G \ -bios u-boot-spl.bin -drive file=spi-nor.img,if=mtd Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/ssi: Add SiFive SPI controller supportBin Meng4-0/+410
This adds the SiFive SPI controller model for the FU540 SoC. The direct memory-mapped SPI flash mode is unsupported. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add various ISSI flash informationBin Meng1-0/+13
This updates the flash information table to include various ISSI flashes that are supported by upstream U-Boot and Linux kernel. Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/block: m25p80: Add ISSI SPI flash supportBin Meng1-1/+43
This adds the ISSI SPI flash support. The number of dummy cycles in fast read, fast read dual output and fast read quad output commands is currently using the default 8. Likewise, the same default value is used for fast read dual/quad I/O command. Per the datasheet [1], the number of dummy cycles is configurable, but this is not modeled at present. For flash whose size is larger than 16 MiB, the sequence of 3-byte address along with EXTADD bit in the bank address register (BAR) is not supported. We assume that guest software always uses op codes with 4-byte address sequence. Fortunately, this is the case for both U-Boot and Linux spi-nor drivers. QPI (Quad Peripheral Interface) that supports 2-cycle instruction has different default values for dummy cycles of fast read family commands, and is unsupported at the time being. [1] http://www.issi.com/WW/pdf/25LP-WP256.pdf Signed-off-by: Bin Meng <bin.meng@windriver.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210126060007.12904-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04target-riscv: support QMP dump-guest-memoryYifei Jiang5-0/+210
Add the support needed for creating prstatus elf notes. This allows us to use QMP dump-guest-memory. Now ELF notes of RISC-V only contain prstatus elf notes. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Mingwang Li <limingwang@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Message-id: 20210201124458.1248-2-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04roms/opensbi: Upgrade from v0.8 to v0.9Bin Meng5-0/+0
Upgrade OpenSBI from v0.8 to v0.9 and the pre-built bios images. The v0.9 release includes the following commits: 35bc810 docs/platform: Update QEMU parameter for fw_payload 78afe11 config.mk: Update QEMU run command for generic and sifive fu540 platforms ec3e5b1 docs/platform: sifive_fu540: Update U-Boot instructions 7d61a68 README.md: fix markdown link formatting a5f9104 lib/utils: fdt: Update FDT expand size to 1024 for reserved memory node ec1abf6 include: sbi_bitops: Remove dead shift assignment in ffs/fls 8e47649 lib: Add sbi_strncmp implementation 2845d2d lib: utils: Add a macro in libfdt_env.h for strncmp 2cfd2fc lib: utils: Use strncmp in fdt_parse_hart_id() 937caee lib: sbi_misaligned_ldst: Determine transformed instruction length correctly 4b18a2a firmware: fw_base: Improve exception stack setup in trap handler 9d56961 lib: sbi_trap: Fix hstatus.SPVP update in sbi_trap_redirect() d7f87d9 platform: kendryte/k210: fixup FDT e435ba0 lib: sbi_init: Avoid thundering hurd problem with coldboot_lock 4f3bad6 lib: sbi: Handle the case where MTVAL has illegal instruction address 7b0b289 lib: sbi: Remove redundant SBI_HART_HAS_PMP feature 74d1db7 lib: sbi: Improve PMP CSR detection and progamming 2c341f7 lib: sbi: Detect and print MHPM counters at boot-time 162d453 include: sbi: Few cosmetic changes in riscv_encoding.h ebc8ebc lib: sbi: Improve HPM CSR read/write emulation dcb10c0 lib: sbi: Don't handle VS-mode ecall in sbi_trap_handler() bef63d6 include: Rename ECALL defines to match latest RISC-V spec c1c7c3e lib: sbi_trap: Allow M-mode to M-mode ECALLs 6734304 lib: sbi: Allow specifying start mode to sbi_hsm_hart_start() API 7ccf6bf lib: sbi: Allow specifying mode in sbi_hart_pmp_check_addr() API 9f935a4 lib: utils: Improve fdt_cpu_fixup() implementation 172fa16 lib: sbi: Ensure coldboot HART supports next privilege mode aaeca7e platform: generic: Don't mark non-MMU HARTs as invalid 7701ea1 lib: sbi: Fix PMP CSR detection 79bf80b lib: sbi_scratch: typo scatch a04c465 makefile: fix clean directive af4b50f Makefile: Build ELF, BIN and LD script in platform build directory 6ca0969 firmware: Add common FW_FDT_PATH compile-time option 9c07c51 firmware: Remove FW_PAYLOAD_FDT_PATH compile-time option e9a4bfb Makefile: Allow padding zeros when converting DTB to C source a0f2d4a platform: kendryte/k210: Add some padding for FDT fixups dbeeacb include: sbi: Remove redundant includes from sbi_platform.h a12d46a include: sbi: Remove pmp_region callbacks from sbi_platform_operations a126886 lib: sbi: Configure PMP late in coldboot and warmboot path f81d6f6 lib: sbi: Remove redundant hartid parameter from sbi_hart_init() 8b65005 include: sbi: Make hartmask pointer const in sbi_hartmask_test_hart() b1678af lib: sbi: Add initial domain support e73b92d lib: sbi: Extend sbi_hsm_hart_started_mask() for domains 3a30d2c lib: sbi: Extend sbi_hsm_hart_start() for domains 530e95b lib: sbi: Optimize sbi_hsm_hart_started_mask() implementation 3e20037 lib: sbi: Extend sbi_system_reset() for domains 5edbb7c lib: utils: Update fdt_reserved_memory_fixup() to use current domain 5fd99db lib: utils: Update fdt_cpu_fixup() to use current domain e856462 lib: sbi: Remove redundant sbi_hart_pmp_xyz() functions c10c30b lib: sbi: Configure PMP based on domain memory regions c347408 lib: sbi: Display domain details in boot prints fdf5d5c docs: Add initial documentation for domain support 74c0ea1 lib: utils: Implement "ranges" property parsing bf21632 lib: sbi: Detect PMP granularity and number of address bits a809f40 lib: sbi: Improve boot time print with additional PMP information 914f81f Makefile: Add option to use toolchain default ABI and ISA string 48616b3 lib: sbi: Improve boot prints in cold boot sequence 781cafd docs: fix a typo error 54a7734 include: sbi: Add SBI SRST extension related defines c4acc60 include: sbi: Remove opensbi specific reset type defines da07479 platform: Remove dummy system reset functions 5c429ae lib: sbi: Improve system reset platform operations 548d03e lib: sbi: Implement System Reset (SRST) SBI extension 2677324 firmware: fw_base: Optimize trap handler for RV32 systems 8d2edc4 lib: sbi: Fix sbi_hart_switch_mode() for u-mode 3d921fa lib: sbi: Fix typo in sbi_domain_finalize() 4e37022 lib: sbi: Fix domain_count check in sbi_domain_finalize() c709d40 lib: sbi: Auto start domain only if boot HART within limits c1f6d89 include: sbi: Use lower bits for domain memory region permissions 62ea4f4 lib: sbi: Override domain boot HART when coldboot HART assigned to it 555e737 lib: sbi: Add error prints in sbi_domain_finalize() 9b65dca include: sbi: Add domains_init() platform operation c0d2baa docs: Add domain device tree binding documentation ba741ea lib: utils: Add helper routines to populate domains from FDT 4fffb53 platform: generic: Populate domains from FDT e7da0b4 lib: utils/libfdt: Upgrade to v1.6.0 release 2179777 lib: utils: Allow FDT domain iteration functions to fail 7baccfc lib: sbi: Add function to register new domain 6fc1986 lib: utils: Remove fdt_domain_get() function a029bd9 lib: sbi: Remove domain_get() platform callback function 7dcb1e1 lib: sbi: Fix sign-extension in sbi_misaligned_load_handler() 80bc506 lib: sbi: Replace args with trap registers in ecall handler b7df5e4 lib: sbi: Introduce sbi_trap_exit() API 12394a2 lib: sbi: Allow custom local TLB flush function 0d49c3b lib: utils: Fix shakti uart implementation db56341 lib: sbi: Allow platforms to provide root domain memory regions e884416 include: sbi: No need to pack struct sbi_trap_regs 386eba2 include: sbi: No need to pack struct sbi_scratch 1bbf361 include: sbi: Don't pack struct sbi_platform and sbi_platform_operations da5293f platform: template: Fix compile error 234ed8e include: Bump-up version to 0.9 Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: 20210119234438.10132-1-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04hw/misc: sifive_u_otp: Use error_report() when block operation failsBin Meng1-8/+5
At present when blk_pread() / blk_pwrite() fails, a guest error is logged, but this is not really a guest error. Change to use error_report() instead. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1611026585-29971-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04target/riscv: Declare csr_ops[] with a known sizeBin Meng1-1/+1
csr_ops[] is currently declared with an unknown size in cpu.h. Since the array size is known, let's do a complete declaration. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 1611024723-14293-1-git-send-email-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-03-04target/s390x/kvm: Simplify debug codePhilippe Mathieu-Daudé1-2/+1
We already have the 'run' variable holding 'cs->kvm_run' value. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210303182219.1631042-3-philmd@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04Merge remote-tracking branch 'remotes/kraxel/tags/ui-20210304-pull-request' ↵Peter Maydell21-123/+131
into staging ui/console: message surface tweaks. ui/cocoa: bugfixes and cleanups. # gpg: Signature made Thu 04 Mar 2021 08:36:53 GMT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20210304-pull-request: virtio-gpu: Do not distinguish the primary console ui/console: Pass placeholder surface to displays ui/console: Add placeholder flag to message surface ui/cocoa: Replace fprintf with error_report configure: Improve OpenGL dependency detections ui/cocoa: Fix stride resolution of pixman image ui/gtk: vte: fix sending multiple characeters ui/cocoa: Remove the uses of full screen APIs Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04Merge remote-tracking branch ↵Peter Maydell2-1/+80
'remotes/dgilbert-gitlab/tags/pull-virtiofs-20210304' into staging virtiofs minor security fix Fix xattrmap to drop remapped security.capability capabilities. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> # gpg: Signature made Thu 04 Mar 2021 10:36:45 GMT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] # Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A 9FA9 0516 331E BC5B FDE7 * remotes/dgilbert-gitlab/tags/pull-virtiofs-20210304: virtiofs: drop remapped security.capability xattr as needed Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-03-04virtiofs: drop remapped security.capability xattr as neededDr. David Alan Gilbert2-1/+80
On Linux, the 'security.capability' xattr holds a set of capabilities that can change when an executable is run, giving a limited form of privilege escalation to those programs that the writer of the file deemed worthy. Any write causes the 'security.capability' xattr to be dropped, stopping anyone from gaining privilege by modifying a blessed file. Fuse relies on the daemon to do this dropping, and in turn the daemon relies on the host kernel to drop the xattr for it. However, with the addition of -o xattrmap, the xattr that the guest stores its capabilities in is now not the same as the one that the host kernel automatically clears. Where the mapping changes 'security.capability', explicitly clear the remapped name to preserve the same behaviour. This bug is assigned CVE-2021-20263. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Vivek Goyal <vgoyal@redhat.com>
2021-03-04vfio-ccw: Do not read region ret_code after writeEric Farman1-6/+6
A pwrite() call returns the number of bytes written (or -1 on error), and vfio-ccw compares this number with the size of the region to determine if an error had occurred or not. If they are not equal, this is a failure and the errno is used to determine exactly how things failed. An errno of zero is possible (though unlikely) in this situation and would be translated to a successful operation. If they ARE equal, the ret_code field is read from the region to determine how to proceed. While the kernel sets the ret_code field as necessary, the region and thus this field is not "written back" to the user. So the value can only be what it was initialized to, which is zero. So, let's convert an unexpected length with errno of zero to a return code of -EFAULT, and explicitly set an expected length to a return code of zero. This will be a little safer and clearer. Suggested-by: Matthew Rosato <mjrosato@linux.ibm.com> Signed-off-by: Eric Farman <farman@linux.ibm.com> Message-Id: <20210303160739.2179378-1-farman@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04css: SCHIB measurement block origin must be alignedPierre Morel1-0/+6
The Measurement Block Origin inside the SCHIB is used when Measurement Block format 1 is in used and must be aligned on 64 bytes otherwise an operand exception is recognized when issuing the Modify Sub CHannel (MSCH) instruction. Signed-off-by: Pierre Morel <pmorel@linux.ibm.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <1613741973-3711-2-git-send-email-pmorel@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04virtio-ccw: commands on revision-less devicesCornelia Huck1-7/+14
The virtio standard specifies that any non-transitional device must reject commands prior to revision setting (which we do). Devices that are transitional need to assume revision 0 (legacy) if the driver sends a non-revision-setting command first in order to support legacy drivers. We neglected to do the latter. Fortunately, nearly everything worked as intended anyway; the only problem was not properly rejecting revision setting after some other command had been issued. Easy to fix by setting revision to 0 if we see a non-revision command on a legacy-capable revision-less device. Found by code inspection, not observed in the wild. Signed-off-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Halil Pasic <pasic@linux.ibm.com> Message-Id: <20210216111830.1087847-1-cohuck@redhat.com>
2021-03-04s390x/pci: restore missing Query PCI Function CLP dataMatthew Rosato1-0/+5
Some CLP response data was accidentally dropped when fixing endianness issues with the Query PCI Function CLP response. All of these values are sent as 0s to the guest for emulated devices, so the impact is only observed on passthrough devices. Fixes: a4e2fff1b104 ("s390x/pci: fix endianness issues") Signed-off-by: Matthew Rosato <mjrosato@linux.ibm.com> Message-Id: <1613681609-9349-1-git-send-email-mjrosato@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04hw/s390x: fix build for virtio-9p-ccwHalil Pasic1-1/+3
Commit 2c44220d05 ("meson: convert hw/arch*"), which migrated the old Makefile.objs to meson.build accidentally excluded virtio-ccw-9p.c and thus the virtio-9p-ccw device from the build (and potentially also included the file virtio-ccw-blk.c twice in the source set). And since CONFIG_VIRTFS can't be used the way it was used here (see commit 2c9dce0196 ("meson: do not use CONFIG_VIRTFS")), the preconditions have to be written differently. Let's fix this! Signed-off-by: Halil Pasic <pasic@linux.ibm.com> Fixes: 2c44220d05 ("meson: convert hw/arch*") Reported-by: Jakob Naucke <jakob.naucke@ibm.com> Cc: qemu-stable@nongnu.org Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210218034059.1096078-1-pasic@linux.ibm.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2021-03-04target/s390x/arch_dump: Fix warning for the name field in the PT_NOTE sectionThomas Huth1-1/+3
There is a compiler warning with GCC 9.3 when compiling with the -fsanitize=thread compiler flag: In function 'strncpy', inlined from 's390x_write_elf64_notes' at ../target/s390x/arch_dump.c:219:9: /usr/include/x86_64-linux-gnu/bits/string_fortified.h:106:10: error: '__builtin_strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation] Since the name should always be NUL-terminated, let's use g_strlcpy() to silence this warning. And while we're at it, also add an assert() to make sure that the provided names always fit the size field (which is fine for the current callers, the function is called once with "CORE" and once with "LINUX" as a name). Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com> Message-Id: <20210205093921.848260-1-thuth@redhat.com> Signed-off-by: Cornelia Huck <cohuck@redhat.com>
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