riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2022-05-25	hw/gpio: replace HWADDR_PRIx with PRIx64	Jamin Lin	2	-5/+5
2022-05-25	hw/gpio support GPIO index mode for write operation.	Jamin Lin	2	-0/+182
2022-05-25	hw/gpio: Add ASPEED GPIO model for AST1030	Jamin Lin	2	-0/+38
2022-05-25	hw/gpio Add GPIO read/write trace event.	Jamin Lin	2	-15/+43
2022-05-25	hw: aspeed: Init all UART's with serial devices	Peter Delevoryas	1	-0/+9
2022-05-25	hw: aspeed: Introduce common UART init function	Peter Delevoryas	4	-14/+17
2022-05-25	hw: aspeed: Ensure AST1030 respects uart-default	Peter Delevoryas	1	-3/+3
2022-05-25	hw: aspeed: Add uarts_num SoC attribute	Peter Delevoryas	4	-0/+5
2022-05-25	hw: aspeed: Add missing UART's	Peter Delevoryas	4	-0/+57
2022-05-25	aspeed: Introduce a get_irq AspeedSoCClass method	Cédric Le Goater	4	-7/+19
2022-05-25	hw: m25p80: allow write_enable latch get/set	Iris Chen	5	-32/+98
2022-05-25	docs: aspeed: Add fby35 board	Peter Delevoryas	1	-0/+1
2022-05-25	hw/arm/aspeed: Add fby35 machine type	Peter Delevoryas	1	-0/+63
2022-05-25	docs: add minibmc section in aspeed document	Jamin Lin	1	-0/+61
2022-05-24	Merge tag 'pull-riscv-to-apply-20220525' of github.com:alistair23/qemu into s...	Richard Henderson	15	-209/+325
2022-05-24	hw/core: loader: Set is_linux to true for VxWorks uImage	Bin Meng	1	-0/+15
2022-05-24	hw/core: Sync uboot_image.h from U-Boot v2022.01	Bin Meng	1	-71/+142
2022-05-24	target/riscv: add zicsr/zifencei to isa_string	Hongren (Zenithal) Zheng	1	-0/+2
2022-05-24	hw/riscv: virt: Fix interrupt parent for dynamic platform devices	Anup Patel	1	-13/+12
2022-05-24	target/riscv: Set [m\|s]tval for both illegal and virtual instruction traps	Anup Patel	4	-5/+23
2022-05-24	target/riscv: Fix hstatus.GVA bit setting for traps taken from HS-mode	Anup Patel	1	-2/+1
2022-05-24	target/riscv: Fix csr number based privilege checking	Anup Patel	1	-2/+6
2022-05-24	target/riscv: Fix typo of mimpid cpu option	Frank Chang	3	-7/+7
2022-05-24	target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize	Weiwei Li	1	-12/+12
2022-05-24	hw/riscv/sifive_u: Resolve redundant property accessors	Bernhard Beschow	1	-20/+4
2022-05-24	hw/vfio/pci-quirks: Resolve redundant property getters	Bernhard Beschow	1	-25/+9
2022-05-24	target/riscv: Move/refactor ISA extension checks	Tsukasa OI	1	-15/+16
2022-05-24	target/riscv: FP extension requirements	Tsukasa OI	1	-0/+25
2022-05-24	target/riscv: Change "G" expansion	Tsukasa OI	1	-2/+5
2022-05-24	target/riscv: Disable "G" by default	Tsukasa OI	1	-1/+1
2022-05-24	target/riscv: Fix coding style on "G" expansion	Tsukasa OI	1	-2/+2
2022-05-24	hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan)	Tsukasa OI	3	-4/+4
2022-05-24	hw/riscv: Make CPU config error handling generous (virt/spike)	Tsukasa OI	2	-2/+2
2022-05-24	target/riscv: Add short-isa-string option	Tsukasa OI	2	-1/+7
2022-05-24	target/riscv: Move Zhinx* extensions on ISA string	Tsukasa OI	1	-2/+2
2022-05-24	hw/intc: Pass correct hartid while updating mtimecmp	Atish Patra	1	-1/+2
2022-05-24	target/riscv: rvv: Fix early exit condition for whole register load/store	eopXD	1	-27/+31
2022-05-24	target/riscv: Fix VS mode hypervisor CSR access	Dylan Reid	1	-5/+5
2022-05-23	linux-user/host/s390: Treat EX and EXRL as writes	Ilya Leoshkevich	1	-0/+7
2022-05-23	tests/tcg/s390x: Test unwinding from signal handlers	Ilya Leoshkevich	1	-14/+55
2022-05-23	linux-user/s390x: Fix unwinding from signal handlers	Ilya Leoshkevich	1	-0/+5
2022-05-23	linux-user: Remove pointless CPU{ARCH}State casts	Philippe Mathieu-Daudé	3	-28/+25
2022-05-23	linux-user: Have do_syscall() use CPUArchState* instead of void*	Philippe Mathieu-Daudé	6	-129/+129
2022-05-23	linux-user/elfload: Remove pointless non-const CPUArchState cast	Philippe Mathieu-Daudé	1	-1/+1
2022-05-23	linux-user/syscall.c: fix build without RLIMIT_RTTIME	Fabrice Fontaine	1	-0/+2
2022-05-23	hostmem: default the amount of prealloc-threads to smp-cpus	Jaroslav Jindrak	1	-1/+1
2022-05-23	target/i386: Remove LBREn bit check when access Arch LBR MSRs	Yang Weijiang	1	-12/+9
2022-05-23	linux-user: Clean up arg_start/arg_end confusion	Richard Henderson	5	-14/+28
2022-05-20	Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into sta...	Richard Henderson	20	-329/+59
2022-05-19	Merge tag 'pull-target-arm-20220519' of https://git.linaro.org/people/pmaydel...	Richard Henderson	46	-228/+697