aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2012-11-01Merge remote-tracking branch 'stefanha/net' into stagingAnthony Liguori3-7/+21
* stefanha/net: e1000: pre-initialize RAH/RAL registers net: Reject non-netdevs in qmp_netdev_del() net: use "socket" model name for UDP sockets e1000: drop check_rxov, always treat RX ring with RDH == RDT as empty Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-11-01Merge remote-tracking branch 'bonzini/threadpool' into stagingAnthony Liguori49-1489/+2429
* bonzini/threadpool: (39 commits) raw-win32: implement native asynchronous I/O raw-posix: move linux-aio.c to block/ raw-win32: add emulated AIO support raw-posix: rename raw-posix-aio.h, hide unavailable prototypes raw: merge posix-aio-compat.c into block/raw-posix.c block: switch posix-aio-compat to threadpool threadpool: do not take lock in event_notifier_ready aio: add generic thread-pool facility qemu-thread: add QemuSemaphore linux-aio: use event notifiers aio: clean up now-unused functions main-loop: use aio_notify for qemu_notify_event main-loop: use GSource to poll AIO file descriptors aio: call aio_notify after setting I/O handlers aio: add aio_notify aio: make AioContexts GSources aio: add Win32 implementation aio: prepare for introducing GSource-based dispatch aio: add non-blocking variant of aio_wait aio: test node->deleted before calling io_flush ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-11-01Merge remote-tracking branch 'qemu-kvm/uq/master' into stagingAnthony Liguori9-93/+242
* qemu-kvm/uq/master: (28 commits) update-linux-headers.sh: Handle new kernel uapi/ directories target-i386: kvm_cpu_fill_host: use GET_SUPPORTED_CPUID target-i386: cpu: make -cpu host/check/enforce code KVM-specific target-i386: make cpu_x86_fill_host() void Emulate qemu-kvms -no-kvm option Issue warning when deprecated -tdf option is used Issue warning when deprecated drive parameter boot=on|off is used Use global properties to emulate -no-kvm-pit-reinjection Issue warning when deprecated -no-kvm-pit is used Use machine options to emulate -no-kvm-irqchip cirrus_vga: allow configurable vram size target-i386: Add missing kvm cpuid feature name i386: cpu: add missing CPUID[EAX=7,ECX=0] flag names i386: kvm: filter CPUID leaf 7 based on GET_SUPPORTED_CPUID, too i386: kvm: reformat filter_features_for_kvm() code i386: kvm: filter CPUID feature words earlier, on cpu.c i386: kvm: mask cpuid_ext4_features bits earlier i386: kvm: mask cpuid_kvm_features earlier i386: kvm: x2apic is not supported without in-kernel irqchip i386: kvm: set CPUID_EXT_TSC_DEADLINE_TIMER on kvm_arch_get_supported_cpuid() ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-11-01Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori52-334/+501
* afaerber/qom-cpu: (35 commits) target-i386: Pass X86CPU to kvm_handle_halt() target-i386: Pass X86CPU to kvm_get_mp_state() cpu: Move thread_id to CPUState cpus: Pass CPUState to run_on_cpu() target-i386: Pass X86CPU to cpu_x86_inject_mce() target-i386: Pass X86CPU to kvm_mce_inject() cpus: Pass CPUState to [qemu_]cpu_has_work() spapr: Pass PowerPCCPU to hypercalls spapr: Pass PowerPCCPU to spapr_hypercall() target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall target-ppc: Pass PowerPCCPU to powerpc_excp() xtensa_pic: Pass XtensaCPU to xtensa_ccompare_cb() cpus: Pass CPUState to qemu_wait_io_event_common() cpus: Pass CPUState to flush_queued_work() cpu: Move queued_work_{first,last} to CPUState cpus: Pass CPUState to qemu_cpu_kick() target-ppc: Rename kvm_kick_{env => cpu} and pass PowerPCCPU ppc: Pass PowerPCCPU to {ppc6xx,ppc970,power7,ppc40x,ppce500}_set_irq() cpus: Pass CPUState to qemu_tcg_init_vcpu() cpus: Pass CPUState to qemu_tcg_cpu_thread_fn ... Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-11-01arm_boot: Change initrd load address to "halfway through RAM"Peter Maydell2-15/+26
To avoid continually having to bump the initrd load address to account for larger kernel images, put the initrd halfway through RAM. This allows large kernels on new boards with lots of RAM to work OK, without breaking existing usecases for boards with only 32MB of RAM. Note that this change fixes in passing a bug where we were passing an overly large max_size to load_image_targphys() for the initrd, which meant that we wouldn't correctly refuse to load an enormous initrd that didn't actually fit into RAM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com> Tested-by: Cole Robinson <crobinso@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-11-01Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agrafAurelien Jarno6-26/+79
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: pseries: Cleanup duplications of ics_valid_irq() code pseries: Clean up inconsistent variable name in xics.c target-ppc: Extend FPU state for newer POWER CPUs target-ppc: Rework storage of VPA registration state Revert "PPC: pseries: Remove hack for PIO window"
2012-11-01Merge branch 'arm-devs.for-upstream' of ↵Aurelien Jarno26-429/+541
git://git.linaro.org/people/pmaydell/qemu-arm * 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: (28 commits) hw/sd.c: add SD card save/load support vmstate: Add support for saving/loading bitmaps hw/sd.c: Fix erase for high capacity cards pflash_cfi01: Fix debug mode printfery pflash_cfi0x: QOMified pflash_cfi01: remove unused total_len field pflash_cfi0x: remove unused base field hw/versatile_i2c: Use LOG_GUEST_ERROR hw/arm_l2x0: Use LOG_GUEST_ERROR hw/arm_sysctl: Use LOG_GUEST_ERROR hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMP hw/arm_timer: Use LOG_GUEST_ERROR and LOG_UNIMP hw/arm_gic: Use LOG_GUEST_ERROR hw/arm11mpcore: Use LOG_GUEST_ERROR rather than hw_error() hw/pl190: Use LOG_UNIMP rather than hw_error() hw/pl110: Use LOG_GUEST_ERROR rather than hw_error() hw/pl080: Use LOG_GUEST_ERROR and LOG_UNIMP hw/pl061: Use LOG_GUEST_ERROR hw/pl050: Use LOG_GUEST_ERROR hw/exynos4_boards: Don't prematurely explode QEMUMachineInitArgs ...
2012-11-01pseries: Cleanup duplications of ics_valid_irq() codeDavid Gibson1-4/+2
A couple of places in xics.c open-coded the same logic as is already implemented in ics_valid_irq(). This patch fixes the code duplication. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-01pseries: Clean up inconsistent variable name in xics.cDavid Gibson1-3/+3
Throughout xics.c 'nr' is used to refer to a global interrupt number, and 'server' is used to refer to an interrupt server number (i.e. CPU number). Except in icp_set_mfrr(), where 'nr' is used as a server number. Fix this confusing inconsistency. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-01target-ppc: Extend FPU state for newer POWER CPUsDavid Gibson3-14/+27
This patch adds some extra FPU state to CPUPPCState. Specifically, fpscr is extended to a target_ulong bits, since some recent (64 bit) CPUs now have more status bits than fit inside 32 bits. Also, we add the 32 VSR registers present on CPUs with VSX (these extend the standard FP regs, which together with the Altivec/VMX registers form a 64 x 128bit register file for VSX). We don't actually support the instructions using these extra registers in TCG yet, but we still need a place to store the state so we can sync it with KVM and savevm/loadvm it. This patch updates the savevm code to not fail on the extended state, but also does not actually save it - that's a project for another patch. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-01target-ppc: Rework storage of VPA registration stateDavid Gibson1-3/+3
We change the storage of the VPA information to explicitly use fixed size integer types which will make life easier for syncing this data with KVM, which we will need in future. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix commit message] Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-01Revert "PPC: pseries: Remove hack for PIO window"David Gibson2-2/+44
This reverts commit a178274efabcbbc5d44805b51def874e47051325. Contrary to that commit's message, the users of old_portio are not all gone. In particular VGA still uses it via portio_list_add(). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-01e1000: pre-initialize RAH/RAL registersGabriel L. Somlo1-0/+10
Some guest operating systems' drivers (Mac OS X in particular) fail to properly initialize the Receive Address registers (probably expecting them to be pre-initialized by an earlier component, such as a specific proprietary BIOS). This patch pre-initializes the RA registers, allowing OS X networking to function properly. Other guest operating systems are not affected, and free to (re)initialize these registers during boot. [According to the datasheet the Address Valid bits in the RA registers are cleared on PCI or software reset. This patch adds the NIC's MAC address and sets Address Valid on reset. So we diverge from real hardware behavior here. -- Stefan] Signed-off-by: Gabriel Somlo <somlo@cmu.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-11-01net: Reject non-netdevs in qmp_netdev_del()Stefan Hajnoczi1-1/+8
The netdev_del command crashes when given a -net device, because it calls qemu_opts_del(NULL). Check that this is a -netdev before attempting to delete it and the QemuOpts. Note the subtle change from qemu_find_opts_err("netdev", errp) to qemu_find_opts_err("netdev", NULL). Since "netdev" is a built in options group and we don't check for NULL return anyway, there's no use in passing errp here. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-11-01net: use "socket" model name for UDP socketsLei Li1-1/+1
Fix the problem that can not delete the udp socket. It's caused by passing "udp" model to net_socket_udp_init, but we do not have "udp" model in our model list. Pass the right model "socket" to init function. https://bugs.launchpad.net/qemu/+bug/1073585?comments=all Signed-off-by: Lei Li <lilei@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-11-01e1000: drop check_rxov, always treat RX ring with RDH == RDT as emptyDmitry Fleytman1-5/+2
Real HW always treats RX ring with RDH == RDT as empty. Emulation is supposed to behave the same. Reported-by: Chris Webb <chris.webb@elastichosts.com> Reported-by: Richard Davies <richard.davies@elastichosts.com> Signed-off-by: Dmitry Fleytman <dmitry@daynix.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-10-31target-mips: don't flush extra TLB on permissions upgradeAurelien Jarno1-5/+23
If the guest uses a TLBWI instruction for upgrading permissions, we don't need to flush the extra TLBs. This improve boot time performance by about 10%. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: fix TLBR wrt SEGMaskAurelien Jarno1-0/+6
Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the address. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: use deposit instead of hardcoded versionAurelien Jarno1-28/+4
Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. At the same time remove the (lsb > msb) test. The MIPS64R2 instruction set manual says "Because of the instruction format, lsb can never be greater than msb, so there is no UNPREDICATABLE case for this instruction." (Bug reported as LP:1071149.) Cc: Никита Канунников <n.kanunnikov@sbtcom.ru> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno1-48/+37
The result of a division by 0, or a division of INT_MIN by -1 in the signed case, is unpredictable. Just replace 0 by 1 in that case so that it doesn't trigger a floating point exception on the host. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: implement movn/movz using movcondAurelien Jarno1-15/+12
Avoid the branches in movn/movz implementation and replace them with movcond. Also update a wrong command. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: don't use local temps for store conditionalAurelien Jarno1-5/+6
Store conditional operations only need local temps in user mode. Fix the code to use temp local only in user mode, this spares two memory stores in system mode. At the same time remove a wrong a wrong copied & pasted comment, store operations don't have a register destination. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: implement unaligned loads using TCGAurelien Jarno3-159/+62
Load/store from helpers should be avoided as they are quite inefficient. Rewrite unaligned loads instructions using TCG and aligned loads. The number of actual loads operations to implement an unaligned load instruction is reduced from up to 8 to 1. Note: As we can't rely on shift by 32 or 64 undefined behaviour, the code loads already shift by one constants. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: simplify load/store microMIPS helpersAurelien Jarno1-64/+9
load/store microMIPS helpers are reinventing the wheel. Call do_lw, do_ll, do_sw and do_sl instead of using a macro calling the cpu_* load/store functions. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: optimize load operationsAurelien Jarno1-4/+12
Only allocate t1 when needed. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: cleanup load/store operationsAurelien Jarno1-64/+35
Load/store operations use macros for historical reasons. Now that there is no point in keeping them, replace them by direct calls to qemu_ld/st. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: restore CPU state after an FPU exceptionAurelien Jarno1-90/+95
Rework *raise_exception*() functions so that they can be called from other helpers, passing the return address as an argument. Use do_raise_exception() function in update_fcr31() to correctly restore the CPU state after an FPU exception. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: use softfloat constants when possibleAurelien Jarno1-48/+44
softfloat already has a few constants defined, use them instead of redefining them in target-mips. Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and FP_TO_INT64_OVERFLOW as even if they have the same value, they are technically different (and defined differently in the MIPS ISA). Remove the unused constants. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: cleanup float to int conversion helpersAurelien Jarno1-39/+79
Instead of accessing the flags from the floating point control register after updating it, read the softfloat flags. This is just code cleanup and should not change the behaviour. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: fix FPU exceptionsAurelien Jarno1-13/+19
For each FPU instruction that can trigger an FPU exception, to call call update_fcr31() after. Remove the manual NaN assignment in case of float to float operation, as softfloat is already taking care of that. However for float to int operation, the value has to be changed to the MIPS one. In the cvtpw_ps case, the two registers have to be handled separately to guarantee a correct final value in both registers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno1-63/+10
Instead of clearing the softfloat exception flags before each floating point instruction, reset them to 0 in update_fcr31() when an exception is detected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno3-105/+64
Use the new softfloat floatXX_muladd() functions to implement the madd, msub, nmadd and nmsub instructions. At the same time replace the name of the helpers by the name of the instruction, as the only reason for the previous names was to keep the macros simple. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31softfloat: implement fused multiply-add NaN propagation for MIPSAurelien Jarno1-0/+27
Add a pickNaNMulAdd function for MIPS, implementing NaN propagation rules for MIPS fused multiply-add instructions. Cc: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: do not save CPU state when using retranslationAurelien Jarno1-20/+0
When the CPU state after a possible retranslation is going to be handled through code retranslation, we don't need to save the CPU state before. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: correctly restore btarget upon exceptionAurelien Jarno1-0/+11
When the CPU state is restored through retranslation after an exception, btarget should also be restored. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31tcg: don't remove op if output needs to be synced to memoryAurelien Jarno1-4/+4
Commit 9c43b68de628a1e2cba556adfb71c17028eb802e do not correctly check for dead outputs when they need to be synced to memory in case of half-dead operations. Fix that by applying the same pattern than for the default case. Tested-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-alpha: Use TCG_CALL_NO_WGRichard Henderson1-10/+10
Mark helper functions that raise exceptions, but otherwise do not change TCG register state, with TCG_CALL_NO_WG. Signed-off-by: Richard Henderson <rth@twiddle.net>
2012-10-31chardev: Use timer instead of bottom-half to postpone open eventJan Kiszka3-12/+13
As the block layer may decide to flush bottom-halfs while the machine is still initializing (e.g. to read geometry data from the disk), our postponed open event may be processed before the last frontend registered with a muxed chardev. Until the semantics of BHs have been clarified, use an expired timer to achieve the same effect (suggested by Paolo Bonzini). This requires to perform the alarm timer initialization earlier as otherwise timer subsystem can be used before being ready. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
2012-10-31target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno1-36/+0
All switch() decoding instruction have a default entry, so it is possible to have unused enum entries. Remove conditional definitions of MIPS64 opcode enums, as it only makes the code less readable. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Change TODO fileJia Liu1-2/+1
Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP testcasesJia Liu487-0/+19151
Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP processorsJia Liu1-0/+52
Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP accumulator instructionsJia Liu3-0/+995
Add MIPS ASE DSP Accumulator and DSPControl Access instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP compare-pick instructionsJia Liu3-0/+635
Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP bit/manipulation instructionsJia Liu3-0/+311
Add MIPS ASE DSP Bit/Manipulation instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP multiply instructionsJia Liu3-0/+1499
Add MIPS ASE DSP Multiply instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP GPR-based shift instructionsJia Liu3-0/+618
Add MIPS ASE DSP GPR-Based Shift instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP arithmetic instructionsJia Liu3-3/+1812
Add MIPS ASE DSP Arithmetic instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP load instructionsJia Liu1-0/+88
Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-31target-mips: Add ASE DSP branch instructionsJia Liu1-0/+36
Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
generated by cgit v1.1 at 2024-12-29 05:17:33 +0000