| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-10-25 | target/sparc: Move UDIV, SDIV to decodetree | Richard Henderson | 3 | -33/+27 |
| 2023-10-25 | target/sparc: Move UDIVX, SDIVX to decodetree | Richard Henderson | 2 | -9/+18 |
| 2023-10-25 | target/sparc: Move SUBC to decodetree | Richard Henderson | 2 | -50/+90 |
| 2023-10-25 | target/sparc: Move UMUL, SMUL to decodetree | Richard Henderson | 2 | -18/+6 |
| 2023-10-25 | target/sparc: Move MULX to decodetree | Richard Henderson | 2 | -5/+6 |
| 2023-10-25 | target/sparc: Move ADDC to decodetree | Richard Henderson | 2 | -55/+94 |
| 2023-10-25 | target/sparc: Move basic arithmetic to decodetree | Richard Henderson | 2 | -103/+94 |
| 2023-10-25 | target/sparc: Remove cpu_hintp, cpu_htba, cpu_hver, cpu_ssr, cpu_ver | Richard Henderson | 1 | -19/+13 |
| 2023-10-25 | target/sparc: Remove cpu_tick_cmpr, cpu_stick_cmpr, cpu_hstick_cmpr | Richard Henderson | 1 | -27/+14 |
| 2023-10-25 | target/sparc: Remove cpu_wim | Richard Henderson | 1 | -6/+8 |
| 2023-10-25 | target/sparc: Move WRTBR, WRHPR to decodetree | Richard Henderson | 2 | -54/+66 |
| 2023-10-25 | target/sparc: Move WRWIM, WRPR to decodetree | Richard Henderson | 2 | -136/+200 |
| 2023-10-25 | target/sparc: Move WRPSR, SAVED, RESTORED to decodetree | Richard Henderson | 2 | -33/+39 |
| 2023-10-25 | target/sparc: Move WRASR to decodetree | Richard Henderson | 2 | -156/+216 |
| 2023-10-25 | target/sparc: Move RDTBR, FLUSHW to decodetree | Richard Henderson | 2 | -12/+16 |
| 2023-10-25 | target/sparc: Move RDWIM, RDPR to decodetree | Richard Henderson | 2 | -138/+204 |
| 2023-10-25 | target/sparc: Move RDPSR, RDHPR to decodetree | Richard Henderson | 2 | -43/+83 |
| 2023-10-25 | target/sparc: Move RDASR, STBAR, MEMBAR to decodetree | Richard Henderson | 2 | -129/+235 |
| 2023-10-25 | target/sparc: Move Tcc to decodetree | Richard Henderson | 2 | -79/+89 |
| 2023-10-25 | target/sparc: Move SETHI to decodetree | Richard Henderson | 2 | -35/+21 |
| 2023-10-25 | target/sparc: Pass DisasCompare to advance_jump_cond | Richard Henderson | 1 | -18/+13 |
| 2023-10-25 | target/sparc: Merge gen_branch_[an] with only caller | Richard Henderson | 1 | -43/+30 |
| 2023-10-25 | target/sparc: Merge gen_fcond with only caller | Richard Henderson | 1 | -14/+8 |
| 2023-10-25 | target/sparc: Merge gen_cond with only caller | Richard Henderson | 1 | -15/+8 |
| 2023-10-25 | target/sparc: Move FBPfcc and FBfcc to decodetree | Richard Henderson | 2 | -63/+43 |
| 2023-10-25 | target/sparc: Move BPr to decodetree | Richard Henderson | 2 | -41/+25 |
| 2023-10-25 | target/sparc: Move BPcc and Bicc to decodetree | Richard Henderson | 2 | -60/+61 |
| 2023-10-25 | target/sparc: Move CALL to decodetree | Richard Henderson | 2 | -17/+18 |
| 2023-10-25 | target/sparc: Define AM_CHECK for sparc32 | Richard Henderson | 1 | -12/+9 |
| 2023-10-25 | target/sparc: Add decodetree infrastructure | Richard Henderson | 3 | -22/+55 |
| 2023-10-25 | target/sparc: Partition cpu features | Richard Henderson | 1 | -15/+21 |
| 2023-10-25 | target/sparc: Remove sparcv7 cpu features | Richard Henderson | 5 | -57/+11 |
| 2023-10-25 | target/sparc: Use CPU_FEATURE_BIT_* for cpu properties | Richard Henderson | 1 | -28/+44 |
| 2023-10-25 | target/sparc: Define features via cpu-feature.h.inc | Richard Henderson | 2 | -19/+32 |
| 2023-10-25 | configs: Enable MTTCG for sparc, sparc64 | Richard Henderson | 2 | -0/+2 |
| 2023-10-25 | target/sparc: Set TCG_GUEST_DEFAULT_MO | Richard Henderson | 1 | -0/+23 |
| 2023-10-25 | target/sparc: Avoid helper_raise_exception in helper_st_asi | Richard Henderson | 1 | -4/+6 |
| 2023-10-25 | target/sparc: Implement check_align inline | Richard Henderson | 3 | -15/+61 |
| 2023-10-25 | target/sparc: Clear may_lookup for npc == DYNAMIC_PC | Richard Henderson | 1 | -3/+17 |
| 2023-10-25 | hw/arm/aspeed: Move AspeedSoCState::cpu/vic to Aspeed2400SoCState | Philippe Mathieu-Daudé | 3 | -15/+19 |
| 2023-10-25 | hw/arm/aspeed: Move AspeedSoCState::a7mpcore to Aspeed2600SoCState | Philippe Mathieu-Daudé | 3 | -30/+37 |
| 2023-10-25 | hw/arm/aspeed: Move AspeedSoCState::armv7m to Aspeed10x0SoCState | Philippe Mathieu-Daudé | 3 | -20/+25 |
| 2023-10-25 | hw/arm/aspeed: Check 'memory' link is set in common aspeed_soc_realize | Philippe Mathieu-Daudé | 1 | -0/+11 |
| 2023-10-25 | hw/arm/aspeed: Introduce TYPE_ASPEED2400_SOC | Philippe Mathieu-Daudé | 3 | -44/+53 |
| 2023-10-25 | hw/arm/aspeed: Introduce TYPE_ASPEED2600_SOC | Philippe Mathieu-Daudé | 2 | -13/+20 |
| 2023-10-25 | hw/arm/aspeed: Introduce TYPE_ASPEED10X0_SOC | Philippe Mathieu-Daudé | 2 | -13/+20 |
| 2023-10-25 | hw/arm/aspeed: Dynamically allocate AspeedMachineState::soc field | Philippe Mathieu-Daudé | 1 | -49/+52 |
| 2023-10-25 | hw/arm/aspeed: Rename aspeed_soc_realize() as AST2400/2500 specific | Philippe Mathieu-Daudé | 1 | -4/+11 |
| 2023-10-25 | hw/arm/aspeed: Rename aspeed_soc_init() as AST2400/2500 specific | Philippe Mathieu-Daudé | 1 | -3/+3 |
| 2023-10-25 | hw/arm/aspeed: Extract code common to all boards to a common file | Philippe Mathieu-Daudé | 3 | -96/+115 |
