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- Byte swapping for internal GT64XXX registers is controlled by the bit
12 of the Configuration Register and not by the PCI Internal Command
register.
- The bit 0 of the PCI Internal Command register controls byte swapping
for PCI access *except for the internal PCI device*, that is when both
bus and device numbers are 0.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4035 c046a42c-6fe2-441c-8c8c-71466251a162
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The patch below fixes the computation of FPSCR_VX and FPSCR_FEX when
using the mtfsf instruction. As stated in the PowerPC manual the mtfsf
instruction can't alter those bit, and thus it should always be
computed.
Acked by Jocelyn Mayer.
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According to the Intel 82540EM manual, the mmio space is
128k size.
Copied from Xen list and noted by tina..yang@oracle.com
Signed-off-by: Dor Laor <dor.laor@qumranet.com>
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sources if no valid clock name has been specified.
(Hervé Poussineau)
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Rename omap files to better reflect OMAP1-specific parts.
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* Save $mof across signals.
* Cleaned up frame accesses.
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* target-cris/helper.c: Update ERP for user-mode simulation aswell.
* hw/etraxfs_timer.c: Support multiple timers.
* hw/etraxfs_ser.c: Multiple ports, the data just goes to stdout.
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issue where QEMU finds an illegal CRIS insn while the guest is returning through a signal return trampoline.
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git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3994 c046a42c-6fe2-441c-8c8c-71466251a162
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depend on it.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3993 c046a42c-6fe2-441c-8c8c-71466251a162
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