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2018-06-22hw/arm/iotkit: Wire up MPC interrupt linesPeter Maydell2-0/+80
The interrupt outputs from the MPC in the IoTKit and the expansion MPCs in the board must be wired up to the security controller, and also all ORed together to produce a single line to the NVIC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180620132032.28865-8-peter.maydell@linaro.org
2018-06-22hw/arm/iotkit: Instantiate MPCPeter Maydell2-11/+29
Wire up the one MPC that is part of the IoTKit itself. For the moment we don't wire up its interrupt line. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 20180620132032.28865-7-peter.maydell@linaro.org
2018-06-22hw/misc/iotkit-secctl.c: Implement SECMPCINTSTATUSPeter Maydell2-2/+44
Implement the SECMPCINTSTATUS register. This is the only register in the security controller that deals with Memory Protection Controllers, and it simply provides a read-only view of the interrupt lines from the various MPCs in the system. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180620132032.28865-6-peter.maydell@linaro.org
2018-06-22hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translatePeter Maydell2-2/+52
The final part of the Memory Protection Controller we need to implement is actually using the BLK_LUT data programmed by the guest to determine whether to block the transaction or not. Since this means we now change transaction mappings when the guest writes to BLK_LUT, we must also call the IOMMU notifiers at that point. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-5-peter.maydell@linaro.org
2018-06-22hw/misc/tz-mpc.c: Implement correct blocked-access behaviourPeter Maydell1-2/+48
The MPC is guest-configurable for whether blocked accesses: * should be RAZ/WI or cause a bus error * should generate an interrupt or not Implement this behaviour in the blocked-access handlers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-4-peter.maydell@linaro.org
2018-06-22hw/misc/tz-mpc.c: Implement registersPeter Maydell2-3/+147
Implement the missing registers for the TZ MPC. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-3-peter.maydell@linaro.org
2018-06-22hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection ControllerPeter Maydell6-0/+480
Implement the Arm TrustZone Memory Protection Controller, which sits in front of RAM and allows secure software to configure it to either pass through or reject transactions. We implement the MPC as a QEMU IOMMU, which will direct transactions either through to the devices and memory behind it or to a special "never works" AddressSpace if they are blocked. This initial commit implements the skeleton of the device: * it always permits accesses * it doesn't implement most of the registers * it doesn't implement the interrupt or other behaviour for blocked transactions Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Auger <eric.auger@redhat.com> Message-id: 20180620132032.28865-2-peter.maydell@linaro.org
2018-06-22xlnx-zynqmp: Swap Cortex-R5 for Cortex-R5FEdgar E. Iglesias2-2/+2
The ZynqMP has Cortex-R5Fs with the optional FPU enabled. Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180529124707.3025-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22target-arm: Add the Cortex-R5FEdgar E. Iglesias1-0/+9
Add the Cortex-R5F with the optional FPU enabled. Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180529124707.3025-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt: Increase max_cpus to 512Eric Auger1-3/+4
virt 3.0 now allows up to 512 vcpus whereas for earlier machine types, max_cpus was set to 255 and any attempt to start the machine with vcpus > 255 was rejected at a very early stage, in vl.c/main level. 512 is the max supported by KVM. Anyway the actual vcpu count that can be achieved depends on other parameters such as the acceleration mode, the vgic version, the host kernel version. Those are discovered later on. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-12-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt: Use 256MB ECAM region by defaultEric Auger2-0/+11
With this patch, virt-3.0 machine uses a new 256MB ECAM region by default instead of the legacy 16MB one, if highmem is set (LPAE supported by the guest) and (!firmware_loaded || aarch64). Indeed aarch32 mode FW may not support this high ECAM region. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-11-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt: Add virt-3.0 machine typeEric Auger1-2/+13
Add virt-3.0 machine type. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-10-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt: Add a new 256MB ECAM regionEric Auger3-12/+25
This patch defines a new ECAM region located after the 256GB limit. The virt machine state is augmented with a new highmem_ecam field which guards the usage of this new ECAM region instead of the legacy 16MB one. With the highmem ECAM region, up to 256 PCIe buses can be used. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-9-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt: Register two redistributor regions when necessaryEric Auger1-1/+17
With a VGICv3 KVM device, if the number of vcpus exceeds the capacity of the legacy redistributor region (123 redistributors), we now attempt to register a second redistributor region. Up to 512 redistributors can fit in this latter on top of the 123 allowed by the legacy redistributor region. Registering this second redistributor region is possible if the host kernel supports the following VGICv3 KVM device group/attribute: KVM_DEV_ARM_VGIC_GRP_ADDR/KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION. In case the host kernel does not support the registration of several redistributor regions and the requested number of vcpus exceeds the capacity of the legacy redistributor region, the GICv3 device initialization fails with a proper error message and qemu exits. At the moment the max number of vcpus still is capped by the virt machine class max_cpus. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-8-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt-acpi-build: Advertise one or two GICR structuresEric Auger1-0/+9
Depending on the number of smp_cpus we now register one or two GICR structures. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-7-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/arm/virt: GICv3 DT node with one or two redistributor regionsEric Auger2-5/+38
This patch allows the creation of a GICv3 node with 1 or 2 redistributor regions depending on the number of smu_cpus. The second redistributor region is located just after the existing RAM region, at 256GB and contains up to up to 512 vcpus. Please refer to kernel documentation for further node details: Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.txt Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-6-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/intc/arm_gicv3_kvm: Get prepared to handle multiple redist regionsEric Auger1-3/+34
Let's check if KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION is supported. If not, we check the number of redist region is equal to 1 and use the legacy KVM_VGIC_V3_ADDR_TYPE_REDIST attribute. Otherwise we use the new attribute and allow to register multiple regions to the KVM device. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-5-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/intc/arm_gicv3: Introduce redist-region-count array propertyEric Auger5-11/+67
To prepare for multiple redistributor regions, we introduce an array of uint32_t properties that stores the redistributor count of each redistributor region. Non accelerated VGICv3 only supports a single redistributor region. The capacity of all redist regions is checked against the number of vcpus. Machvirt is updated to set those properties, ie. a single redistributor region with count set to the number of vcpus capped by 123. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Message-id: 1529072910-16156-4-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22target/arm: Allow KVM device address overwritingEric Auger5-7/+16
for KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION attribute, the attribute data pointed to by kvm_device_attr.addr is a OR of the redistributor region address and other fields such as the index of the redistributor region and the number of redistributors the region can contain. The existing machine init done notifier framework sets the address field to the actual address of the device and does not allow to OR this value with other fields. This patch extends the KVMDevice struct with a new kda_addr_ormask member. Its value is passed at registration time and OR'ed with the resolved address on kvm_arm_set_device_addr(). Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1529072910-16156-3-git-send-email-eric.auger@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22linux-headers: Update to kernel mainline commit b357bf602Eric Auger15-4/+47
Update our kernel headers to mainline commit b357bf6023a948cf6a9472f07a1b0caac0e4f8e8 ("Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm") Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1529072910-16156-2-git-send-email-eric.auger@redhat.com [PMM: clarified commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22target-arm: fix a segmentation fault due to illegal memory accessZheng Xiang1-0/+1
The elements of kvm_devices_head list are freed in kvm_arm_machine_init_done(), but we still access these illegal memory in kvm_arm_devlistener_del(). This will cause segment fault when booting guest with MALLOC_PERTURB_=1. Signed-off-by: Zheng Xiang <xiang.zheng@linaro.org> Message-id: 20180619075821.9884-1-zhengxiang9@huawei.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22target/arm: Minor cleanup for ARMv6-M 32-bit instructionsJulia Suvorova1-14/+13
The arrays were made static, "if" was simplified because V7M and V8M define V6 feature. Signed-off-by: Julia Suvorova <jusual@mail.ru> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20180618214604.6777-1-jusual@mail.ru Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22hw/intc/arm_gicv3: fix an extra left-shift when reading IPRIORITYRAmol Surati2-2/+4
When either GICD_IPRIORITYR or GICR_IPRIORITYR is read as a 32-bit register, the post left-shift operator in the for loop causes an extra shift after the least significant byte has been placed. The 32-bit value actually returned is therefore the expected value shifted left by 8 bits. Signed-off-by: Amol Surati <suratiamol@gmail.com> Message-id: 20180614054857.26248-1-suratiamol@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22Merge remote-tracking branch ↵Peter Maydell77-628/+8136
'remotes/stsquad/tags/pull-tcg-testing-revivial-210618-2' into staging Add check-tcg machinary This restores the ability to run TCG smoke tests by using our docker infrastructure to support cross building simple tests. It represents the first step to making better cross-architecture testing available straight from the source tree ;-) v2 - fix quoting of target_compiler - make docker.py Py3 safe - tweak .travis.yml recipe - don't probe docker when HAVE_USER_DOCKER not set # gpg: Signature made Thu 21 Jun 2018 07:23:45 BST # gpg: using RSA key FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-tcg-testing-revivial-210618-2: (57 commits) .travis.yml: add check-tcg test tests/docker/Makefile.include: only force SID to NOCACHE if old docker: docker.py adding age check command tests/Makefile: call sub-makes with SKIP_DOCKER_BUILD=1 docker: docker.py add check sub-command docker: docker.py don't conflate checksums for extra_files docker: docker.py use "version" to probe usage tests: add top-level make dependency for docker builds tests/tcg/i386: extend timeout for runcom test tests/tcg: override runners for broken tests tests/tcg: add run, diff, and skip helper macros tests/Makefile.include: add [build|clean|check]-tcg targets Makefile.target: add (clean-/build-)guest-tests targets tests/tcg/Makefile: update to be called from Makefile.target tests/tcg: enable building for PowerPC docker: move debian-powerpc-cross to sid based build tests/tcg: enable building for RISCV64 tests/tcg: enable building for mips64 tests/tcg: enable building for sparc64 tests/tcg: enable building for sh4 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-22Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2018-06-20-v2' ↵Peter Maydell9-144/+433
into staging nbd patches for 2018-06-20 Add experimental x-nbd-server-add-bitmap to expose a disabled bitmap over NBD, in preparation for a pull model incremental backup scheme. Also fix a corner case protocol issue with NBD_CMD_BLOCK_STATUS, and add new NBD_CMD_CACHE. - Eric Blake: tests: Simplify .gitignore - Eric Blake: nbd/server: Reject 0-length block status request - Vladimir Sementsov-Ogievskiy: 0/6 NBD export bitmaps - Vladimir Sementsov-Ogievskiy: nbd/server: introduce NBD_CMD_CACHE # gpg: Signature made Thu 21 Jun 2018 15:53:55 BST # gpg: using RSA key A7A16B4A2527436A # gpg: Good signature from "Eric Blake <eblake@redhat.com>" # gpg: aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" # gpg: aka "[jpeg image of size 6874]" # Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A * remotes/ericb/tags/pull-nbd-2018-06-20-v2: nbd/server: introduce NBD_CMD_CACHE docs/interop: add nbd.txt qapi: new qmp command nbd-server-add-bitmap nbd/server: implement dirty bitmap export nbd/server: add nbd_meta_empty_or_pattern helper nbd/server: refactor NBDExportMetaContexts nbd/server: fix trace nbd/server: Reject 0-length block status request tests: Simplify .gitignore Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-21Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20180615' into stagingPeter Maydell25-488/+1155
TCG patch queue: Workaround macos assembler lossage. Eliminate tb_lock. Fix TB code generation overflow. # gpg: Signature made Fri 15 Jun 2018 20:40:56 BST # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20180615: tcg: Reduce max TB opcode count tcg: remove tb_lock translate-all: remove tb_lock mention from cpu_restore_state_from_tb cputlb: remove tb_lock from tlb_flush functions translate-all: protect TB jumps with a per-destination-TB lock translate-all: discard TB when tb_link_page returns an existing matching TB translate-all: introduce assert_no_pages_locked translate-all: add page_locked assertions translate-all: use per-page locking in !user-mode translate-all: move tb_invalidate_phys_page_range up in the file translate-all: work page-by-page in tb_invalidate_phys_range_1 translate-all: remove hole in PageDesc translate-all: make l1_map lockless translate-all: iterate over TBs in a page with PAGE_FOR_EACH_TB tcg: move tb_ctx.tb_phys_invalidate_count to tcg_ctx tcg: track TBs with per-region BST's qht: return existing entry when qht_insert fails qht: require a default comparison function tcg/i386: Use byte form of xgetbv instruction Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-06-21nbd/server: introduce NBD_CMD_CACHEVladimir Sementsov-Ogievskiy3-5/+11
Handle nbd CACHE command. Just do read, without sending read data back. Cache mechanism should be done by exported node driver chain. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180413143156.11409-1-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: fix two missing case labels in switch statements] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21docs/interop: add nbd.txtVladimir Sementsov-Ogievskiy2-0/+39
Describe new metadata namespace: "qemu". Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180609151758.17343-7-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: grammar tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21qapi: new qmp command nbd-server-add-bitmapVladimir Sementsov-Ogievskiy2-0/+46
For now, the actual command ix x-nbd-server-add-bitmap, reflecting the fact that we are still working on libvirt code that proves the command works as needed, and also the fact that we may remove bitmap-export-name (and just require that the exported name be the bitmap name). Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180609151758.17343-6-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: make the command experimental by adding x- prefix] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21nbd/server: implement dirty bitmap exportVladimir Sementsov-Ogievskiy3-25/+262
Handle a new NBD meta namespace: "qemu", and corresponding queries: "qemu:dirty-bitmap:<export bitmap name>". With the new metadata context negotiated, BLOCK_STATUS query will reply with dirty-bitmap data, converted to extents. The new public function nbd_export_bitmap selects which bitmap to export. For now, only one bitmap may be exported. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180609151758.17343-5-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: wording tweaks, minor cleanups, additional tracing] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21nbd/server: add nbd_meta_empty_or_pattern helperVladimir Sementsov-Ogievskiy1-27/+62
Add nbd_meta_pattern() and nbd_meta_empty_or_pattern() helpers for metadata query parsing. nbd_meta_pattern() will be reused for the "qemu" namespace in following patches. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180609151758.17343-4-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: comment tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21nbd/server: refactor NBDExportMetaContextsVladimir Sementsov-Ogievskiy1-12/+11
Use NBDExport pointer instead of just export name: there is no need to store a duplicated name in the struct; moreover, NBDExport will be used further. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180609151758.17343-3-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: commit message grammar tweak] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21nbd/server: fix traceVladimir Sementsov-Ogievskiy1-4/+10
Return code = 1 doesn't mean that we parsed base:allocation. Use correct traces in both -parsed and -skipped cases. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com> Message-Id: <20180609151758.17343-2-vsementsov@virtuozzo.com> Reviewed-by: Eric Blake <eblake@redhat.com> [eblake: comment tweaks] Signed-off-by: Eric Blake <eblake@redhat.com>
2018-06-21nbd/server: Reject 0-length block status requestEric Blake1-0/+4
The NBD spec says that behavior is unspecified if the client requests 0 length for block status; but since the structured reply is documenting as returning a non-zero length, it's easier to just diagnose this with an EINVAL error than to figure out what to return. CC: qemu-stable@nongnu.org Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20180621124937.166549-1-eblake@redhat.com> Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
2018-06-21tests: Simplify .gitignoreEric Blake1-88/+5
Commit 0bcc8e5b was yet another instance of 'git status' reporting dirty files after an in-tree build, thanks to the new binary tests/check-block-qdict. Instead of piecemeal exemptions of each new binary as they are added, let's use git's negative globbing feature to exempt ALL files that have a 'test-' or 'check-' prefix, except for the ones ending in '.c' or '.sh'. We still have a couple of generated files that then need (re-)exclusion, but the overall list is a LOT shorter, and less prone to needing future edits. Signed-off-by: Eric Blake <eblake@redhat.com> Message-Id: <20180619203918.65450-1-eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20.travis.yml: add check-tcg testAlex Bennée1-0/+8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/docker/Makefile.include: only force SID to NOCACHE if oldAlex Bennée1-0/+6
Now we can check the age of a docker image we can be a little more intelligent about re-building Sid images and only force NOCACHE if it is "old". Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20docker: docker.py adding age check commandAlex Bennée1-10/+36
This is useful for querying if an image is too old. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/Makefile: call sub-makes with SKIP_DOCKER_BUILD=1Alex Bennée2-3/+18
As we now ensure all the images we are going to use are built in the top level make file lets not over complicate things by running the full script again. We do run the check script just in case someone deletes the docker image while we are running. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20docker: docker.py add check sub-commandAlex Bennée1-1/+37
This command allows you to check if we need to re-build a docker image. If the image isn't in the repository or the checksums don't match then we return false and some text (for processing in makefiles). Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20docker: docker.py don't conflate checksums for extra_filesAlex Bennée1-3/+5
This just gets confusing especially as the helper function doesn't even take into account any extra files (or the executable). Currently the actual check just ignores them and also passes the result through _dockerfile_preprocess so we fix that too. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20docker: docker.py use "version" to probe usageAlex Bennée1-1/+3
The "images" command is a fairly heavyweight command to run as it involves searching the whole docker file-system inventory. On a machine with a lot of images this makes start-up fairly expensive. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20tests: add top-level make dependency for docker buildsAlex Bennée2-0/+39
One problem with satisfying your docker dependencies in a sub-make it you might end up trying to satisfy the dependency multiple times. This is especially a problem with debian-sid based cross compilers and CI setups. We solve this by doing a docker build pass at the top level before any sub-makes are called. We still need to satisfy dependencies in the Makefile.target call so people can run tests from individual target directories. We introduce a new Makefile.probe which gets called for each PROBE_TARGET and allows us to build up the list. It does require multiply including config-target.mak which shouldn't cause any issues as it shouldn't define anything that clashes with config-host.mak. However we undefine a few key variables each time around. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20tests/tcg/i386: extend timeout for runcom testAlex Bennée1-0/+1
The Travis hardware can be a little slow and the runcom test is fairly heavy in calculating pi. Lets double the timeout so we don't trip up during CI by mistake. Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2018-06-20tests/tcg: override runners for broken testsAlex Bennée2-1/+9
To get a clean run of check-tcg these tests are currently skipped: - hello-mips for mips - linux-test for sparc Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: add run, diff, and skip helper macrosAlex Bennée5-19/+20
As we aren't using the default runners for all the test cases it is easy to miss out things like timeouts. To help with this we add some helpers and use them so we only need to make core changes in one place. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/Makefile.include: add [build|clean|check]-tcg targetsAlex Bennée1-1/+25
This will ensure all linux-user targets build their guest test programs and ensure check-tcg will run the respective tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20Makefile.target: add (clean-/build-)guest-tests targetsAlex Bennée3-0/+94
Now all the build infrastructure is in place we can build tests for each guest that we support. That support mainly depends on having cross compilers installed or docker setup. To keep all the logic for that together we put the rules in tests/tcg/Makefile.include and include it from the main Makefile.target. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg/Makefile: update to be called from Makefile.targetAlex Bennée2-107/+82
This make is now invoked from each individual target make with the appropriate CC and EXTRA_CFLAGS set for each guest. It then includes additional Makefile.targets from: - tests/tcg/multiarch (always) - tests/tcg/$(TARGET_BASE_ARCH) (if available) - tests/tcg/$(TARGET_NAME) The order is important as the later Makefile's may want to suppress TESTS from its base arch profile. Each included Makefile.target is responsible for adding TESTS as well as defining any special build instructions for individual tests. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2018-06-20tests/tcg: enable building for PowerPCAlex Bennée3-2/+19
Now we have restored debian-image-powerpc-cross using Debian SID compilers we can build for 32 bit powerpc. Although PPC32 supports a range of pages sizes currently only 4k works so the others are commented out for now. We can also merge the ppc64 support under the base architecture directory to avoid too much proliferation of directories. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
generated by cgit v1.1 at 2025-01-01 17:14:18 +0000