| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2023-11-06 | tcg: Remove TCG_TARGET_HAS_neg_{i32,i64} | Richard Henderson | 16 | -43/+15 |
| 2023-11-06 | tcg/loongarch64: Implement neg opcodes | Richard Henderson | 2 | -2/+11 |
| 2023-11-06 | tcg/mips: Implement neg opcodes | Richard Henderson | 2 | -2/+10 |
| 2023-11-06 | tcg: Remove TCG_TARGET_HAS_movcond_{i32,i64} | Richard Henderson | 14 | -66/+14 |
| 2023-11-06 | tcg/mips: Always implement movcond | Richard Henderson | 2 | -7/+16 |
| 2023-11-06 | tcg/mips: Split out tcg_out_setcond_int | Richard Henderson | 1 | -172/+106 |
| 2023-11-06 | tcg: Move tcg_temp_free_* out of line | Richard Henderson | 2 | -24/+30 |
| 2023-11-06 | tcg: Move tcg_temp_new_*, tcg_global_mem_new_* out of line | Richard Henderson | 4 | -77/+76 |
| 2023-11-06 | tcg: Move tcg_constant_* out of line | Richard Henderson | 4 | -26/+30 |
| 2023-11-06 | tcg: Unexport tcg_gen_op*_{i32,i64} | Richard Henderson | 2 | -126/+52 |
| 2023-11-06 | tcg: Move tcg_gen_opN declarations to tcg-internal.h | Richard Henderson | 2 | -7/+7 |
| 2023-11-06 | tcg: Move vec_gen_* declarations to tcg-internal.h | Richard Henderson | 2 | -4/+4 |
| 2023-11-06 | tcg: Move 64-bit expanders out of line | Richard Henderson | 2 | -206/+169 |
| 2023-11-06 | tcg: Move 32-bit expanders out of line | Richard Henderson | 2 | -122/+140 |
| 2023-11-06 | tcg: Move generic expanders out of line | Richard Henderson | 2 | -16/+19 |
| 2023-11-06 | tcg: Move tcg_gen_op* out of line | Richard Henderson | 2 | -208/+252 |
| 2023-11-06 | tcg: Mark tcg_gen_op* as noinline | Richard Henderson | 1 | -8/+14 |
| 2023-11-06 | accel/tcg: Fix condition for store_atom_insert_al16 | Richard Henderson | 2 | -6/+6 |
| 2023-11-06 | accel/tcg: Remove redundant case in store_atom_16 | Richard Henderson | 1 | -4/+0 |
| 2023-11-06 | host/include/loongarch64: Add atomic16 load and store | Richard Henderson | 3 | -0/+103 |
| 2023-11-06 | tcg/loongarch64: Use cpuinfo.h | Richard Henderson | 2 | -11/+5 |
| 2023-11-06 | util: Add cpuinfo for loongarch64 | Richard Henderson | 3 | -0/+58 |
| 2023-11-06 | tcg/loongarch64: Use C_N2_I1 for INDEX_op_qemu_ld_a*_i128 | Richard Henderson | 2 | -7/+12 |
| 2023-11-06 | tcg: Add C_N2_I1 | Richard Henderson | 1 | -0/+5 |
| 2023-11-06 | accel/tcg: Move HMP info jit and info opcount code | Richard Henderson | 7 | -158/+154 |
| 2023-11-06 | Merge tag 'pull-sp-20231105' of https://gitlab.com/rth7680/qemu into staging | Stefan Hajnoczi | 15 | -1381/+764 |
| 2023-11-06 | Merge tag 'migration-20231103-pull-request' of https://gitlab.com/juan.quinte... | Stefan Hajnoczi | 10 | -70/+398 |
| 2023-11-06 | Merge tag 'dump-pull-request' of https://gitlab.com/marcandre.lureau/qemu int... | Stefan Hajnoczi | 5 | -81/+134 |
| 2023-11-06 | Merge tag 'pull-loongarch-20231103' of https://gitlab.com/gaosong/qemu into s... | Stefan Hajnoczi | 9 | -52/+318 |
| 2023-11-05 | target/sparc: Check for invalid cond in gen_compare_reg | Richard Henderson | 1 | -19/+26 |
| 2023-11-05 | target/sparc: Implement UDIV inline | Richard Henderson | 2 | -14/+56 |
| 2023-11-05 | target/sparc: Implement UDIVX and SDIVX inline | Richard Henderson | 4 | -44/+97 |
| 2023-11-05 | target/sparc: Discard cpu_cond at the end of each insn | Richard Henderson | 1 | -0/+27 |
| 2023-11-05 | target/sparc: Record entire jump condition in DisasContext | Richard Henderson | 1 | -11/+16 |
| 2023-11-05 | target/sparc: Merge gen_op_next_insn into only caller | Richard Henderson | 1 | -7/+2 |
| 2023-11-05 | target/sparc: Pass displacement to advance_jump_cond | Richard Henderson | 1 | -7/+5 |
| 2023-11-05 | target/sparc: Merge advance_jump_uncond_{never,always} into advance_jump_cond | Richard Henderson | 1 | -44/+30 |
| 2023-11-05 | target/sparc: Merge gen_branch2 into advance_pc | Richard Henderson | 1 | -14/+14 |
| 2023-11-05 | target/sparc: Do flush_cond in advance_jump_cond | Richard Henderson | 1 | -6/+4 |
| 2023-11-05 | target/sparc: Always copy conditions into a new temporary | Richard Henderson | 1 | -1/+2 |
| 2023-11-05 | target/sparc: Change DisasCompare.c2 to int | Richard Henderson | 1 | -15/+18 |
| 2023-11-05 | target/sparc: Remove DisasCompare.is_bool | Richard Henderson | 1 | -15/+7 |
| 2023-11-05 | target/sparc: Remove CC_OP leftovers | Richard Henderson | 10 | -178/+26 |
| 2023-11-05 | target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV | Richard Henderson | 4 | -200/+32 |
| 2023-11-05 | target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB | Richard Henderson | 3 | -261/+42 |
| 2023-11-05 | target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD | Richard Henderson | 3 | -255/+87 |
| 2023-11-05 | target/sparc: Remove CC_OP_DIV | Richard Henderson | 5 | -110/+93 |
| 2023-11-05 | target/sparc: Remove CC_OP_LOGIC | Richard Henderson | 3 | -53/+28 |
| 2023-11-05 | target/sparc: Split psr and xcc into components | Richard Henderson | 7 | -270/+289 |
| 2023-11-05 | target/sparc: Introduce cpu_put_psr_icc | Richard Henderson | 3 | -2/+8 |
