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2014-06-16PPC: e500: Fix MMUCSR0 emulationAlex Zuepke3-5/+3
A "mtspr SPRMMUCSR0, reg" always flushed TLB0, because it passed the SPR number 0x3f4 to the flush routine. But we want to flush either TLB0 or TBL1 depending on the GPR value. Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> [agraf: change subject line, fix TCGv size mismatch] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Introduce bus_offset in sPAPRTCETableAlexey Kardashevskiy4-6/+15
This adds @bus_offset into sPAPRTCETable to tell where TCE table starts from. It is set to 0 for emulated devices. Dynamic DMA windows will use other offset. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Introduce page_shift in sPAPRTCETableAlexey Kardashevskiy4-26/+49
At the moment only 4K pages are supported by sPAPRTCETable. Since sPAPR spec allows other page sizes and we are going to implement them, we need page size to be configrable. This adds @page_shift into sPAPRTCETable and replaces SPAPR_TCE_PAGE_SHIFT with it where it is possible. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Get rid of window_size in sPAPRTCETableAlexey Kardashevskiy7-40/+26
This removes window_size as it is basically a copy of nb_table shifted by SPAPR_TCE_PAGE_SHIFT. As new dynamic DMA windows are going to support windows as big as the entire RAM and this number will be bigger that 32 capacity, we will have to do something about @window_size anyway and removal seems to be the right way to go. This removes dma_window_start/dma_window_size from sPAPRPHBState as they are no longer used. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Convert old qdev_init_nofail() to object_property_set_boolAlexey Kardashevskiy1-1/+1
qdev_init_nofail() was replaced by object_property_set_bool("realized") all over the QEMU so do we. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: Allow multiple TCE tables per PHBAlexey Kardashevskiy2-12/+43
At the moment sPAPRPHBState contains a @tcet pointer to the only TCE table. However sPAPR spec allows having more than one DMA window. Since the TCE object is already a child of SPAPR PHB object, there is no need to keep an additional pointer to it in sPAPRPHBState so remove it. This changes the way sPAPRPHBState::reset performs reset of sPAPRTCETable objects. This changes the default DMA window properties calculation. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: spapr_iommu: Make DMA window a subregionAlexey Kardashevskiy3-3/+20
Currently the default DMA window is represented by a single MemoryRegion. However there can be more than just one window so we need a "root" memory region to be separated from the actual DMA window(s). This introduces a "root" IOMMU memory region and adds a subregion for the default DMA 32bit window. Following patches will add other subregion(s). This initializes a default DMA window subregion size to the guest RAM size as this window can be switched into "bypass" mode which implements direct DMA mapping. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_pci: Introduce a finish_realize() callbackAlexey Kardashevskiy2-14/+42
The spapr-pci PHB initializes IOMMU for emulated devices only. The upcoming VFIO support will do it different. However both emulated and VFIO PHB types share most of the initialization code. For the type specific things a new finish_realize() callback is introduced. This introduces sPAPRPHBClass derived from PCIHostBridgeClass and adds the callback pointer. This implements finish_realize() for emulated devices. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: Fix compilation] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Enable multiple TCE requestsAlexey Kardashevskiy5-0/+96
Currently only single TCE entry per request is supported (H_PUT_TCE). However PAPR+ specification allows multiple entry requests such as H_PUT_TCE_INDIRECT and H_STUFF_TCE. Having less transitions to the host kernel via ioctls, support of these calls can accelerate IOMMU operations. This implements H_STUFF_TCE and H_PUT_TCE_INDIRECT. This advertises "multi-tce" capability to the guest if the host kernel supports it (KVM_CAP_SPAPR_MULTITCE) or guest is running in TCG mode. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Enable dynamic change of the supported hypercalls listAlexey Kardashevskiy1-7/+23
At the moment the "ibm,hypertas-functions" list is fixed. However some calls should be listed there if they are supported by QEMU or the host kernel. This enables hyperrtas_prop to grow on stack by adding a SPAPR_HYPERRTAS_ADD macro. "qemu,hypertas-functions" is converted as well. The first user of this is going to be a "multi-tce" property. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16macio: Fix timer endiannessAlexander Graf1-1/+1
The timer registers on our KeyLargo macio emulation are read as byte reversed from the big endian guest, so we better expose them endian reversed as well. This fixes initial hickups of booting Mac OS X with -M mac99 for me. Signed-off-by: Alexander Graf <agraf@suse.de> Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
2014-06-16macio ide: Do remainder access asynchronouslyAlexander Graf3-10/+51
The macio IDE controller has some pretty nasty magic in its implementation to allow for unaligned sector accesses. We used to handle these accesses synchronously inside the IO callback handler. However, the block infrastructure changed below our feet and now it's impossible to call a synchronous block read/write from the aio callback handler of a previous block access. Work around that limitation by making the unaligned handling bits also go through our asynchronous handler. This fixes booting Mac OS X for me. Reported-by: John Arbuckle <programmingkidx@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Fix popcntb Opcode BugTom Musta1-1/+1
The popcntb instruction is erroneously encoded with opcode extension (opc1,opc2) = (0x03,0x03). Bits 21-30 of popcntb are 122 = 0b00011-0b11010 and therefore this should be encoded as (opc1,opc2) = (0x1A, 0x03). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr_iommu: Replace @instance_id with LIOBN for migrationAlexey Kardashevskiy1-1/+3
SPAPR IOMMU is a bus-less device and therefore its only ID in migration stream is an instance id which is not reliable ID as it depends on the command line parameters order. Since libvirt may change the order, we need something better than that. This removes VMSD descriptor from the class definitiion and registers it with @liobn as an intance ID to let the destination side find the right device to receive migration data. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16KVM: PPC: Enable compatibility modeAlexey Kardashevskiy3-0/+16
The host kernel implements a KVM_REG_PPC_ARCH_COMPAT register which this uses to enable a compatibility mode if any chosen. This sets the KVM_REG_PPC_ARCH_COMPAT register in KVM. ppc_set_compat() signals the caller if the mode cannot be enabled by the host kernel. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix TCG compat setting] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Implement processor compatibility in ibm, client-architecture-supportAlexey Kardashevskiy3-1/+113
Modern Linux kernels support last POWERPC CPUs so when a kernel boots, in most cases it can find a matching cpu_spec in the kernel's cpu_specs list. However if the kernel is quite old, it may be missing a definition of the actual CPU. To provide an ability for old kernels to work on modern hardware, a Processor Compatibility Mode has been introduced by the PowerISA specification. >From the hardware prospective, it is supported by the Processor Compatibility Register (PCR) which is defined in PowerISA. The register enables one of the compatibility modes (2.05/2.06/2.07). Since PCR is a hypervisor privileged register and cannot be directly accessed from the guest, the mode selection is done via ibm,client-architecture-support (CAS) RTAS call using which the guest specifies what "raw" and "architected" CPU versions it supports. QEMU works out the best match, changes a "cpu-version" property of every CPU and notifies the guest about the change by setting these properties in the buffer passed as a response on a custom H_CAS hypercall. This implements ibm,client-architecture-support parameters parsing (now only for PVRs) and cooks the device tree diff with new values for "cpu-version", "ibm,ppc-interrupt-server#s" and "ibm,ppc-interrupt-server#s" properties. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Limit threads per core according to current compatibility modeAlexey Kardashevskiy3-1/+29
This puts a limit to the number of threads per core based on the current compatibility mode. Although PowerISA specs do not specify the maximum threads per core number, the linux guest still expects that PowerISA2.05-compatible CPU supports only 2 threads per core as this is what POWER6 (2.05 compliant CPU) implements, the same is for POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads). This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of threads which affects ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. The number of CPU nodesremains unchanged. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Rework spapr_fixup_cpu_dt()Alexey Kardashevskiy1-11/+22
In PPC code we usually use the "cs" name for a CPUState* variables and "cpu" for PowerPCCPU. So let's change spapr_fixup_cpu_dt() to use same rules as spapr_create_fdt_skel() does. This adds missing nodes creation if they do not already exist in the current device tree, this is going to be used from the client-architecture-support handler. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add ibm, client-architecture-support callAlexey Kardashevskiy4-1/+69
The PAPR+ specification defines a ibm,client-architecture-support (CAS) RTAS call which purpose is to provide a negotiation mechanism for the guest and the hypervisor to work out the best compatibility parameters. During the negotiation process, the guest provides an array of various options and capabilities which it supports, the hypervisor adjusts the device tree and (optionally) reboots the guest. At the moment the Linux guest calls CAS method at early boot so SLOF gets called. SLOF allocates a memory buffer for the device tree changes and calls a custom KVMPPC_H_CAS hypercall. QEMU parses the options, composes a diff for the device tree, copies it to the buffer provided by SLOF and returns to SLOF. SLOF updates the device tree and returns control to the guest kernel. Only then the Linux guest parses the device tree so it is possible to avoid unnecessary reboot in most cases. The device tree diff is a header with an update format version (defined as 1 in this patch) followed by a device tree with the properties which require update. If QEMU detects that it has to reboot the guest, it silently does so as the guest expects reboot to happen because this is usual pHyp firmware behavior. This defines custom KVMPPC_H_CAS hypercall. The current SLOF already has support for it. This implements stub which returns very basic tree (root node, no properties) to the guest. As the return buffer does not contain any change, no change in behavior is expected. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Define Processor Compatibility MasksAlexey Kardashevskiy2-0/+4
This introduces PCR mask for supported compatibility modes. This will be used later by the ibm,client-architecture-support call. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy4-0/+61
This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Move SMT-related properties out of skeleton fdtAlexey Kardashevskiy1-15/+33
The upcoming support of the "ibm,client-architecture-support" reconfiguration call will be able to change dynamically the number of threads per core (SMT mode). From the device tree prospective this does not change the number of CPU nodes (as it is one node per a CPU core) but affects content and size of the ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. This moves ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s out of the device tree skeleton. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Add "compat" CPU optionAlexey Kardashevskiy3-0/+87
PowerISA defines a compatibility mode for server POWERPC CPUs which is supported by the PCR special register which is hypervisor privileged. To support this mode for guests, SPAPR defines a set of virtual PVRs, one per PowerISA spec version. When a hypervisor needs a guest to work in a compatibility mode, it puts a virtual PVR value into @cpu-version property of a CPU node. This introduces a "compat" CPU option which defines maximal compatibility mode enabled. The supported modes are power6/power7/power8. This does not change the existing behaviour, new property will be used by next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: openpic_kvm: Implement resetAlexander Graf1-5/+10
When we trigger a system reset, the in-kernel openpic controller should also get reset. This happens through a write to the GCR.RESET register which is the same mechanism a guest would use to manually reset the device. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16openpic: Reset IRQ source private membersPaul Janzen1-2/+2
The openpic emulation code maintains an allowable-CPU's bitmap ("destmask") for each IRQ source which is calculated from the IDR register value whenever the guest OS writes to it. However, if the guest OS relies on the system to set the IDR register to a default value at reset, and does not write IDR, then destmask does not get updated, and interrupts do not get propagated to the guest. Additionally, if an IRQ source is marked as critical, the source's internal "output" and "nomask" fields are not correctly reset when the PIC is reset. Fix both these issues by calling write_IRQreg_idr from within openpic_reset, instead of simply setting the IDR register to the specified idr_reset value. Signed-off-by: Paul Janzen <pcj@pauljanzen.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16openpic: Move definition of openpic_resetPaul Janzen1-49/+50
This patch moves the definition of openpic_reset after the various register read/write functions. No functional change. It is in preparation for using the register read/write functions in openpic_reset. Signed-off-by: Paul Janzen <pcj@pauljanzen.org> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Set the correct endianness in ELF dump headerBharata B Rao1-4/+8
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Introduce callback for interrupt endiannessGreg Kurz2-0/+17
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a Linux guest, this provides a hint on the endianness used by the kernel. And when it comes to dumping a guest, the information is needed to write ELF headers using the kernel endianness. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> [agraf: change subject line] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Support dump for little endian ppc64Bharata B Rao1-33/+62
Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16dump: Make DumpState and endian conversion routines available for ↵Bharata B Rao4-152/+154
arch-specific dump code Make DumpState and endian conversion routines available for arch-specific dump code by moving into dump.h. DumpState will be needed by arch-specific dump code to access target endian information from DumpState->ArchDumpInfo. Also break the dependency of dump.h from stubs/dump.c by creating a separate dump-arch.h. This patch doesn't change any functionality. Signed-off-by: Bharata B Rao <bharata@linux.ibm.com> [ rebased on top of current master branch, renamed endian helpers to cpu_to_dump{16,32,64}, pass a DumpState * argument to endian helpers, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> [agraf: fix to apply] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16macio: handle non-block ATAPI DMA transfersMark Cave-Ayland1-0/+21
Currently the macio DMA routines assume that all DMA requests are for read/write block transfers. This is not always the case for ATAPI, for example when requesting a TOC where the response is generated directly in the IDE buffer. Detect these non-block ATAPI DMA transfers (where no lba is specified in the command) and copy the results directly into RAM as indicated by the DBDMA descriptor. This fixes CDROM access under MorphOS. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add ibm, chip-id property in device treeAlexey Kardashevskiy1-0/+6
This adds a "ibm,chip-id" property for CPU nodes which should be the same for all cores in the same CPU socket. The recent guest kernels use this information to associate threads with sockets. Refer to the kernel commit 256f2d4b463d3030ebc8d2b54f427543814a2bdc for more details. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16spapr: Add support for time base offset migrationAlexey Kardashevskiy6-2/+106
This allows guests to have a different timebase origin from the host. This is needed for migration, where a guest can migrate from one host to another and the two hosts might have a different timebase origin. However, the timebase seen by the guest must not go backwards, and should go forwards only by a small amount corresponding to the time taken for the migration. This is only supported for recent POWER hardware which has the TBU40 (timebase upper 40 bits) register. That includes POWER6, 7, 8 but not 970. This adds kvm_access_one_reg() to access a special register which is not in env->spr. This requires kvm_set_one_reg/kvm_get_one_reg patch. The feature must be present in the host kernel. This bumps vmstate_spapr::version_id and enables new vmstate_ppc_timebase only for it. Since the vmstate_spapr::minimum_version_id remains unchanged, migration from older QEMU is supported but without vmstate_ppc_timebase. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Move to u-boot as firmwareAlexander Graf1-41/+73
Almost all platforms QEMU emulates have some sort of firmware they can load to expose a guest environment that closely resembles the way it would look like on real hardware. This patch introduces such a firmware on our e500 platforms. U-boot is the default firmware for most of these systems and as such our preferred choice. For backwards compatibility reasons (and speed and simplicity) we skip u-boot when you use -kernel and don't pass in -bios. For all other combinations like -kernel and -bios or no -kernel you get u-boot as firmware. This allows you to modify the boot environment, execute a networked boot through the e1000 emulation and execute u-boot payloads. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add u-boot firmware for e500Alexander Graf6-0/+18
This adds a special build of u-boot tailored for the e500 platforms we emulate. It is based on the current version of upstream u-boot which contains all the code necessary to drive our QEMU provided machines. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: Expose kernel load address in dtAlexander Graf1-5/+23
We want to move to a model where firmware loads our kernel. To achieve this we need to be able to tell firmware where the kernel lies. Let's copy the mechanism we already use for -M pseries and expose the kernel load address and size through the device tree. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add dcbtls emulationAlexander Graf1-0/+12
The dcbtls instruction is able to lock data inside the L1 cache. Unfortunately we don't emulate any caches, so we have to tell the guest that its locking attempt failed. However, by implementing the instruction we at least don't give the guest a program exception which it definitely does not expect. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Properly emulate L1CSR0 and L1CSR1Alexander Graf2-3/+23
There are 2 L1 cache control registers - one for data (L1CSR0) and one for instructions (L1CSR1). Emulate both of them well enough to give the guest the illusion that it could actually do anything about its caches. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add L1CFG1 SPR emulationAlexander Graf2-1/+8
In addition to the L1 data cache configuration register L1CFG0 there is also another one for the L1 instruction cache called L1CFG1. Emulate that one with the same values as the data one. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Fix SPR access control of L1CFG0Alexander Graf1-4/+4
The L1CFG0 register on e200 and e500 is "User RO" according to the specifications. So let's make it user readable and world unwritable. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Add definitions for GIVORsAlexander Graf1-0/+6
We're missing SPR definitions for GIVORs. Add them to the list of SPRs. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Make all e500 CPUs SVR awareAlexander Graf1-14/+14
Our pre-e500mc e500 CPU types didn't get instanciated with SVR information, even though those systems do support the SVR register. Spawn them with the SVR tag so that they don't get confused when someone tries to read SPR_SVR. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Fail on leaking temporariesAlexander Graf1-0/+7
When QEMU gets compiled with --enable-debug-tcg we can check for temporary leakage. Implement the necessary target code for this and fail emulation when we hit a leakage. This hopefully ensures that we don't get new leaks. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: Fix TCG chunks that don't free their tempsAlexander Graf1-0/+7
We want to make sure that every instruction cleans up after itself and clears every temporary it allocated. While checking whether this is already the case, I came across a few cases where it isn't. This patch fixes every translation I found that doesn't free their allocated temporaries. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: implement PCI INTx routingBharat Bhushan2-2/+24
This patch adds pci pin to irq_num routing callback. This callback is called from pci_device_route_intx_to_irq to find which pci device maps to which irq. This fix is required for pci-device passthrough using vfio. Also without this patch we gets below prints " PCI: Bug - unimplemented PCI INTx routing (e500-pcihost) qemu-system-ppc64: PCI: Bug - unimplemented PCI INTx routing (e500-pcihost) " and Legacy interrupt does not work with pci device passthrough. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> [agraf: remove double semicolon] Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16PPC: e500: some pci related cleanupBharat Bhushan2-12/+14
- Use PCI_NUM_PINS rather than hardcoding - use "pin" wherever possible Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16KVM: PPC: Don't secretly add 1T segment feature to CPUAlexander Graf1-3/+5
When we select a CPU type that does not support 1TB segments, we should not expose 1TB just because KVM supports 1TB segments. User configuration always wins over feature availability. Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-ppc: Refactor AES InstructionsTom Musta1-254/+38
This patch refactors the PowerPC Advanced Encryption Standard (AES) instructions to use the common AES tables (include/qemu/aes.h). Specifically: - vsbox is recoded to use the AES_sbox table. - vcipher, vcipherlast and vncipherlast are all recoded to use the optimized AES_t[ed][0-4] tables. - vncipher is recoded to use a combination of InvS-Box, InvShiftRows and InvMixColumns tables. It was not possible to use AES_Td[0-4] due to a slight difference in how PowerPC implements vncipher. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-arm: Use Common Tables in AES InstructionsTom Musta1-75/+4
This patch refactors the ARM cryptographic instructions to use the (newly) added common tables from include/qemu/aes.h. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
2014-06-16target-i386: Use Common ShiftRows and InvShiftRows TablesTom Musta1-19/+13
This patch eliminates the (now) redundant copy of the Advanced Encryption Standard (AES) ShiftRows and InvShiftRows tables; the code is updated to use the common tables declared in include/qemu/aes.h. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
generated by cgit v1.1 at 2024-12-29 17:51:25 +0000