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2017-01-039pfs: introduce init_out/in_iov_from_pduStefano Stabellini3-13/+27
Not all 9pfs transports share memory between request and response. For those who don't, it is necessary to know how much memory is required in the response. Split the existing init_iov_from_pdu function in two: init_out_iov_from_pdu (for writes) and init_in_iov_from_pdu (for reads). init_in_iov_from_pdu takes an additional size parameter to specify the memory required for the response message. Signed-off-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-039pfs: call v9fs_init_qiov_from_pdu before v9fs_packStefano Stabellini1-29/+30
v9fs_xattr_read should not access VirtQueueElement elems directly. Move v9fs_init_qiov_from_pdu up in the file and call v9fs_init_qiov_from_pdu before v9fs_pack. Use v9fs_pack on the new iovec. Signed-off-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-039pfs: introduce transport specific callbacksStefano Stabellini4-20/+40
Don't call virtio functions from 9pfs generic code, use generic function callbacks instead. Signed-off-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Greg Kurz <groug@kaod.org>
2017-01-039pfs: move pdus to V9fsStateStefano Stabellini3-5/+4
pdus are initialized and used in 9pfs common code. Move the array from V9fsVirtioState to V9fsState. Signed-off-by: Stefano Stabellini <sstabellini@kernel.org> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Greg Kurz <groug@kaod.org>
2016-12-28Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-2.9-pull-request' ↵Peter Maydell7-265/+1623
into staging # gpg: Signature made Tue 27 Dec 2016 17:52:12 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier/tags/m68k-for-2.9-pull-request: target-m68k: free TCG variables that are not target-m68k: add rol/ror/roxl/roxr instructions target-m68k: Inline shifts target-m68k: Do not cpu_abort on undefined insns target-m68k: Implement 680x0 movem target-m68k: add cas/cas2 ops target-m68k: add abcd/sbcd/nbcd target-m68k: add 680x0 divu/divs variants target-m68k: add 64bit mull target-m68k: add cmpm target-m68k: Split gen_lea and gen_ea target-m68k: Delay autoinc writeback Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-m68k: free TCG variables that are notLaurent Vivier1-9/+32
This is a cleanup patch. It adds call to tcg_temp_free() when it is missing. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add rol/ror/roxl/roxr instructionsLaurent Vivier1-0/+391
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: Inline shiftsRichard Henderson3-80/+201
Also manage word and byte operands and fix the computation of overflow in the case of M68000 arithmetic shifts. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-4-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: Do not cpu_abort on undefined insnsRichard Henderson1-3/+5
Report this properly via exception and, importantly, allow the disassembler the chance to tell us what insn is not handled. Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-3-git-send-email-rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2016-12-27target-m68k: Implement 680x0 movemLaurent Vivier1-23/+107
680x0 movem can load/store words and long words and can use more addressing modes. Coldfire can only use long words with (Ax) and (d16,Ax) addressing modes. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478699171-10637-2-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: add cas/cas2 opsLaurent Vivier3-0/+265
Implement CAS using cmpxchg. Implement CAS2 using helper and either cmpxchg when the 32bit addresses are consecutive, or with parallel_cpus+cpu_loop_exit_atomic() otherwise. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add abcd/sbcd/nbcdLaurent Vivier1-0/+220
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net>
2016-12-27target-m68k: add 680x0 divu/divs variantsLaurent Vivier6-70/+218
Update helper to set the throwing location in case of div-by-0. Cleanup divX.w and add quad word variants of divX.l. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twidle.net> [laurent: modified to clear Z on overflow, as found with risu]
2016-12-27target-m68k: add 64bit mullLaurent Vivier1-12/+50
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twidle.net>
2016-12-27target-m68k: add cmpmLaurent Vivier1-0/+16
Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <1477604609-2206-2-git-send-email-laurent@vivier.eu> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-4-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: Split gen_lea and gen_eaRichard Henderson1-53/+59
Provide gen_lea_mode and gen_ea_mode, where the mode can be specified manually, rather than taken from the instruction. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-3-git-send-email-rth@twiddle.net>
2016-12-27target-m68k: Delay autoinc writebackRichard Henderson1-20/+64
Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1478206203-4606-2-git-send-email-rth@twiddle.net>
2016-12-27Merge remote-tracking branch ↵Peter Maydell24-89/+245
'remotes/pmaydell/tags/pull-target-arm-20161227' into staging target-arm queue: * add VBAR support to ARM1176 CPUs * hw/i2c: add NULL check to i2c slave init callbacks * pxa2xx.c: fix trailing whitespace * aspeed: various cleanups * aspeed: add romulus-bmc board * virt: add 2.9 machine type * gicv3: don't signal Pending+Active interrupts to CPU * gicv3: fix incorrect usage of fieldoffset * arm: log AArch64 exception returns * gicv3: fix aff3 field in typer register * aarch64: fix ldst_single_struct on BE hosts * aarch64: fix vec_reg_offset on BE hosts * arm: fix Cortex-A8 MVFR1 register value * cadence_uart: check if receiver timeout counter disabled * cadence_uart: check register values on migration # gpg: Signature made Tue 27 Dec 2016 15:19:26 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20161227: (25 commits) target-arm: Add VBAR support to ARM1176 CPUs hw/i2c: Add a NULL check for i2c slave init callbacks hw/arm: remove trailing whitespace aspeed/smc: set the number of flash modules for the FMC controller aspeed/smc: improve segment register support aspeed/scu: fix SCU region size aspeed: change SoC revision of the palmetto-bmc machine aspeed: add the definitions for the AST2400 A1 SoC aspeed: add a memory region for SRAM aspeed: add support for the romulus-bmc board aspeed: extend the board configuration with flash models aspeed: attach the second SPI controller object to the SoC aspeed: remove cannot_destroy_with_object_finalize_yet aspeed: QOMify the CPU object and attach it to the SoC m25p80: add support for the mx66l1g45g hw/arm/virt: add 2.9 machine type hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset target-arm: Log AArch64 exception returns hw/intc/arm_gicv3_common: fix aff3 in typer ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Add VBAR support to ARM1176 CPUsCédric Le Goater3-6/+23
ARM1176 CPUs have TrustZone support and can use the Vector Base Address Register, but currently, qemu only adds VBAR support to ARMv7 CPUs. Fix this by adding a new feature ARM_FEATURE_VBAR which can used for ARMv7 and ARM1176 CPUs. The VBAR feature is always set for ARMv7 because some legacy boards require it even if this is not architecturally correct. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1481810970-9692-1-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27hw/i2c: Add a NULL check for i2c slave init callbacksAlastair D'Silva5-28/+5
Add a NULL check for i2c slave init callbacks, so that we no longer need to implement empty init functions. Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Message-id: 20161202054617.6749-4-alastair@au1.ibm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: squashed in later tweak from Alistair to if() phrasing] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27hw/arm: remove trailing whitespaceAlastair D'Silva1-1/+1
Remove trailing whitespace in hw/arm/pxa2xx.c Signed-off-by: Alastair D'Silva <alastair@d-silva.org> Message-id: 20161202054617.6749-3-alastair@au1.ibm.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed/smc: set the number of flash modules for the FMC controllerCédric Le Goater2-4/+10
Add a new configuration field at the board level and propagate the value using the "num-cs" property of the FMC controller model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1480434248-27138-14-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed/smc: improve segment register supportCédric Le Goater1-8/+9
The HW does not enforce all the rules in the specs and allows a few "curious" setups like zero size segments and overlaps. So change the model to be in sync but keep the warnings which are always interesting for debug. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 1480434248-27138-13-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed/scu: fix SCU region sizeCédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-12-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: change SoC revision of the palmetto-bmc machineCédric Le Goater1-1/+1
The palmetto BMC machine uses a AST2400 revision A1 SoC. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-11-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add the definitions for the AST2400 A1 SoCCédric Le Goater4-0/+16
There is not much differences with the A0 revision apart from the DDR calibration. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-10-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add a memory region for SRAMCédric Le Goater2-9/+45
The size of the SRAM depends on the SoC model, so use a per-soc definition when creating the region. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-9-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: add support for the romulus-bmc boardCédric Le Goater1-0/+44
The Romulus machine is an OpenPOWER system with an AST2500 SoC for the BMC and a POWER9 chip for the host. It does not make much difference for qemu a part from the fact that the FMC controller has two SPI flash module. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Message-id: 1480434248-27138-8-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: extend the board configuration with flash modelsCédric Le Goater1-4/+16
Future machine will use different flash models for the FMC and the SPI controllers. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-7-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: attach the second SPI controller object to the SoCCédric Le Goater1-1/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-6-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: remove cannot_destroy_with_object_finalize_yetCédric Le Goater1-6/+0
With commit ce5b1bbf624b ("exec: move cpu_exec_init() calls to realize functions"), we can now remove cannot_destroy_with_object_finalize_yet. Suggested-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-id: 1480434248-27138-5-git-send-email-clg@kaod.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27aspeed: QOMify the CPU object and attach it to the SoCCédric Le Goater2-4/+15
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-4-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27m25p80: add support for the mx66l1g45gCédric Le Goater1-0/+1
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Marcin Krzeminski <marcin.krzeminski@nokia.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 1480434248-27138-3-git-send-email-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27hw/arm/virt: add 2.9 machine typePeter Maydell2-2/+20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Andrew Jones <drjones@redhat.com>
2016-12-27hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPUPeter Maydell1-0/+5
The GICv3 requires that we only signal Pending interrupts to the CPU. This category does not include Pending+Active interrupts, which means we need to check whether the interrupt is Active in the gicr_int_pending() and gicd_int_pending() functions. Interrupts are rarely in the Active+Pending state, but KVM uses this as part of its handling of the virtual timer, so this bug was causing KVM to go into an infinite loop of taking the vtimer interrupt when the guest first triggered it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27hw/intc/arm_gicv3: Remove incorrect usage of fieldoffsetPeter Maydell1-7/+6
In the ARMCPRegInfo definitions for the GICv3 CPU interface registers, we were trying to use .fieldoffset to specify the locations of data fields within the GICv3CPUState struct. This is completely broken, because .fieldoffset is for offsets into the CPUARMState struct. We didn't notice because we were only using this for reads to BPR0, AP0R<n>, IGRPEN0 and CTLR_EL3, and Linux doesn't use these registers. Replace the .fieldoffset uses with explicit read functions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27target-arm: Log AArch64 exception returnsPeter Maydell1-0/+9
We already log exception entry; add logging of the AArch64 exception return path as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2016-12-27hw/intc/arm_gicv3_common: fix aff3 in typerAndrew Jones1-1/+2
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-id: 20161209143703.29457-1-drjones@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Fix aarch64 disas_ldst_single_structRichard Henderson1-2/+2
We add s->be_data within do_vec_ld/st. Adding it here means that we have the wrong bits set in SIZE for a big-endian host, leading to g_assert_not_reached in write_vec_element and read_vec_element. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-3-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27target-arm: Fix aarch64 vec_reg_offsetRichard Henderson1-1/+2
Since CPUARMState.vfp.regs is not 16 byte aligned, the ^ 8 fixup used for a big-endian host doesn't do what's intended. Fix this by adding in the vfp.regs offset after computing the inter-register offset. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1481085020-2614-2-git-send-email-rth@twiddle.net Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27Correct value of ARM Cortex-A8 MVFR1 register.Julian Brown1-1/+1
The value of the MVFR1 (Media and VFP Feature Register 1) register for the Cortex-A8 appears to be incorrect (according to the TRM, DDI0344K), with the "full denormal arithmetic" and "propagation of NaN" fields holding both 0 instead of both 1. I had a go tracing the history of the use of this value, and it seems it's always just been wrong in QEMU: maybe it was derived from early documentation, or guessed based on the use of a "VFP Lite" implementation in the Cortex-A8. Depending on the startup/early-boot code in use, this can manifest as failure to perform denormal arithmetic properly: in our case, selecting a Cortex-A8 CPU when using QEMU as an instruction-set simulator for bare-metal GCC testing caused tests using denormal arithmetic to fail. Problems might be masked (or not occur) when using a full OS kernel with suitable trap handlers (I'm not sure). Signed-off-by: Julian Brown <julian@codesourcery.com> Message-id: 1481130858-31767-1-git-send-email-julian@codesourcery.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27cadence_uart: Check if receiver timeout counter is disabledAndrew Gacek1-3/+4
When register Rcvr_timeout_reg0 (R_RTOR in cadence_uart.c) is set to 0, the receiver timeout counter should be disabled. See page 1801 of "Zynq-7000 AP SoC Technical Reference Manual". This commit adds a such a check before setting the receive timeout interrupt. Signed-off-by: Andrew Gacek <andrew.gacek@gmail.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27cadence_uart: Check baud rate generator and divider values on migrationAlistair Francis1-0/+7
The Cadence UART device emulator calculates speed by dividing the baud rate by a 'baud rate generator' & 'baud rate divider' value. The device specification defines these register values to be non-zero and within certain limits. Checks were recently added when writing to these registers but not when restoring from migration. This patch adds checks when restoring from migration to avoid divide by zero errors. Reported-by: Huawei PSIRT <psirt@huawei.com> Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 04ae30ed8ee1758cd2d2af880da4d28f74c67738.1481132150.git.alistair.francis@xilinx.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-27Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20161223' into stagingPeter Maydell1-35/+40
queued s390 host fixes # gpg: Signature made Sat 24 Dec 2016 03:41:40 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20161223: tcg/s390: Remove 'R' constraint tcg/s390: Fix setcond expansion Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-23tcg/s390: Remove 'R' constraintRichard Henderson1-15/+10
Since R0 is reserved, we don't need a special case constraint. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-23tcg/s390: Fix setcond expansionRichard Henderson1-20/+30
We can't use LOAD AND TEST for unsigned data and then expect to extract the result with ADD LOGICAL WITH CARRY. Fall through to using COMPARE LOGICAL IMMEDIATE instead. Signed-off-by: Richard Henderson <rth@twiddle.net>
2016-12-22Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell45-793/+1722
* core support for MemoryRegionCache from myself * rules.mak speedup and cleanups from myself and Marc-Adnré * multiboot command line fix from Vlad * SCSI fixes from myself * small qemu-timer speedup from myself * x86 debugging improvements from Doug * configurable Q35 devices from Chao * x86 5-level paging support from Kirill * x86 SHA_NI support for KVM from Yi Sun * improved kvmclock migration logic from Marcelo * bugfixes and doc fixes from others # gpg: Signature made Thu 22 Dec 2016 15:01:13 GMT # gpg: using RSA key 0xBFFBD25F78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: (25 commits) x86: implement la57 paging mode target-i386: Fix eflags.TF/#DB handling of syscall/sysret insns kvmclock: reduce kvmclock difference on migration kvm: sync linux headers scsi-disk: fix VERIFY for scsi-block hw/block/pflash_cfi*.c: fix confusing assert fail message multiboot: copy the cmdline verbatim, unescape module strings x86: Fix x86_64 'g' packet response to gdb from 32-bit mode. pc: make pit configurable pc: make sata configurable pc: make smbus configurable target-i386: Add Intel SHA_NI instruction support. block: drop remaining legacy aio functions in comment main-loop: update comment for qemu_mutex_lock/unlock_iothread timer: fix misleading comment in timer.h qemu-timer: check active_timers outside lock/event virtio-scsi: introduce virtio_scsi_acquire/release build-sys: remove libtool left-over rules.mak: add more rules to avoid chaining rules.mak: speedup save-vars load-vars ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-22Merge remote-tracking branch ↵Peter Maydell14-6/+1191
'remotes/berrange/tags/pull-qcrypto-2016-12-21-2' into staging Merge qcrypto 2016/12/21 v2 # gpg: Signature made Thu 22 Dec 2016 10:46:17 GMT # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qcrypto-2016-12-21-2: crypto: add HMAC algorithms testcases crypto: support HMAC algorithms based on nettle crypto: support HMAC algorithms based on glib crypto: support HMAC algorithms based on libgcrypt crypto: add HMAC algorithms framework configure: add CONFIG_GCRYPT_HMAC item crypto: add 3des-ede support when using libgcrypt/nettle cipher: fix leak on initialization error Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-12-22x86: implement la57 paging modeKirill A. Shutemov5-74/+274
The new paging more is extension of IA32e mode with more additional page table level. It brings support of 57-bit vitrual address space (128PB) and 52-bit physical address space (4PB). The structure of new page table level is identical to pml4. The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16]. CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level paging mode. Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Message-Id: <20161215001305.146807-1-kirill.shutemov@linux.intel.com> [Drop changes to target-i386/translate.c. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-12-22target-i386: Fix eflags.TF/#DB handling of syscall/sysret insnsDoug Evans3-5/+32
The syscall and sysret instructions behave a bit differently: TF is checked after the instruction completes. This allows the o/s to disable #DB at a syscall by adding TF to FMASK. And then when the sysret is executed the #DB is taken "as if" the syscall insn just completed. Signed-off-by: Doug Evans <dje@google.com> Message-Id: <94eb2c0bfa1c6a9fec0543057483@google.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-01-04 10:56:35 +0000