aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2016-02-11hw/arm/virt: fix max-cpus checkAndrew Jones1-5/+5
mach-virt doesn't yet support hotplug, but command lines specifying -smp <num>,maxcpus=<bigger-num> don't fail. Of course specifying bigger-num as something bigger than the machine supports, e.g. > 8 on a gicv2 machine, should fail though. This fix also makes mach- virt's max-cpus check truly consistent with the one in vl.c:main, as the one there was already correctly checking max-cpus instead of smp-cpus. Reported-by: Shannon Zhao <shannon.zhao@linaro.org> Signed-off-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1454511578-24863-1-git-send-email-drjones@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-11sd: limit 'req.cmd' while using as an array indexPrasad J Pandit1-2/+5
While processing standard SD commands, the 'req.cmd' value could lead to OOB read when used as an index into 'sd_cmd_type' or 'sd_cmd_class' arrays. Limit 'req.cmd' value to avoid such an access. Reported-by: Qinghao Tang <luodalongde@gmail.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453315857-1352-1-git-send-email-ppandit@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-11target-arm: Implement checking of fired watchpointSergey Fedorov3-14/+25
ARM stops before access to a location covered by watchpoint. Also, QEMU watchpoint fire is not necessarily an architectural watchpoint match. Unfortunately, that is hardly possible to ignore a fired watchpoint in debug exception handler. So move watchpoint check from debug exception handler to the dedicated watchpoint checking callback. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1454256948-10485-3-git-send-email-serge.fdrv@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-11cpu: Add callback to check architectural watchpoint matchSergey Fedorov3-2/+21
When QEMU watchpoint matches, that is not definitely an architectural watchpoint match yet. If it is a stop-before-access watchpoint then that is hardly possible to ignore it after throwing a TCG exception. A special callback is introduced to check for architectural watchpoint match before raising a TCG exception. Signed-off-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454256948-10485-2-git-send-email-serge.fdrv@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-11target-arm: Fix IL bit reported for Thumb VFP and Neon trapsPeter Maydell1-3/+3
All Thumb Neon and VFP instructions are 32 bits, so the IL bit in the syndrome register should be set. Pass false to the syn_* function's is_16bit argument rather than s->thumb so we report the correct IL bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454683067-16001-4-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Fix IL bit reported for Thumb coprocessor trapsPeter Maydell1-4/+4
All Thumb coprocessor instructions are 32 bits, so the IL bit in the syndrome register should be set. Pass false to the syn_* function's is_16bit argument rather than s->thumb so we report the correct IL bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454683067-16001-3-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Correct misleading 'is_thumb' syn_* parameter namesPeter Maydell1-14/+14
In syndrome register values, the IL bit indicates the instruction length, and is 1 for 4-byte instructions and 0 for 2-byte instructions. All A64 and A32 instructions are 4-byte, but Thumb instructions may be either 2 or 4 bytes long. Unfortunately we named the parameter to the syn_* functions for constructing syndromes "is_thumb", which falsely implies that it should be set for all Thumb instructions, rather than only the 16-bit ones. Fix the functions to name the parameter 'is_16bit' instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454683067-16001-2-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Enable EL3 for Cortex-A53 and Cortex-A57Peter Maydell1-0/+2
Enable EL3 support for our Cortex-A53 and Cortex-A57 CPU models. We have enough implemented now to be able to run real world code at least to some extent (I can boot ARM Trusted Firmware to the point where it pulls in OP-TEE and then falls over because it doesn't have a UEFI image it can chain to). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-8-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Implement NSACR trapping behaviourPeter Maydell1-4/+58
Implement some corner cases of the behaviour of the NSACR register on ARMv8: * if EL3 is AArch64 then accessing the NSACR from Secure EL1 with AArch32 should trap to EL3 * if EL3 is not present or is AArch64 then reads from NS EL1 and NS EL2 return constant 0xc00 It would in theory be possible to implement all these with a single reginfo definition, but for clarity we use three separate definitions for the three cases and install the right one based on the CPU feature flags. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-7-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Add isread parameter to CPAccessFnsPeter Maydell6-37/+68
System registers might have access requirements which need to be described via a CPAccessFn and which differ for reads and writes. For this to be possible we need to pass the access function a parameter to tell it whether the access being checked is a read or a write. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-6-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3Peter Maydell1-5/+43
The arm_generate_debug_exceptions() function as originally implemented assumes no EL2 or EL3. Since we now have much more of an implementation of those now, fix this assumption. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-5-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Use access_trap_aa32s_el1() for SCR and MVBARPeter Maydell1-2/+4
The registers MVBAR and SCR should have the behaviour of trapping to EL3 if accessed from Secure EL1, but we were incorrectly implementing them to UNDEF (which would trap to EL1). Fix this by using the new access_trap_aa32s_el1() access function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-4-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Implement MDCR_EL3 and SDCRPeter Maydell2-0/+27
Implement the MDCR_EL3 register (which is SDCR for AArch32). For the moment we implement it as reads-as-written. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1454506721-11843-3-git-send-email-peter.maydell@linaro.org
2016-02-11target-arm: Fix typo in comment in arm_is_secure_below_el3()Peter Maydell1-1/+1
Fix a typo where "EL2" was written but "EL3" intended. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com> Message-id: 1454506721-11843-2-git-send-email-peter.maydell@linaro.org
2016-02-10memory: fix usage of find_next_bit and find_next_zero_bitPaolo Bonzini1-19/+36
The last two arguments to these functions are the last and first bit to check relative to the base. The code was using incorrectly the first bit and the number of bits. Fix this in cpu_physical_memory_get_dirty and cpu_physical_memory_all_dirty. This requires a few changes in the iteration; change the code in cpu_physical_memory_set_dirty_range to match. Fixes: 5b82b70 Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Thomas Huth <thuth@redhat.com> Message-id: 1455113505-11237-1-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-09Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell32-1195/+5223
* switch to C11 atomics (Alex) * Coverity fixes for IPMI (Corey), i386 (Paolo), qemu-char (Paolo) * at long last, fail on wrong .pc files if -m32 is in use (Daniel) * qemu-char regression fix (Daniel) * SAS1068 device (Paolo) * memory region docs improvements (Peter) * target-i386 cleanups (Richard) * qemu-nbd docs improvements (Sitsofe) * thread-safe memory hotplug (Stefan) # gpg: Signature made Tue 09 Feb 2016 16:09:30 GMT using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" * remotes/bonzini/tags/for-upstream: (33 commits) qemu-char, io: fix ordering of arguments for UDP socket creation MAINTAINERS: add all-match entry for qemu-devel@ get_maintainer.pl: fall back to git if only lists are found target-i386: fix PSE36 mode docs/memory.txt: Improve list of different memory regions ipmi_bmc_sim: Add break to correct watchdog NMI check ipmi_bmc_sim: Fix off by one in check. ipmi: do not take/drop iothread lock target-i386: Deconstruct the cpu_T array target-i386: Tidy gen_add_A0_im target-i386: Rewrite leave target-i386: Rewrite gen_enter inline target-i386: Use gen_lea_v_seg in pusha/popa target-i386: Access segs via TCG registers target-i386: Use gen_lea_v_seg in stack subroutines target-i386: Use gen_lea_v_seg in gen_lea_modrm target-i386: Introduce mo_stacksize target-i386: Create gen_lea_v_seg char: fix repeated registration of tcp chardev I/O handlers kvm-all: trace: strerror fixup ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-09Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell5-9/+45
staging # gpg: Signature made Tue 09 Feb 2016 15:11:25 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/block-pull-request: block: add missing call to bdrv_drain_recurse blockjob: Fix hang in block_job_finish_sync iov: avoid memcpy for "simple" iov_from_buf/iov_to_buf Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-09qemu-char, io: fix ordering of arguments for UDP socket creationPaolo Bonzini2-2/+2
Two wrongs make a right, but they should be fixed anyway. Cc: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1455015557-15106-1-git-send-email-pbonzini@redhat.com>
2016-02-09Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2016-02-09' ↵Peter Maydell7-34/+71
into staging Error reporting patches for 2016-02-09 # gpg: Signature made Tue 09 Feb 2016 12:38:33 GMT using RSA key ID EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" * remotes/armbru/tags/pull-error-2016-02-09: HACKING: Add a section on error handling and reporting error: Improve documentation some more Use error_fatal to simplify obvious fatal errors (again) Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2016-02-09MAINTAINERS: add all-match entry for qemu-devel@Stephen Warren1-0/+5
Add an entry to MAINTAINERS that matches every patch, and requests the user send patches to qemu-devel@nongnu.org. It's not 100% obvious to project newcomers that all patches should be sent there; checkpatch doesn't say so, and since it mentions other lists to CC, the wording "the list" from the SubmitAPatch wiki page can be taken to mean only those lists, not the main list too. The F: entries were taken from a similar entry in the Linux kernel. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: John Snow <jsnow@redhat.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Message-Id: <1454987065-12961-1-git-send-email-swarren@wwwdotorg.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09get_maintainer.pl: fall back to git if only lists are foundPaolo Bonzini1-1/+1
It's not 100% obvious to project newcomers that all patches should be sent there; checkpatch doesn't say so, and since it mentions other lists to CC, the wording "the list" from the SubmitAPatch wiki page can be taken to mean only those lists, not the main list too. We would like therefore to add a catch-all entry for qemu-devel@nongnu.org. On its own, this would break fallback to git, because now every file has a maintainer of sorts. Modify get_maintainer.pl so that mailing lists (L: lines) no longer prevent the fallback, only humans (M: entries). Several pre-existing entries have a list but no human. These now fall back to git. That's a feature. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Markus Armbruster <armbru@redhat.com> Cc: John Snow <jsnow@redhat.com> Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Message-Id: <1454987065-12961-1-git-send-email-swarren@wwwdotorg.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: fix PSE36 modePaolo Bonzini1-2/+2
(pde & 0x1fe000) is a 32-bit integer; when shifting it into bits 39-32 the result is zero. Fix it by making the mask (and thus the result of the AND) a 64-bit integer. Reported by Coverity. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09docs/memory.txt: Improve list of different memory regionsPeter Maydell1-1/+25
Improve the part of the memory region documentation which describes the various different kinds of memory region: * add the missing types ROM, IOMMU and reservation * mention the functions used to initialize each type, as a hint for finding the API docs and examples of use Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1454007297-3971-1-git-send-email-peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09ipmi_bmc_sim: Add break to correct watchdog NMI checkCorey Minyard1-0/+2
It was falling through when it should have been a break. Found by Coverity. The logic could be simplified a bit with a fallthrough, probably the original thought, but that would be less clear, I think. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Shannon Zhao <zhaoshenglong@huawei.com> Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Message-Id: <1452519152-6500-3-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09ipmi_bmc_sim: Fix off by one in check.Corey Minyard1-1/+1
Found by Paolo. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Shannon Zhao <zhaoshenglong@huawei.com> Cc: Xiao Guangrong <guangrong.xiao@linux.intel.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com> Message-Id: <1452519152-6500-2-git-send-email-minyard@acm.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09ipmi: do not take/drop iothread lockPaolo Bonzini1-2/+0
This is not necessary and actually causes a hang; it was probably copied and pasted from KVM code, that is one of the very few places that run outside iothread lock. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Deconstruct the cpu_T arrayRichard Henderson1-607/+617
All references to cpu_T are done with a constant index. It aids readability to decompose the array into two scalar variables. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1436426122-12276-11-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Tidy gen_add_A0_imRichard Henderson1-22/+5
Merge gen_op_addl_A0_im and gen_op_addq_A0_im into gen_add_A0_im and clean up the ifdef. Replace the one remaining user of gen_op_addl_A0_im with gen_add_A0_im. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-10-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Rewrite leaveRichard Henderson1-14/+15
Unify the code across stack pointer widths. Fix the note about not updating ESP before the potential exception. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-9-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Rewrite gen_enter inlineRichard Henderson3-137/+34
Use gen_lea_v_seg for centralized segment base knowledge. Unify code across 32- and 64-bit. Fix note about "must save state" before using the out-of-line helpers. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-8-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in pusha/popaRichard Henderson1-27/+23
More centralization of handling of segment bases. Also fixes the note about 16-bit wrap around not fully handled. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-7-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Access segs via TCG registersRichard Henderson1-24/+28
Having segs[].base as a register significantly improves code generation for real and protected modes, particularly for TBs that have multiple memory references where the segment base can be held in a hard register through the TB. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-6-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in stack subroutinesRichard Henderson1-39/+13
I.e. gen_push_v, gen_pop_T0, gen_stack_A0. More centralization of handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-5-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Use gen_lea_v_seg in gen_lea_modrmRichard Henderson1-59/+23
Centralize handling of segment bases. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-4-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Introduce mo_stacksizeRichard Henderson1-14/+10
Centralize computation of a MO_SIZE for the stack pointer. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-3-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09target-i386: Create gen_lea_v_segRichard Henderson1-107/+53
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case; use this new function to implement gen_string_movl_A0_EDI, gen_string_movl_A0_ESI, gen_add_A0_ds_seg. Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1450379966-28198-2-git-send-email-rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09char: fix repeated registration of tcp chardev I/O handlersDaniel P. Berrange1-0/+4
In previous commit: commit f2001a7e0555b66d6db25a3ff1801540814045bb Author: Daniel P. Berrange <berrange@redhat.com> Date: Tue Jan 19 11:14:30 2016 +0000 char: don't assume telnet initialization will not block The code which writes the telnet initialization sequence moved to an event loop callback. If the TCP chardev is opened as a server in blocking mode (ie -serial telnet:0.0.0.0:3000,server,wait) this results in a state where the TCP chardev is connected, but not yet ready to send/recv data when virtual hardware is created. When the virtual hardware initialization registers its chardev callbacks, it triggers tcp_chr_update_read_handler, which will add I/O watches to the connection. When the telnet initialization finally runs, it will then call tcp_chr_connect to finish the connection setup. This will in turn add I/O watches to the connection too. There are now two sets of I/O watches registered on the same connection. This ultimately causes data loss on the connection, for example, when typing into the telnet console only every second byte is echoed back to the client. The same flaw can affect channels running with TLS encryption too, since they also have delayed connection setup completion. The fix is to update tcp_chr_update_read_handler so that it avoids registering watches if the connection is not fully setup yet. Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1454939707-10869-1-git-send-email-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09kvm-all: trace: strerror fixupAndrew Jones1-2/+2
Signed-off-by: Andrew Jones <drjones@redhat.com> Message-Id: <1454355464-14999-1-git-send-email-drjones@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09nbd: avoid unaligned uint64_t storeJohn Snow1-10/+10
cpu_to_be64w can't be used to make unaligned stores, but stq_be_p can. Also, the st?_be_p takes a void* so it is more clearly suited to the case where you're writing into a byte buffer. Use the st?_be_p family of functions everywhere in nbd/server.c. Signed-off-by: John Snow <jsnow@redhat.com> [Changed to use st?_be_p everywhere. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09scripts/kvm/kvm_stat: Fix tracefs access checkingJanosch Frank1-6/+17
On kernels build without CONFIG_TRACING kvm_stat will bail out even when traces are not used. This is not very helpful, especially if the user can't install a new kernel. Instead, we should warn the user and fall back to debugfs statistics. These changes check if trace statistics were selected without kernel support, warn with a small timeout, set the debugfs statistics option to True and the tracefs one to False. Fixes: 7aa4ee5 ('scripts/kvm/kvm_stat: Improve debugfs access checking') Signed-off-by: Janosch Frank <frankja@linux.vnet.ibm.com> Message-Id: <1454485291-43849-2-git-send-email-frankja@linux.vnet.ibm.com> [Exit if -t is passed explicitly. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09qemu-nbd: Fix texi sentence capitalisationSitsofe Wheeler1-19/+19
Capitalise the first letter of sentences (and reword for grammar) the options section of qemu-nbd.texi. Signed-off-by: Sitsofe Wheeler <sitsofe@yahoo.com> Message-Id: <1451979212-25479-4-git-send-email-sitsofe@yahoo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09qemu-nbd: Minor texi updatesSitsofe Wheeler1-12/+22
- Change some spacing. - Add disconnect usage to synopsis. - Highlight the command and its options in the synopsis. - Fix up the grammar in the description. - Move filename variable description out of the option table. - Add a description of the dev variable. - Remove duplicate entry for --format. - Reword --discard documentation. - Add --detect-zeroes documentation. - Add reference to qemu man page to see also section. Signed-off-by: Sitsofe Wheeler <sitsofe@yahoo.com> Message-Id: <1451979212-25479-3-git-send-email-sitsofe@yahoo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09qemu-nbd: Fix unintended texi verbatim formattingSitsofe Wheeler1-29/+29
Indented lines in the texi meant the perlpod produced interpreted the paragraph as being verbatim (thus formatting codes were not interpreted). Fix this by un-indenting problem lines. Signed-off-by: Sitsofe Wheeler <sitsofe@yahoo.com> Message-Id: <1451979212-25479-2-git-send-email-sitsofe@yahoo.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09hw: Add support for LSI SAS1068 (mptsas) devicePaolo Bonzini9-0/+3827
This adds the SAS1068 device, a SAS disk controller used in VMware that is oldish but widely supported and has decent performance. Unlike megasas, it presents itself as a SAS controller and not as a RAID controller. The device corresponds to the mptsas kernel driver in Linux. A few small things in the device setup are based on Don Slutz's old patch, but the device emulation was written from scratch based on Don's SeaBIOS patch and on the FreeBSD and Linux drivers. It is 2400 lines shorter than Don's patch (and roughly the same size as MegaSAS---also because it doesn't support the similar SPI controller), implements SCSI task management functions (with asynchronous cancellation), supports big-endian hosts, has complete support for migration and follows the QEMU coding standards much more closely. To write the driver, I first split Don's patch in two parts, with the configuration bits in one file and the rest in a separate file. I first left mptconfig.c in place and rewrote the rest, then deleted mptconfig.c as well. The configuration pages are still based mostly on VirtualBox's, though not exactly the same. However, the implementation is completely different. The contents of the pages themselves should not be copyrightable. Signed-off-by: Don Slutz <Don@CloudSwitch.com> Message-Id: <1347382813-5662-1-git-send-email-Don@CloudSwitch.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09scsi-generic: grab device and port SAS addresses from backendPaolo Bonzini3-0/+94
This lets a SAS adapter expose them through its own configuration mechanism. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09scsi: push WWN fields up to SCSIDevicePaolo Bonzini2-12/+12
SAS adapters need to access them in order to publish the SAS addresses of the end devices connected to them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09include/qemu/atomic.h: default to __atomic functionsAlex Bennée1-61/+131
The __atomic primitives have been available since GCC 4.7 and provide a richer interface for describing memory ordering requirements. As a bonus by using the primitives instead of hand-rolled functions we can use tools such as the ThreadSanitizer which need the use of well defined APIs for its analysis. If we have __ATOMIC defines we exclusively use the __atomic primitives for all our atomic access. Otherwise we fall back to the mixture of __sync and hand-rolled barrier cases. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <1453976119-24372-4-git-send-email-alex.bennee@linaro.org> [Use __ATOMIC_SEQ_CST for atomic_mb_read/atomic_mb_set on !POWER. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09configure: sanity check the glib library that pkg-config findsDaniel P. Berrange1-0/+24
Developers on 64-bit machines will often try to perform a 32-bit build of QEMU by running ./configure --extra-cflags="-m32" Unfortunately if PKG_CONFIG_LIBDIR is not set to point to the location of the 32-bit pkg-config files, then configure will silently pick up the 64-bit pkg-config files and still succeed. This causes a problem for glib because it means QEMU will be pulling in /usr/lib64/glib-2.0/include/glibconfig.h instead of /usr/lib/glib-2.0/include/glibconfig.h This causes problems because the 'gsize' type (defined as 'unsigned long') will no longer be fully compatible with the 'size_t' type (defined as 'unsigned int'). Although both are the same size, the compiler refuses to allow casts from 'unsigned long *' to 'unsigned int *' as they are different pointer types. This results in non-obvious compiler errors when building QEMU eg qga/commands-posix.c: In function ‘qmp_guest_set_user_password’: qga/commands-posix.c:1912:55: error: passing argument 2 of ‘g_base64_decode’ from incompatible pointer type [-Werror=incompatible-pointer-types] rawpasswddata = (char *)g_base64_decode(password, &rawpasswdlen); ^ In file included from /usr/include/glib-2.0/glib.h:35:0, from qga/commands-posix.c:14: /usr/include/glib-2.0/glib/gbase64.h:52:9: note: expected ‘gsize * {aka long unsigned int *}’ but argument is of type ‘size_t * {aka unsigned int *}’ guchar *g_base64_decode (const gchar *text, ^ cc1: all warnings being treated as errors To detect this problem, add a check to configure that verifies that GLIB_SIZEOF_SIZE_T matches sizeof(size_t). If this fails print a warning suggesting that the dev probably needs to set PKG_CONFIG_LIBDIR. On Fedora x86_64 it passes with any of: # ./configure # PKG_CONFIG_LIBDIR=/usr/lib/pkgconfig ./configure --extra-cflags="-m32" # PKG_CONFIG_LIBDIR=/usr/lib64/pkgconfig ./configure --extra-cflags="-m64" And fails with a mis-match # PKG_CONFIG_LIBDIR=/usr/lib64/pkgconfig ./configure --extra-cflags="-m32" # PKG_CONFIG_LIBDIR=/usr/lib/pkgconfig ./configure --extra-cflags="-m64" ERROR: sizeof(size_t) doesn't match GLIB_SIZEOF_SIZE_T. You probably need to set PKG_CONFIG_LIBDIR to point to the right pkg-config files for your build target Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1453885245-15562-1-git-send-email-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09qemu-char: Keep pty slave file descriptor open until the master is closedPaolo Bonzini1-1/+3
If a process opens the slave pts device, writes data to it, then immediately closes it, the data doesn't reliably get delivered to the emulated serial port. This seems to be because a read of the master pty device returns EIO on Linux if no process has the pts device open, even when data is waiting "in the pipe". A fix seems to be for QEMU to keep the pts file descriptor open until the pty is closed, as per the below patch. Signed-off-by: Ashley Jonathan <jonathan.ashley@altran.com> Message-Id: <AC19797808C8D548ABDE0CA4A97AA30A30DEB409@XMB-DCFR-37.europe.corp.altran.com> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2016-02-09memory: RCU ram_list.dirty_memory[] for safe RAM hotplugStefan Hajnoczi3-43/+225
Although accesses to ram_list.dirty_memory[] use atomics so multiple threads can safely dirty the bitmap, the data structure is not fully thread-safe yet. This patch handles the RAM hotplug case where ram_list.dirty_memory[] is grown. ram_list.dirty_memory[] is change from a regular bitmap to an RCU array of pointers to fixed-size bitmap blocks. Threads can continue accessing bitmap blocks while the array is being extended. See the comments in the code for an in-depth explanation of struct DirtyMemoryBlocks. I have tested that live migration with virtio-blk dataplane works. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <1453728801-5398-2-git-send-email-stefanha@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
generated by cgit v1.1 at 2025-02-11 19:57:39 +0000