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2022-07-11target/arm: Mark FTSMUL, FTMAD, FADDA as non-streamingRichard Henderson2-7/+11
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark PMULL, FMMLA as non-streamingRichard Henderson2-11/+15
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark BDEP, BEXT, BGRP, COMPACT, FEXPA, FTSSEL as non-streamingRichard Henderson2-13/+12
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark RDFFR, WRFFR, SETFFR as non-streamingRichard Henderson2-5/+6
Mark these as a non-streaming instructions, which should trap if full a64 support is not enabled in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Mark ADR as non-streamingRichard Henderson3-5/+11
Mark ADR as a non-streaming instruction, which should trap if full a64 support is not enabled in streaming mode. Removing entries from sme-fa64.decode is an easy way to see what remains to be done. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Trap non-streaming usage when Streaming SVE is activeRichard Henderson8-2/+195
This new behaviour is in the ARM pseudocode function AArch64.CheckFPAdvSIMDEnabled, which applies to AArch32 via AArch32.CheckAdvSIMDOrFPEnabled when the EL to which the trap would be delivered is in AArch64 mode. Given that ARMv9 drops support for AArch32 outside EL0, the trap EL detection ought to be trivially true, but the pseudocode still contains a number of conditions, and QEMU has not yet committed to dropping A32 support for EL[12] when v9 features are present. Since the computation of SME_TRAP_NONSTREAMING is necessarily different for the two modes, we might as well preserve bits within TBFLAG_ANY and allocate separate bits within TBFLAG_A32 and TBFLAG_A64 instead. Note that DDI0616A.a has typos for bits [22:21] of LD1RO in the table of instructions illegal in streaming mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Add infrastructure for disas_smeRichard Henderson5-1/+64
This includes the build rules for the decoder, and the new file for translation, but excludes any instructions. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-11target/arm: Handle SME in aarch64_cpu_dump_stateRichard Henderson1-1/+16
Dump SVCR, plus use the correct access check for Streaming Mode. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220708151540.18136-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-08Merge tag 'pull-target-arm-20220707' of ↵Richard Henderson13-538/+684
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * hw/arm/virt: dt: add rng-seed property * Fix MTE check in sve_ldnfff1_r * Record tagged bit for user-only in sve_probe_page * Correctly implement OS Lock and OS DoubleLock * Implement DBGDEVID, DBGDEVID1, DBGDEVID2 registers * Fix qemu-system-arm handling of LPAE block descriptors for highmem # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmLG0O8ZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3h1MEACnTd+jfssa/MdtQPP8N+cp # cvrdrW+V9iho1vLPGG3d6yni6T8IMdulA5OvSkiNz2IaspY3z3u/t01PCpqEF0tA # nl3HxA65ddehzG8QHpORiP2DIJfuYUcMaruK2zMcC//0EXBOVI215hkR7oNyC0r9 # PrYb+tiDVL1t3xzXWNKMoolZwUjS6M6dloxEu2b/d0tOBvtBLI0E7y9taANHCnmZ # 8r7ih0WRELo1rzveZVOXqnZGLUjFzbCurHCmshN6xr2V6iilBaLoaGHovZ2c489Z # Fz/Ui1tyvDUoajr/Ck57GYo0BwDf9dKYkl5RkchdeY+cA88CgJAVK5pT0Rrybpf0 # lMgSAalIFcnIr2kjdnWRUqL02t+HgnOnsBTSUpgiwMNKwjfMN5NDi9294GuMCu2h # 7UyuAkQvfTwoQyFzJYzuapcnB6i5BvQjq6GxSmogzuR6kNSFptNOGimMhqCO4kN0 # fixOHOOE/aj7QoXq33V9u3ESY1IleDMX6+Zff2RLmVQYZpQKW6LpCfuwgnZrZEN3 # 4hPiL+00bY9pWlXvvEHdu0/XYx8kPXtmdzgzpm80edCLUMFOVMDQMQE1Zy/qzC7S # 8ryfC2EvSQuigD1+s6I9WxCnHVv5Byz+DXgRCjRsitDPVu2kFcEgAibzz9K1WVUW # qwQP4WGUzFD/LNUwO/Vryw== # =TzwD # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 05:56:23 PM +0530 # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220707' of https://git.linaro.org/people/pmaydell/qemu-arm: target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmem target/arm: Correctly implement Feat_DoubleLock target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2 target/arm: Suppress debug exceptions when OS Lock set target/arm: Move define_debug_regs() to debug_helper.c target/arm: Fix code style issues in debug helper functions target/arm: Record tagged bit for user-only in sve_probe_page target/arm: Fix MTE check in sve_ldnfff1_r hw/arm/virt: dt: add rng-seed property Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-07Merge tag 'pull-request-2022-07-07' of https://gitlab.com/thuth/qemu into ↵Richard Henderson13-138/+129
staging * Check validity of the address in the SET PREFIX instruction * Fix booting from devices that use 4k sectors, but are not like DASDs * Re-evaluate pending interrupts after EXECUTE of certain instructions # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmLGhkURHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbU76Q//Y4mEXxWZDpJTg7tL5SZP+UzBVttnCifv # 6q+2I0keOUs6wFhPq8TzBqkazT9wlv51cNrY2Q3fU9I3dpDeRbAXZR34UD4kw5an # Q+ZQcebuGSKLjzMrIb1DLAieq8OmZR5FvDUu16BbeJr6GIQIE80lMRfWh9j30UfW # tlxkXr15BnyPx6m0rSGwzkZD2vgfj5zSUrDtYJcUsfypIA9OOBMA7yNGNlO+d94V # UZiKgNQtAoBNm4hZh2M86nsUtem+WpMTZQnDnCpMLYvFV/u9jRQBFSR+Ay41hcEN # WYuLK61rkjc9gPWSjeNNT28x8RMvFJU4YNn1UDiMRSzrigxeui6MOW3SI/h3y6tI # 94yXmXV2IuDMibvOjK07nkDaEItqPxfj6zuM2xW1Nc+l8Sk12korFBpk/AZiD0Jo # R3u36efci3zNqDRDJvhGUv8sGcv0mwO7Agq1Bm3h5941gYwzQKILHCShL7DPzvQa # h+K1MsT7vWfh5++unkGUrN/Zd9CazEylbDuWtywK8lgQcTGDO/9rab8GeXfH/5es # Tp0RGJwxmalgrAHZPK9lqgpQaGw92ct2G5odvc82EXQhgccnN9mh54BHPfdKs95E # JZVrXtZH3Gtgl5MGZ+yJevWSc9h1iRnRF4a7QC3UlVBjA/9yAWzQUAnNGZOamE/s # F+pi89oWLn8= # =UsTi # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 12:37:49 PM +0530 # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-07-07' of https://gitlab.com/thuth/qemu: target/s390x: Exit tb after executing ex_value target/s390x: Remove DISAS_PC_STALE_NOCHAIN target/s390x: Remove DISAS_PC_STALE target/s390x: Remove DISAS_GOTO_TB pc-bios/s390-ccw: Update the s390-ccw bios binaries with the virtio-blk fixes pc-bios/s390-ccw/netboot.mak: Ignore Clang's warnings about GNU extensions pc-bios/s390-ccw/virtio: Remove "extern" keyword from prototypes pc-bios/s390-ccw/virtio-blkdev: Request the right feature bits pc-bios/s390-ccw: Split virtio-scsi code from virtio_blk_setup_device() pc-bios/s390-ccw/virtio: Beautify the code for reading virtqueue configuration pc-bios/s390-ccw/virtio: Read device config after feature negotiation pc-bios/s390-ccw/virtio: Set missing status bits while initializing pc-bios/s390-ccw/virtio-blkdev: Remove virtio_assume_scsi() pc-bios/s390-ccw/virtio-blkdev: Simplify/fix virtio_ipl_disk_is_valid() pc-bios/s390-ccw/bootmap: Improve the guessing logic in zipl_load_vblk() pc-bios/s390-ccw/virtio: Introduce a macro for the DASD block size pc-bios/s390-ccw: Add a proper prototype for main() target/s390x/tcg: SPX: check validity of new prefix Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-07target/arm: Fix qemu-system-arm handling of LPAE block descriptors for highmemPeter Maydell1-1/+1
In commit 39a1fd25287f5d we fixed a bug in the handling of LPAE block descriptors where we weren't correctly zeroing out some RES0 bits. However this fix has a bug because the calculation of the mask is done at the wrong width: in descaddr &= ~(page_size - 1); page_size is a target_ulong, so in the 'qemu-system-arm' binary it is only 32 bits, and the effect is that we always zero out the top 32 bits of the calculated address. Fix the calculation by forcing the mask to be calculated with the same type as descaddr. This only affects 32-bit CPUs which support LPAE (e.g. cortex-a15) when used on board models which put RAM or devices above the 4GB mark and when the 'qemu-system-arm' executable is being used. It was also masked in 7.0 by the main bug reported in https://gitlab.com/qemu-project/qemu/-/issues/1078 where the virt board incorrectly does not enable 'highmem' for 32-bit CPUs. The workaround is to use 'qemu-system-aarch64' with the same command line. Reported-by: He Zhe <zhe.he@windriver.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220627134620.3190252-1-peter.maydell@linaro.org Fixes: 39a1fd25287f5de ("target/arm: Fix handling of LPAE block descriptors") Cc: qemu-stable@nongnu.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07target/arm: Correctly implement Feat_DoubleLockPeter Maydell2-2/+38
The architecture defines the OS DoubleLock as a register which (similarly to the OS Lock) suppresses debug events for use in CPU powerdown sequences. This functionality is required in Arm v7 and v8.0; from v8.2 it becomes optional and in v9 it must not be implemented. Currently in QEMU we implement the OSDLR_EL1 register as a NOP. This is wrong both for the "feature implemented" and the "feature not implemented" cases: if the feature is implemented then the DLK bit should read as written and cause suppression of debug exceptions, and if it is not implemented then the bit must be RAZ/WI. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07target/arm: Implement AArch32 DBGDEVID, DBGDEVID1, DBGDEVID2Peter Maydell4-0/+55
Starting with v7 of the debug architecture, there are three extra ID registers that add information on top of that provided in DBGDIDR. These are DBGDEVID, DBGDEVID1 and DBGDEVID2. In the v7 debug architecture, DBGDEVID is optional, present only of DBGDIDR.DEVID_imp is set. In v7.1 all three must be present. Implement the missing registers. Note that we only need to set the values in the ARMISARegisters struct for the CPUs Cortex-A7, A15, A53, A57 and A72 (plus the 32-bit 'max' which uses the Cortex-A53 values): earlier CPUs didn't implement v7 of the architecture, and our other 64-bit CPUs (Cortex-A76, Neoverse-N1 and A64fx) don't have AArch32 support at EL1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-5-peter.maydell@linaro.org
2022-07-07target/arm: Suppress debug exceptions when OS Lock setPeter Maydell1-0/+3
The "OS Lock" in the Arm debug architecture is a way for software to suppress debug exceptions while it is trying to power down a CPU and save the state of the breakpoint and watchpoint registers. In QEMU we implemented the support for writing the OS Lock bit via OSLAR_EL1 and reading it via OSLSR_EL1, but didn't implement the actual behaviour. The required behaviour with the OS Lock set is: * debug exceptions (apart from BKPT insns) are suppressed * some MDSCR_EL1 bits allow write access to the corresponding EDSCR external debug status register that they shadow (we can ignore this because we don't implement external debug) * similarly with the OSECCR_EL1 which shadows the EDECCR (but we don't implement OSECCR_EL1 anyway) Implement the missing behaviour of suppressing debug exceptions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-4-peter.maydell@linaro.org
2022-07-07target/arm: Move define_debug_regs() to debug_helper.cPeter Maydell4-530/+538
The target/arm/helper.c file is very long and is a grabbag of all kinds of functionality. We have already a debug_helper.c which has code for implementing architectural debug. Move the code which defines the debug-related system registers out to this file also. This affects the define_debug_regs() function and the various functions and arrays which are used only by it. The functions raw_write() and arm_mdcr_el2_eff() and define_debug_regs() now need to be global rather than local to helper.c; everything else is pure code movement. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-3-peter.maydell@linaro.org
2022-07-07target/arm: Fix code style issues in debug helper functionsPeter Maydell1-20/+38
Before moving debug system register helper functions to a different file, fix the code style issues (mostly block comment syntax) so checkpatch doesn't complain about the code-motion patch. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220630194116.3438513-2-peter.maydell@linaro.org
2022-07-07target/arm: Record tagged bit for user-only in sve_probe_pageRichard Henderson1-0/+3
Fixes a bug in that we were not honoring MTE from user-only SVE. Copy the user-only MTE logic from allocation_tag_mem into sve_probe_page. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07target/arm: Fix MTE check in sve_ldnfff1_rRichard Henderson1-1/+1
The comment was correct, but the test was not: disable mte if tagged is *not* set. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07hw/arm/virt: dt: add rng-seed propertyJason A. Donenfeld4-24/+47
In 60592cfed2 ("hw/arm/virt: dt: add kaslr-seed property"), the kaslr-seed property was added, but the equally as important rng-seed property was forgotten about, which has identical semantics for a similar purpose. This commit implements it in exactly the same way as kaslr-seed. It then changes the name of the disabling option to reflect that this has more to do with randomness vs determinism, rather than something particular about kaslr. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com> [PMM: added deprecated.rst section for the deprecation] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-07-07Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into stagingRichard Henderson1-8/+4
Pull request # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmLGlXYACgkQnKSrs4Gr # c8jfNwf/fFfx4mPFwdnud9cseb9jFU44/RWJ2rJlYerbHIUUNvW0vAv1nGjuVVWT # DeHxG2pkHPJQ5u4y/oivq4CCGGQ/Ukx/IEqJsnXEpWyKHosHJHlBrePt+/x+uygA # RUOfReSq4gsK1FIcluuO/wnBzgREXL6lBsyIHtvG57hYSSESS10fCdRXBPJJMBcF # pI8LpEgID5KuqPjXoO/Cv4qOXpOpO8540b8mzHP8wY1tYbBP9H4uqO1MJ/OFz8GU # wDeRJEa66o9kwV7oym8T+KdZHR1f+Yfk0o1WmtfUgECJkM/8aUTvNog5SVeaHKqV # 0ZQ4L6j8cprKXl9Ui+LXFp2YMMXV9g== # =IjWZ # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 01:42:38 PM +0530 # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] * tag 'block-pull-request' of https://gitlab.com/stefanha/qemu: block/io_uring: clarify that short reads can happen io_uring: fix short read slow path Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-07block/io_uring: clarify that short reads can happenStefan Hajnoczi1-6/+2
Jens Axboe has confirmed that short reads are rare but can happen: https://lore.kernel.org/io-uring/YsU%2FCGkl9ZXUI+Tj@stefanha-x1.localdomain/T/#m729963dc577d709b709c191922e98ec79d7eef54 The luring_resubmit_short_read() comment claimed they were only due to a specific io_uring bug that was fixed in Linux commit 9d93a3f5a0c ("io_uring: punt short reads to async context"), which is wrong. Dominique Martinet found that a btrfs bug also causes short reads. There may be more kernel code paths that result in short reads. Let's consider short reads fair game. Cc: Dominique Martinet <dominique.martinet@atmark-techno.com> Based-on: <20220630010137.2518851-1-dominique.martinet@atmark-techno.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Message-id: 20220706080341.1206476-1-stefanha@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-07-07io_uring: fix short read slow pathDominique Martinet1-2/+2
sqeq.off here is the offset to read within the disk image, so obviously not 'nread' (the amount we just read), but as the author meant to write its current value incremented by the amount we just read. Normally recent versions of linux will not issue short reads, but it can happen so we should fix this. This lead to weird image corruptions when short read happened Fixes: 6663a0a33764 ("block/io_uring: implements interfaces for io_uring") Link: https://lkml.kernel.org/r/YrrFGO4A1jS0GI0G@atmark-techno.com Signed-off-by: Dominique Martinet <dominique.martinet@atmark-techno.com> Message-Id: <20220630010137.2518851-1-dominique.martinet@atmark-techno.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-07-07Merge tag 'pull-ppc-20220706' of https://gitlab.com/danielhb/qemu into stagingRichard Henderson33-576/+885
ppc patch queue for 2022-07-06: This queue consists of improvements and bug fixes in TCG, powernv and pSeries, with some fixes in other areas as well. - tcg and target/ppc: BCDA and mffscdrn implementations, Remove CONFIG_INT128 conditional code - fix '-cpu max' alias - remove '-cpu default' alias - spapr: fixes in DDW handling, H_WATCHDOG support - powernv: cleanups in the pnv-phb3/4 models - fix core type of MPC8555 and MPC8560 models # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQQX6/+ZI9AYAK8oOBk82cqW3gMxZAUCYsXrpgAKCRA82cqW3gMx # ZBe9AP4oqMTFw7r9EQPJU4QFMUeAVABl4o0xNb2wLyYov9CtKAD+LoVERSmtLTJ1 # kFpgBrRTWKVylaLEdZQoTdFlJeBwzQg= # =GPG1 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 07 Jul 2022 01:38:06 AM +0530 # gpg: using EDDSA key 17EBFF9923D01800AF2838193CD9CA96DE033164 # gpg: Good signature from "Daniel Henrique Barboza <danielhb413@gmail.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 17EB FF99 23D0 1800 AF28 3819 3CD9 CA96 DE03 3164 * tag 'pull-ppc-20220706' of https://gitlab.com/danielhb/qemu: (34 commits) target/ppc: Fix MPC8555 and MPC8560 core type to e500v1 target/ppc/cpu-models: Remove the "default" CPU alias target/ppc: Return default CPU for max CPU target/ppc: implement cdtbcd target/ppc: implement cbcdtd target/ppc: implement addg6s target/ppc: Add flag for ISA v2.06 BCDA instructions tests/tcg/ppc64: Add mffsce test target/ppc: Implement mffscdrn[i] instructions target/ppc: Move mffs[.] to decodetree target/ppc: Move mffsl to decodetree target/ppc: Move mffsce to decodetree target/ppc: Move mffscrn[i] to decodetree target/ppc: Fix insn32.decode style issues ppc/spapr: Implement H_WATCHDOG ppc: Define SETFIELD for the ppc target target/ppc: use int128.h methods in vsubcuq target/ppc: use int128.h methods in vsubecuq and vsubeuqm target/ppc: use int128.h methods in vsubuqm target/ppc: use int128.h methods in vaddcuq ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-06target/s390x: Exit tb after executing ex_valueRichard Henderson1-1/+1
When EXECUTE sets ex_value to interrupt the constructed instruction, we implicitly disable interrupts so that the value is not corrupted. Exit to the main loop after execution, so that we re-evaluate any pending interrupts. Reported-by: Sven Schnelle <svens@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-5-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06target/s390x: Remove DISAS_PC_STALE_NOCHAINRichard Henderson1-10/+11
Replace this with a flag: exit_to_mainloop. We can now control the exit for each of DISAS_TOO_MANY, DISAS_PC_UPDATED, and DISAS_PC_CC_UPDATED, and fold in the check for PER. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-4-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06target/s390x: Remove DISAS_PC_STALERichard Henderson1-9/+4
There is nothing to distinguish this from DISAS_TOO_MANY. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-3-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06target/s390x: Remove DISAS_GOTO_TBRichard Henderson1-6/+2
There is nothing to distinguish this from DISAS_NORETURN. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220702060228.420454-2-richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw: Update the s390-ccw bios binaries with the virtio-blk fixesThomas Huth2-0/+0
The binaries have been recompiled with the fixes from the previous patches. Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/netboot.mak: Ignore Clang's warnings about GNU extensionsThomas Huth1-2/+5
When compiling the s390-ccw bios with Clang (v14.0), there is currently an unuseful warning like this: CC pc-bios/s390-ccw/ipv6.o ../../roms/SLOF/lib/libnet/ipv6.c:447:18: warning: variable length array folded to constant array as an extension [-Wgnu-folding-constant] unsigned short raw[ip6size]; ^ SLOF is currently GCC-only and cannot be compiled with Clang yet, so it is expected that such extensions sneak in there - and as long as we don't want to compile the code with a compiler that is neither GCC or Clang, it is also not necessary to avoid such extensions. Thus these GNU-extension related warnings are completely useless in the s390-ccw bios, especially in the code that is coming from SLOF, so we should simply disable the related warnings here now. Message-Id: <20220704111903.62400-13-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio: Remove "extern" keyword from prototypesThomas Huth1-6/+6
All the other protytpes in the headers here do not use the "extern" keyword, so let's unify this by removing the "extern" from the misfits, too. Message-Id: <20220704111903.62400-12-thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio-blkdev: Request the right feature bitsThomas Huth1-0/+4
The virtio-blk code uses the block size and geometry fields in the config area. According to the virtio-spec, these have to be negotiated with the right feature bits during initialization, otherwise they might not be available. QEMU is so far very forgiving and always provides them, but we should not rely on this behavior, so let's better request them properly via the VIRTIO_BLK_F_GEOMETRY and VIRTIO_BLK_F_BLK_SIZE feature bits. Message-Id: <20220704111903.62400-11-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw: Split virtio-scsi code from virtio_blk_setup_device()Thomas Huth4-27/+38
The next patch is going to add more virtio-block specific code to virtio_blk_setup_device(), and if the virtio-scsi code is also in there, this is more cumbersome. And the calling function virtio_setup() in main.c looks at the device type already anyway, so it's more logical to separate the virtio-scsi stuff into a new function in virtio-scsi.c instead. Message-Id: <20220704111903.62400-10-thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio: Beautify the code for reading virtqueue configurationThomas Huth1-3/+2
It looks nicer if we separate the run_ccw() from the IPL_assert() statement, and the error message should talk about "virtio device" instead of "block device", since this code is nowadays used for non-block (i.e. network) devices, too. Message-Id: <20220704111903.62400-9-thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio: Read device config after feature negotiationThomas Huth1-4/+3
Feature negotiation should be done first, since some fields in the config area can depend on the negotiated features and thus should rather be read afterwards. While we're at it, also adjust the error message here a little bit (the code is nowadays used for non-block virtio devices, too). Message-Id: <20220704111903.62400-8-thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio: Set missing status bits while initializingThomas Huth1-4/+14
According chapter "3.1.1 Driver Requirements: Device Initialization" of the Virtio specification (v1.1), a driver for a device has to set the ACKNOWLEDGE and DRIVER bits in the status field after resetting the device. The s390-ccw bios skipped these steps so far and seems like QEMU never cared. Anyway, it's better to follow the spec, so let's set these bits now in the right spots, too. Message-Id: <20220704111903.62400-7-thuth@redhat.com> Acked-by: Christian Borntraeger <borntraeger@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio-blkdev: Remove virtio_assume_scsi()Thomas Huth2-25/+0
The virtio_assume_scsi() function is very questionable: First, it is only called for virtio-blk, and not for virtio-scsi, so the naming is already quite confusing. Second, it is called if we detected a "invalid" IPL disk, trying to fix it by blindly setting a sector size of 512. This of course won't work in most cases since disks might have a different sector size for a reason. Thus let's remove this strange function now. The calling code can also be removed completely, since there is another spot in main.c that does "IPL_assert(virtio_ipl_disk_is_valid(), ...)" to make sure that we do not try to IPL from an invalid device. Message-Id: <20220704111903.62400-6-thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio-blkdev: Simplify/fix virtio_ipl_disk_is_valid()Thomas Huth2-36/+7
The s390-ccw bios fails to boot if the boot disk is a virtio-blk disk with a sector size of 4096. For example: dasdfmt -b 4096 -d cdl -y -p -M quick /dev/dasdX fdasd -a /dev/dasdX install a guest onto /dev/dasdX1 using virtio-blk qemu-system-s390x -nographic -hda /dev/dasdX1 The bios then bails out with: ! Cannot read block 0 ! Looking at virtio_ipl_disk_is_valid() and especially the function virtio_disk_is_scsi(), it does not really make sense that we expect only such a limited disk geometry (like a block size of 512) for our boot disks. Let's relax the check and allow everything that remotely looks like a sane disk. Message-Id: <20220704111903.62400-5-thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/bootmap: Improve the guessing logic in zipl_load_vblk()Thomas Huth1-4/+23
The logic of trying an final ISO or ECKD boot on virtio-block devices is very weird: Since the geometry hardly ever matches in virtio_disk_is_scsi(), virtio_blk_setup_device() always sets a "guessed" disk geometry via virtio_assume_scsi() (which is certainly also wrong in a lot of cases). zipl_load_vblk() then sees that there's been a "virtio_guessed_disk_nature" and tries to fix up the geometry again via virtio_assume_iso9660() before always trying to do ipl_iso_el_torito(). That's a very brain-twisting way of attempting to boot from ISO images, which won't work anymore after the following patches that will clean up the virtio_assume_scsi() mess (and thus get rid of the "virtio_guessed_disk_nature" here). Let's try a better approach instead: ISO files always have a magic string "CD001" at offset 0x8001 (see e.g. the ECMA-119 specification) which we can use to decide whether we should try to boot in ISO 9660 mode (which we should also try if we see a sector size of 2048). And if we were not able to boot in ISO mode here, the final boot attempt before panicking is to boot in ECKD mode. Since this is our last boot attempt anyway, simply always assume the ECKD geometry here (if the sector size was not 4096 yet), so that we also do not depend on the guessed disk geometry from virtio_blk_setup_device() here anymore. Message-Id: <20220704111903.62400-4-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw/virtio: Introduce a macro for the DASD block sizeThomas Huth2-1/+2
Use VIRTIO_DASD_DEFAULT_BLOCK_SIZE instead of the magic value 4096. Message-Id: <20220704111903.62400-3-thuth@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06pc-bios/s390-ccw: Add a proper prototype for main()Thomas Huth2-2/+2
Older versions of Clang complain if there is no prototype for main(). Add one, and while we're at it, make sure that we use the same type for main.c and netmain.c - since the return value does not matter, declare the return type of main() as "void". Message-Id: <20220704111903.62400-2-thuth@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Eric Farman <farman@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-07-06Merge tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k ↵Richard Henderson3-1/+25
into staging Pull request m68k 20220706 pass RNG seed via bootinfo block # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEEzS913cjjpNwuT1Fz8ww4vT8vvjwFAmLFdGkSHGxhdXJlbnRA # dml2aWVyLmV1AAoJEPMMOL0/L748oSUP/1W3bsPkFTGi0F77RuVFo8jBdvnCznH+ # mh/9FJdILuOla2Z+N+Y8dBErp9ZPk0FNAOFboZyX6+UzS6G64nLeIqEKIK+gfoWA # qImxlCnip3d0tS0/od+x5+wOYYXqTqerU++i/J/bACMjciAqbUB3GvZvmP32ixma # cqkOo0jHawRx9k0tzuWcP1zgmGHfHIJQEu/GdBUKeTYIQ7P0ACK0qIijndb4kZYO # OYuXF4TNncojzqJf6wOpvYbpifmpL2RkJmhHE2LLgIHeuZxV+9AdFmhbp7/D1kCw # 64qRn2oQHxuHQWL87ZOUXGmARcecW58uwLgUrkXIR8ZjHu8Y4KCLfnDrVHzDBfjE # AA8Jgbo07ASuGnc/DR9EieZNBFZT7sMK9VccUCI78G3ExR7xL0JkRGqc7nnX5WK/ # JDf9dDNVqlEbVJ5JUbQQBl80bTRf9toHlfbwbwDd8Ow5x/R1e62lXIukx4xo+oTW # DhjYoGqF/grcUQop50jS9vU9BMICPqmUp+4ueoj08kzAa96Z5D7ptXVY5WZFlk/W # DN5D1MYFflxt/FmSDBUpT/9u1GUYOmod3dt69x8Jk5nSkKjQECIed1kxndqIKhQI # zmeo3MKgf2HEJ0tobOe9UzD24DrvbK9g5IPFQTZDu/6u1IzNUgGi/YZUy7N1Owup # PG+ez9RwhSzV # =lR7N # -----END PGP SIGNATURE----- # gpg: Signature made Wed 06 Jul 2022 05:09:21 PM +0530 # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [undefined] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [undefined] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * tag 'm68k-for-7.1-pull-request' of https://github.com/vivier/qemu-m68k: m68k: virt: pass RNG seed via bootinfo block m68k: use correct variable name in boot info string macro Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-07-06target/ppc: Fix MPC8555 and MPC8560 core type to e500v1Pali Rohár2-14/+14
Commit 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") changed core type of MPC8555 and MPC8560 from e500v1 to e500v2. But both MPC8555 and MPC8560 have just e500v1 cores, there are no features of e500v2 cores. It can be verified by reading NXP documentations: https://www.nxp.com/docs/en/data-sheet/MPC8555EEC.pdf https://www.nxp.com/docs/en/data-sheet/MPC8560EC.pdf https://www.nxp.com/docs/en/reference-manual/MPC8555ERM.pdf https://www.nxp.com/docs/en/reference-manual/MPC8560RM.pdf Therefore fix core type of MPC8555 and MPC8560 back to e500v1. Just for completeness, here is list of all Motorola/Freescale/NXP processors which were released and have e500v1 or e500v2 cores: e500v1: MPC8540 MPC8541 MPC8555 MPC8560 e500v2: BSC9131 BSC9132 C291 C292 C293 MPC8533 MPC8535 MPC8536 MPC8543 MPC8544 MPC8545 MPC8547 MPC8548 MPC8567 MPC8568 MPC8569 MPC8572 P1010 P1011 P1012 P1013 P1014 P1015 P1016 P1020 P1021 P1022 P1024 P1025 P2010 P2020 Sorted alphabetically; not by release date / generation / feature set. All this is from public information available on NXP website. Seems that qemu has support only for some subset of MPC85xx processors. Historically processors with e500 cores have mpc85xx family codename and lot of software have them in mpc85xx architecture subdirectory. Note that GCC uses -mcpu=8540 option for specifying e500v1 core and -mcpu=8548 option for specifying e500v2 core. So sometimes (mpc)8540 is alias for e500v1 and (mpc)8548 is alias for e500v2. Fixes: 80d11f4467c4 ("Add definitions for Freescale PowerPC implementations") Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20220703195029.23793-1-pali@kernel.org> [danielhb: added more context in the commit msg] Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc/cpu-models: Remove the "default" CPU aliasThomas Huth1-1/+1
QEMU emulates a *lot* of PowerPC-based machines - having a CPU that is named "default" and cannot be used with most of those machines sounds just wrong. Thus let's remove this old and confusing alias now. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220705151030.662140-1-thuth@redhat.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc: Return default CPU for max CPUMurilo Opsfelder Araujo2-1/+19
All ppc CPUs represent hardware that exists in the real world, i.e.: we do not have a "max" CPU with all possible emulated features enabled. Return the default CPU type for the machine because that has greater chance of being useful as the "max" CPU. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1038 Cc: Cédric Le Goater <clg@kaod.org> Cc: Daniel Henrique Barboza <danielhb413@gmail.com> Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Greg Kurz <groug@kaod.org> Cc: Matheus K. Ferst <matheus.ferst@eldorado.org.br> Cc: Thomas Huth <thuth@redhat.com> Signed-off-by: Murilo Opsfelder Araujo <muriloo@linux.ibm.com> Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220628205513.81917-1-muriloo@linux.ibm.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc: implement cdtbcdMatheus Ferst4-0/+35
Implements the Convert Declets To Binary Coded Decimal instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsFromDPD, DPD2BCD, etc), a positive decimal32 with zero exponent is used as an intermediate value to convert the declets. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-12-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc: implement cbcdtdMatheus Ferst4-0/+51
Implements the Convert Binary Coded Decimal To Declets instruction. Since libdecnumber doesn't expose the methods for direct conversion (decDigitsToDPD, BCD2DPD, etc.), the BCD values are converted to decimal32 format, from which the declets are extracted. Where the behavior is undefined, we try to match the result observed in a POWER9 DD2.3. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-11-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc: implement addg6sMatheus Ferst2-0/+41
Implements the following Power ISA v2.06 instruction: addg6s: Add and Generate Sixes Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br> Message-Id: <20220629162904.105060-10-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc: Add flag for ISA v2.06 BCDA instructionsMatheus Ferst2-5/+10
Adds an insns_flags2 for the BCD assist instructions introduced in Power ISA 2.06. These instructions are not listed in the manuals for e5500[1] and e6500[2], so the flag is only added for POWER7/8/9/10 models. [1] https://www.nxp.com/files-static/32bit/doc/ref_manual/EREF_RM.pdf [2] https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220629162904.105060-9-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06tests/tcg/ppc64: Add mffsce testVíctor Colombo3-0/+39
Add mffsce test to check both the return value and the new fpscr stored in the cpu. Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-8-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
2022-07-06target/ppc: Implement mffscdrn[i] instructionsVíctor Colombo2-0/+46
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br> Reviewed-by: Matheus Ferst <matheus.ferst@eldorado.org.br> Message-Id: <20220629162904.105060-7-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
generated by cgit v1.1 at 2025-02-12 19:41:40 +0000