aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-05-19vhost-user: send SET_STATUS 0 after GET_VRING_BASEStefan Hajnoczi1-1/+15
Setting the VIRTIO Device Status Field to 0 resets the device. The device's state is lost, including the vring configuration. vhost-user.c currently sends SET_STATUS 0 before GET_VRING_BASE. This risks confusion about the lifetime of the vhost-user state (e.g. vring last_avail_idx) across VIRTIO device reset. Eugenio Pérez <eperezma@redhat.com> adjusted the order for vhost-vdpa.c in commit c3716f260bff ("vdpa: move vhost reset after get vring base") and in that commit description suggested doing the same for vhost-user in the future. Go ahead and adjust vhost-user.c now. I ran various online code searches to identify vhost-user backends implementing SET_STATUS. It seems only DPDK implements SET_STATUS and Yajun Wu <yajunw@nvidia.com> has confirmed that it is safe to make this change. Fixes: commit 923b8921d210763359e96246a58658ac0db6c645 ("vhost-user: Support vhost_dev_start") Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Cindy Lu <lulu@redhat.com> Cc: Yajun Wu <yajunw@nvidia.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20230501230409.274178-1-stefanha@redhat.com> Reviewed-by: Maxime Coquelin <maxime.coquelin@redhat.com> Reviewed-by: Yajun Wu <yajunw@nvidia.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19pci: pci_add_option_rom(): refactor: use g_autofree for path variableVladimir Sementsov-Ogievskiy1-7/+1
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230515125229.44836-3-vsementsov@yandex-team.ru> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com>
2023-05-19pci: pci_add_option_rom(): improve styleVladimir Sementsov-Ogievskiy1-10/+9
Fix over-80 lines and missing curly brackets for if-operators, which are required by QEMU coding style. Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <20230515125229.44836-2-vsementsov@yandex-team.ru> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Juan Quintela <quintela@redhat.com>
2023-05-19ACPI: bios-tables-test.c step 5 (update expected table binaries)Eric DeVolder15-14/+0
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6. An examination of all the files impacted (as listed in bios-tables-test-allowe-diff.h) shows only the MADT/APIC tables bumping revision from 1 to 3, and a corresponding change to the checksum. The below diff is typical: --- /tmp/asl-1F9641.dsl 2023-05-16 15:18:31.292579156 -0400 +++ /tmp/asl-GVD741.dsl 2023-05-16 15:18:31.291579149 -0400 @@ -1,32 +1,32 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20230331 (64-bit version) * Copyright (c) 2000 - 2023 Intel Corporation * - * Disassembly of tests/data/acpi/pc/APIC, Tue May 16 15:18:31 2023 + * Disassembly of /tmp/aml-R4D741, Tue May 16 15:18:31 2023 * * ACPI Data Table [APIC] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in hex) */ [000h 0000 004h] Signature : "APIC" [Multiple APIC Description Table (MADT)] [004h 0004 004h] Table Length : 00000078 -[008h 0008 001h] Revision : 01 -[009h 0009 001h] Checksum : 8A +[008h 0008 001h] Revision : 03 +[009h 0009 001h] Checksum : 88 [00Ah 0010 006h] Oem ID : "BOCHS " [010h 0016 008h] Oem Table ID : "BXPC " [018h 0024 004h] Oem Revision : 00000001 [01Ch 0028 004h] Asl Compiler ID : "BXPC" [020h 0032 004h] Asl Compiler Revision : 00000001 [024h 0036 004h] Local Apic Address : FEE00000 [028h 0040 004h] Flags (decoded below) : 00000001 PC-AT Compatibility : 1 [02Ch 0044 001h] Subtable Type : 00 [Processor Local APIC] [02Dh 0045 001h] Length : 08 [02Eh 0046 001h] Processor ID : 00 [02Fh 0047 001h] Local Apic ID : 00 [030h 0048 004h] Flags (decoded below) : 00000001 Processor Enabled : 1 @@ -81,24 +81,24 @@ [06Bh 0107 001h] Source : 0B [06Ch 0108 004h] Interrupt : 0000000B [070h 0112 002h] Flags (decoded below) : 000D Polarity : 1 Trigger Mode : 3 [072h 0114 001h] Subtable Type : 04 [Local APIC NMI] [073h 0115 001h] Length : 06 [074h 0116 001h] Processor ID : FF [075h 0117 002h] Flags (decoded below) : 0000 Polarity : 0 Trigger Mode : 0 [077h 0119 001h] Interrupt Input LINT : 01 Raw Table Data: Length 120 (0x78) - 0000: 41 50 49 43 78 00 00 00 01 8A 42 4F 43 48 53 20 // APICx.....BOCHS + 0000: 41 50 49 43 78 00 00 00 03 88 42 4F 43 48 53 20 // APICx.....BOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ 0070: 0D 00 04 06 FF 00 00 01 // ........ Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Message-Id: <20230517162545.2191-4-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Ani Sinha <anisinha@redhat.com>
2023-05-19ACPI: i386: bump to MADT to revision 3Eric DeVolder1-1/+1
Currently i386 QEMU generates MADT revision 3, and reports MADT revision 1. Set .revision to 3 to match reality. Link: https://lore.kernel.org/linux-acpi/20230327191026.3454-1-eric.devolder@ora cle.com/T/#t Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <anisinha@redhat.com> Message-Id: <20230517162545.2191-3-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2023-05-19ACPI: bios-tables-test.c step 2 (allowed-diff entries)Eric DeVolder1-0/+14
Following the guidelines in tests/qtest/bios-tables-test.c, set up bios-tables-test-allowed-diff.h to ignore the imminent changes to the APIC tables, per step 2. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Message-Id: <20230517162545.2191-2-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Ani Sinha <ani@anisinha.ca>
2023-05-19hw/cxl: Multi-Region CXL Type-3 Devices (Volatile and Persistent)Gregory Price7-114/+366
This commit enables each CXL Type-3 device to contain one volatile memory region and one persistent region. Two new properties have been added to cxl-type3 device initialization: [volatile-memdev] and [persistent-memdev] The existing [memdev] property has been deprecated and will default the memory region to a persistent memory region (although a user may assign the region to a ram or file backed region). It cannot be used in combination with the new [persistent-memdev] property. Partitioning volatile memory from persistent memory is not yet supported. Volatile memory is mapped at DPA(0x0), while Persistent memory is mapped at DPA(vmem->size), per CXL Spec 8.2.9.8.2.0 - Get Partition Info. Signed-off-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Fan Ni <fan.ni@samsung.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421160827.2227-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19hw/mem: Use memory_region_size() in cxl_type3Jonathan Cameron1-4/+4
Accessors prefered over direct use of int128_get64() as they clamp out of range values. None are expected here but cleaner to always use the accessor than mix and match. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421160827.2227-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Gregory Price <gregory.price@memverge.com>
2023-05-19tests/qtest/cxl-test: whitespace, line ending cleanupGregory Price1-38/+46
Defines are starting to exceed line length limits, align them for cleanliness before making modifications. Signed-off-by: Gregory Price <gregory.price@memverge.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421160827.2227-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19hw/cxl: Fix incorrect reset of commit and associated clearing of committed.Jonathan Cameron2-2/+25
The hardware clearing the commit bit is not spec compliant. Clearing of committed bit when commit is cleared is not specifically stated in the CXL spec, but is the expected (and simplest) permitted behaviour so use that for QEMU emulation. Reviewed-by: Fan Ni <fan.ni@samsung.com> Tested-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> -- v2: Picked up tags. Message-Id: <20230421135906.3515-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19hw/cxl: Fix endian handling for decoder commit.Jonathan Cameron2-7/+10
Not a real problem yet as all supported architectures are little endian, but continue to tidy these up when touching code for other reasons. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421135906.3515-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19hw/cxl: drop pointless memory_region_transaction_guardsJonathan Cameron1-2/+0
Not clear what intent was here, but probably based on a misunderstanding of what these guards are for. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421135906.3515-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19docs/cxl: Replace unsupported AARCH64 with x86_64Raghu H1-3/+3
Currently Qemu CXL emulation support is not availabe on AARCH64 but its available with qemu x86_64 architecture, updating the document to reflect the supported platform. Signed-off-by: Raghu H <raghuhack78@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421134507.26842-4-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19docs/cxl: Remove incorrect CXL type 3 size parameterRaghu H1-4/+4
cxl-type3 memory size is read directly from the provided memory backed end device. Remove non existent size option Signed-off-by: Raghu H <raghuhack78@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421134507.26842-3-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19docs/cxl: fix some typosBrice Goglin1-4/+4
Signed-off-by: Brice Goglin <Brice.Goglin@inria.fr> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421134507.26842-2-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19hw/cxl: cdat: Fix failure to free buffer in erorr pathsJonathan Cameron3-15/+25
The failure paths in CDAT file loading did not clear up properly. Change to using g_auto_free and a local pointer for the buffer to ensure this function has no side effects on error. Also drop some unnecessary checks that can not fail. Cleanup properly after a failure to load a CDAT file. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Message-Id: <20230421132020.7408-3-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19hw/cxl: cdat: Fix open file not closed in ct3_load_cdat()Hao Zeng1-21/+8
Open file descriptor not closed in error paths. Fix by replace open coded handling of read of whole file into a buffer with g_file_get_contents() Fixes: aba578bdac ("hw/cxl: CDAT Data Object Exchange implementation") Signed-off-by: Zeng Hao <zenghao@kylinos.cn> Suggested-by: Philippe Mathieu-Daudé <philmd@linaro.org> Suggested-by: Peter Maydell <peter.maydell@linaro.org> Suggested-by: Jonathan Cameron via <qemu-devel@nongnu.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> -- Changes since v5: - Drop if guard on g_free() as per checkpatch warning. Message-Id: <20230421132020.7408-2-Jonathan.Cameron@huawei.com> Reviewed-by: Fan Ni <fan.ni@samsung.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2023-05-19vhost: fix possible wrap in SVQ descriptor ringHawkins Jiawei2-1/+7
QEMU invokes vhost_svq_add() when adding a guest's element into SVQ. In vhost_svq_add(), it uses vhost_svq_available_slots() to check whether QEMU can add the element into SVQ. If there is enough space, then QEMU combines some out descriptors and some in descriptors into one descriptor chain, and adds it into `svq->vring.desc` by vhost_svq_vring_write_descs(). Yet the problem is that, `svq->shadow_avail_idx - svq->shadow_used_idx` in vhost_svq_available_slots() returns the number of occupied elements, or the number of descriptor chains, instead of the number of occupied descriptors, which may cause wrapping in SVQ descriptor ring. Here is an example. In vhost_handle_guest_kick(), QEMU forwards as many available buffers to device by virtqueue_pop() and vhost_svq_add_element(). virtqueue_pop() returns a guest's element, and then this element is added into SVQ by vhost_svq_add_element(), a wrapper to vhost_svq_add(). If QEMU invokes virtqueue_pop() and vhost_svq_add_element() `svq->vring.num` times, vhost_svq_available_slots() thinks QEMU just ran out of slots and everything should work fine. But in fact, virtqueue_pop() returns `svq->vring.num` elements or descriptor chains, more than `svq->vring.num` descriptors due to guest memory fragmentation, and this causes wrapping in SVQ descriptor ring. This bug is valid even before marking the descriptors used. If the guest memory is fragmented, SVQ must add chains so it can try to add more descriptors than possible. This patch solves it by adding `num_free` field in VhostShadowVirtqueue structure and updating this field in vhost_svq_add() and vhost_svq_get_buf(), to record the number of free descriptors. Fixes: 100890f7ca ("vhost: Shadow virtqueue buffers forwarding") Signed-off-by: Hawkins Jiawei <yin31149@gmail.com> Acked-by: Eugenio Pérez <eperezma@redhat.com> Message-Id: <20230509084817.3973-1-yin31149@gmail.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Tested-by: Lei Yang <leiyang@redhat.com>
2023-05-18accel/tcg: Fix append_mem_cbRichard Henderson1-42/+0
In fcdab382c8b9 we removed a tcg_gen_extu_tl_i64 from gen_empty_mem_cb, and failed to adjust the associated copy, leading to a failed assert. Fixes: fcdab382c8b9 ("accel/tcg: Widen plugin_gen_empty_mem_callback to i64") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20230518145813.2940745-1-richard.henderson@linaro.org>
2023-05-18Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson62-1348/+2162
* kvm: enable dirty ring for arm64 * target/i386: new features * target/i386: AVX fixes * configure: create a python venv unconditionally * meson: bump to 0.63.0 and move tests from configure * meson: Pass -j option to sphinx * drop support for Python 3.6 * fix check-python-tox * fix "make clean" in the source directory # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmRmDYQUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroOXSwf/WKmYPe09yHfxfVSFsSz83QpB3e+f # KJx6FdyMMt26ZQJpcqorobrDV23R8FyxngXPkwoxqobAEtXB/AH0/S/u8RUZ46Qt # IrF8FXr4ZdyLW7CW6nmIejmlul0iRmFD7D98E6dZ3QXfype3Ifra7gG74spZ1B44 # ZNvaomJKUK8Ga8rbChs9KtgrxlOC5q8IfTWF5ZExmZszPC9NRnZmU5Oncnuwek9T # Ic6zDPoAeF3jDtovZhxg1HAB9e/ENZX/V9NjO92yZa8u/TITQ88l4tJctf7uiLxO # 2oGY12ln8i//pbjyUe4iM+bNh5+reAChEI8iv7WxEsj9s2HBUJ68f3tpbQ== # =Zg00 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 04:35:32 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (68 commits) docs/devel: update build system docs configure: remove unnecessary check configure: reorder option parsing code configure: remove unnecessary mkdir configure: do not rerun the tests with -Werror configure: remove compiler sanity check build: move --disable-debug-info to meson build: move compiler version check to meson build: move remaining compiler flag tests to meson build: move warning flag selection to meson build: move stack protector flag selection to meson build: move coroutine backend selection to meson build: move SafeStack tests to meson build: move sanitizer tests to meson meson: prepare move of QEMU_CFLAGS to meson configure, meson: move --enable-modules to Meson configure: remove pkg-config functions build: move glib detection and workarounds to meson meson: drop unnecessary declare_dependency() meson: add more version numbers to the summary ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-18Merge tag 'pull-target-arm-20230518' of ↵Richard Henderson20-904/+959
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Fix vd == vm overlap in sve_ldff1_z * Add support for MTE with KVM guests * Add RAZ/WI handling for DBGDTR[TX|RX] * Start of conversion of A64 decoder to decodetree * Saturate L2CTLR_EL1 core count field rather than overflowing * vexpress: Avoid trivial memory leak of 'flashalias' * sbsa-ref: switch default cpu core to Neoverse-N1 * sbsa-ref: use Bochs graphics card instead of VGA * MAINTAINERS: Add Marcin Juszkiewicz to sbsa-ref reviewer list * docs: Convert u2f.txt to rST # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmRmHvMZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3vqqEACFEcWq3E2gRjwnz8JAEk/0 # jYuYg9jUG6Ev6xY5x31+M4DfK78eXgHYtCxhEcT6FSwpFg/ZXC+bPlZcRlM+8692 # gkp+JJeBA4VRy9e7Uk6GvRWnpGzjnkHTHf4E9PZB8iIvbJY9nFTtMZydn1w0EnMW # HsetnNLIxrtJaETwUa5mDWh0Bt4t6ZIEB2bJSr3O0fy7uiJ8xvpRMYxqfxvI0h+0 # 7xSaG7xb5Dy4LxohMK0CLdj1wy+8uWpYgD6ZneJ2hlqjknvNWa3zdR8bRLNT0aZL # 8ubR1ioFvfi+uA26SNVrdRrGEhqMrTxD0XstFutz0zlOjn0wjo1Ny/ojmGYWuvcU # aG09UvcecMP8hy+ygTXJ+2D04eH1VGmS1GEwRS3p+fdODsgHy0Ctln8IPK8SuG7q # 67BG/F4GNdkbktHGbZlwduxh30furH8pSSlIJOeTq7d20+atqZ94MWaoW1iQ+t4B # 9gDi3MsKoUKVNEhJPorHlDxvtlQppr0ziL0IVPeYUNJONlSza88hkx34ScA5Rl7+ # 5vQYjLkhS1qZQqvd1fNSRNtHeGx2uBeE9eZF/ZCp7bA5rxcRn//LmG7hO7Octuii # zIVaOektXeShALdJ7dMt4MZh0z1RjVVLf0ouC1HHCg9rlzvB+0I5AhXYacGkmCqW # wf9S0hvNqdGmJRQhNRonGg== # =ooCi # -----END PGP SIGNATURE----- # gpg: Signature made Thu 18 May 2023 05:49:55 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20230518' of https://git.linaro.org/people/pmaydell/qemu-arm: (29 commits) docs: Convert u2f.txt to rST hw/arm/vexpress: Avoid trivial memory leak of 'flashalias' target/arm: Saturate L2CTLR_EL1 core count field rather than overflowing target/arm: Convert ERET, ERETAA, ERETAB to decodetree target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetree target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetree target/arm: Convert BR, BLR, RET to decodetree target/arm: Convert conditional branch insns to decodetree target/arm: Convert TBZ, TBNZ to decodetree target/arm: Convert CBZ, CBNZ to decodetree target/arm: Convert unconditional branch immediate to decodetree target/arm: Convert Extract instructions to decodetree target/arm: Convert Bitfield to decodetree target/arm: Convert Move wide (immediate) to decodetree target/arm: Convert Logical (immediate) to decodetree target/arm: Replace bitmask64 with MAKE_64BIT_MASK target/arm: Convert Add/subtract (immediate with tags) to decodetree target/arm: Convert Add/subtract (immediate) to decodetree target/arm: Split gen_add_CC and gen_sub_CC target/arm: Convert PC-rel addressing to decodetree ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-05-18docs/devel: update build system docsPaolo Bonzini1-108/+175
configure is only doing compiler and host setup now, so adjust the relevant documentation. It is also possible to build emulators with ninja directly if one is so inclined, so mention that as well. The Python virtual environment set up is a new major task of configure as well. Mention it in the list of produced files, while leaving it for a future patch to document how it works and how ``mkvenv ensure`` is used. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18configure: remove unnecessary checkPaolo Bonzini1-7/+0
All calls to probe_target_compiler are conditioned on some "have_target" invocation, or inside a loop on target_list. Therefore there is no issue with building unnecessary firmware images and tests. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18configure: reorder option parsing codePaolo Bonzini1-63/+58
Move some variable assignments around for clarity and to remove one of three loops on the command line arguments. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18configure: remove unnecessary mkdirPaolo Bonzini1-1/+0
It is taken care of by the symlink shell function. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18configure: do not rerun the tests with -WerrorPaolo Bonzini1-34/+1
Tests run in configure are pretty trivial at this point, so do not bother with the extra complication of running tests both with and without -Werror. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18configure: remove compiler sanity checkPaolo Bonzini1-14/+0
The comment is not correct anymore, in that the usability test for the compiler and linker are done after probing $cpu, and Meson will redo them anyway. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18build: move --disable-debug-info to mesonPaolo Bonzini3-5/+5
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18build: move compiler version check to mesonPaolo Bonzini2-25/+20
Use the slighly nicer .version_compare() function for GCC; for Clang that is not possible due to the mess that Apple does with version numbers. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18build: move remaining compiler flag tests to mesonPaolo Bonzini2-69/+62
Remove the only remaining uses of QEMU_CFLAGS. Now that no feature tests are done in configure, it is possible to remove CONFIGURE_CFLAGS and CONFIGURE_LDFLAGS as well. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18build: move warning flag selection to mesonPaolo Bonzini3-109/+48
Meson already knows to test with the positive form of the flag, which simplifies the test. Warnings are now tested explicitly for the C++ compiler, instead of hardcoding those that are only available for the C language. At this point all compiler flags in QEMU_CFLAGS are global and only depend on the OS. No feature tests are performed in configure. Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2023-05-18docs: Convert u2f.txt to rSTPeter Maydell4-111/+95
Convert the u2f.txt file to rST, and place it in the right place in our manual layout. The old text didn't fit very well into our manual style, so the new version ends up looking like a rewrite, although some of the original text is preserved: * the 'building' section of the old file is removed, since we generally assume that users have already built QEMU * some rather verbose text has been cut back * document the passthrough device first, on the assumption that's most likely to be of interest to users * cut back on the duplication of text between sections * format example command lines etc with rST As it's a short document it seemed simplest to do this all in one go rather than try to do a minimal syntactic conversion and then clean up the wording and layout. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-id: 20230421163734.1152076-1-peter.maydell@linaro.org
2023-05-18hw/arm/vexpress: Avoid trivial memory leak of 'flashalias'Peter Maydell1-20/+20
In the vexpress board code, we allocate a new MemoryRegion at the top of vexpress_common_init() but only set it up and use it inside the "if (map[VE_NORFLASHALIAS] != -1)" conditional, so we leak it if not. This isn't a very interesting leak as it's a tiny amount of memory once at startup, but it's easy to fix. We could silence Coverity simply by moving the g_new() into the if() block, but this use of g_new(MemoryRegion, 1) is a legacy from when this board model was originally written; we wouldn't do that if we wrote it today. The MemoryRegions are conceptually a part of the board and must not go away until the whole board is done with (at the end of the simulation), so they belong in its state struct. This machine already has a VexpressMachineState struct that extends MachineState, so statically put the MemoryRegions in there instead of dynamically allocating them separately at runtime. Spotted by Coverity (CID 1509083). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20230512170223.3801643-3-peter.maydell@linaro.org
2023-05-18target/arm: Saturate L2CTLR_EL1 core count field rather than overflowingPeter Maydell1-2/+9
The IMPDEF sysreg L2CTLR_EL1 found on the Cortex-A35, A53, A57, A72 and which we (arguably dubiously) also provide in '-cpu max' has a 2 bit field for the number of processors in the cluster. On real hardware this must be sufficient because it can only be configured with up to 4 CPUs in the cluster. However on QEMU if the board code does not explicitly configure the code into clusters with the right CPU count we default to "give the value assuming that all CPUs in the system are in a single cluster", which might be too big to fit in the field. Instead of just overflowing this 2-bit field, saturate to 3 (meaning "4 CPUs", so at least we don't overwrite other fields in the register. It's unlikely that any guest code really cares about the value in this field; at least, if it does it probably also wants the system to be more closely matching real hardware, i.e. not to have more than 4 CPUs. This issue has been present since the L2CTLR was first added in commit 377a44ec8f2fac5b back in 2014. It was only noticed because Coverity complains (CID 1509227) that the shift might overflow 32 bits and inadvertently sign extend into the top half of the 64 bit value. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512170223.3801643-2-peter.maydell@linaro.org
2023-05-18target/arm: Convert ERET, ERETAA, ERETAB to decodetreePeter Maydell2-108/+63
Convert the exception-return insns ERET, ERETA and ERETB to decodetree. These were the last insns left in the legacy decoder function disas_uncond_reg_b(), which allows us to remove it. The old decoder explicitly decoded the DRPS instruction, only in order to call unallocated_encoding() on it, exactly as would have happened if it hadn't decoded it. This is because this insn always UNDEFs unless the CPU is in halting-debug state, which we don't emulate. So we list the pattern in a comment in a64.decode, but don't actively decode it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-21-peter.maydell@linaro.org
2023-05-18target/arm: Convert BRAA, BRAB, BLRAA, BLRAB to decodetreePeter Maydell2-58/+43
Convert the last four BR-with-pointer-auth insns to decodetree. The remaining cases in the outer switch in disas_uncond_b_reg() all return early rather than leaving the case statement, so we can delete the now-unused code at the end of that function. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-20-peter.maydell@linaro.org
2023-05-18target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to decodetreePeter Maydell2-55/+84
Convert the single-register pointer-authentication variants of BR, BLR, RET to decodetree. (BRAA/BLRAA are in a different branch of the legacy decoder and will be dealt with in the next commit.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-19-peter.maydell@linaro.org
2023-05-18target/arm: Convert BR, BLR, RET to decodetreePeter Maydell2-6/+54
Convert the simple (non-pointer-auth) BR, BLR and RET insns to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-18-peter.maydell@linaro.org
2023-05-18target/arm: Convert conditional branch insns to decodetreePeter Maydell2-24/+8
Convert the immediate conditional branch insn B.cond to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-17-peter.maydell@linaro.org
2023-05-18target/arm: Convert TBZ, TBNZ to decodetreePeter Maydell2-20/+11
Convert the test-and-branch-immediate insns TBZ and TBNZ to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-16-peter.maydell@linaro.org
2023-05-18target/arm: Convert CBZ, CBNZ to decodetreePeter Maydell2-20/+11
Convert the compare-and-branch-immediate insns CBZ and CBNZ to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-15-peter.maydell@linaro.org
2023-05-18target/arm: Convert unconditional branch immediate to decodetreePeter Maydell2-19/+19
Convert the unconditional branch immediate insns B and BL to decodetree. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-14-peter.maydell@linaro.org
2023-05-18target/arm: Convert Extract instructions to decodetreePeter Maydell2-63/+34
Convert the EXTR instruction to decodetree (this is the only one in the 'Extract" class). This is the last of the dp-immediate insns in the legacy decoder, so we can now remove disas_data_proc_imm(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20230512144106.3608981-13-peter.maydell@linaro.org
2023-05-18target/arm: Convert Bitfield to decodetreeRichard Henderson2-57/+88
Convert the BFM, SBFM, UBFM instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-12-peter.maydell@linaro.org [PMM: Rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-18target/arm: Convert Move wide (immediate) to decodetreeRichard Henderson2-43/+41
Convert the MON, MOVZ, MOVK instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-11-peter.maydell@linaro.org [PMM: Rebased] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-18target/arm: Convert Logical (immediate) to decodetreeRichard Henderson2-64/+43
Convert the ADD, ORR, EOR, ANDS (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org [PMM: rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-18target/arm: Replace bitmask64 with MAKE_64BIT_MASKRichard Henderson1-9/+2
Use the bitops.h macro rather than rolling our own here. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-9-peter.maydell@linaro.org
2023-05-18target/arm: Convert Add/subtract (immediate with tags) to decodetreeRichard Henderson2-27/+19
Convert the ADDG and SUBG (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-8-peter.maydell@linaro.org [PMM: Rebased; use TRANS_FEAT()] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-18target/arm: Convert Add/subtract (immediate) to decodetreeRichard Henderson3-53/+42
Convert the ADD and SUB (immediate) instructions. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-7-peter.maydell@linaro.org [PMM: Rebased; adjusted to use translate.h's TRANS macro] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2023-05-18target/arm: Split gen_add_CC and gen_sub_CCRichard Henderson1-60/+79
Split out specific 32-bit and 64-bit functions. These carry the same signature as tcg_gen_add_i64, and so will be easier to pass as callbacks. Retain gen_add_CC and gen_sub_CC during conversion. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-6-peter.maydell@linaro.org [PMM: rebased] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-30 23:03:31 +0000