aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-05-25aspeed: Introduce a get_irq AspeedSoCClass methodCédric Le Goater4-7/+19
and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code. Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Peter Delevoryas <pdel@fb.com> Reviewed-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516055620.2380197-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw: m25p80: allow write_enable latch get/setIris Chen5-32/+98
The write_enable latch property is not currently exposed. This commit makes it a modifiable property. Signed-off-by: Iris Chen <irischenlj@fb.com> Acked-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20220513055022.951759-1-irischenlj@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25docs: aspeed: Add fby35 boardPeter Delevoryas1-0/+1
Add fby35 to the list of Aspeed boards. Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20220506193354.990532-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25hw/arm/aspeed: Add fby35 machine typePeter Delevoryas1-0/+63
Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB. Reference images can be found in Facebook OpenBMC Github Release assets as "fby35.mtd". [3] You can boot the reference images as follows (fby35 uses dual-flash): qemu-system-arm -machine fby35-bmc \ -drive file=fby35.mtd,format=raw,if=mtd \ -drive file=fby35.mtd,format=raw,if=mtd \ -nographic [1] https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e36015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts [2] https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a385286d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-dev.sh [3] https://github.com/facebook/openbmc/releases Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220503225925.1798324-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-25docs: add minibmc section in aspeed documentJamin Lin1-0/+61
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220506031521.13254-2-jamin_lin@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2022-05-20Merge tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu into ↵Richard Henderson20-329/+59
staging * Remove Ubuntu 18.04 containers (not supported anymore) * Improve the cleanup of the QEMU binary in case of failing qtests * Update the Windows support statement * Remove the capstone submodule (and rely on Capstone of the distros instead) # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmKEovQRHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbXXtxAAsjL2M/kUcr1KBSfkaMhTa0D3OKPQ+p/e # Bac/9+l7UhZZLLffzg53lSsCmlj9cSr5cVUkooT7IFS03wauH7ZJ/wuefIS8IYED # jREmeMWXmVTTfQo4QQZ+6T+XknG2DWjzXQ3sNat71LH4RbHXO5um3zYIdDUaujP+ # v4sAKKH+F/FUsEXMP1rFmZpkaWOcvsuSwP/H4kEfhlovebAZINPow26eYYRrTM2t # Ifs7HelO12TlmqlBFn0UzHj8bV8MZkqcjj0efocVzuYMQ8DVcxE7IPc3tft2PuUu # Ia+Czh1hLsLA1zYiO/nN9bVIIewFGOErASzjlYWUlQwNRc1nLik+m+p4Cl9WOEhL # JpkN/yY3pTI5uC6a4KgxDQGTeFUR4D5la6Hg7yQjQbTBMEeGFCV50iOdkItdnRBx # ByReVctXS3oIhsDqHMb8qydlBkPp5pUrAXdj43IBCUb3UsrHmCxH+z8U5BhHvv4D # OleykLKyMcuff6HcEpC1fBQNIFJX5uS69EtAXYtyo2kb5zAJWezCv65UPldAZJCT # kRT4beueQ+d5t+4LZn1qNePdoyeFArdCLlOqg/3Fx08kM5eEv22pSQhOtWclE7U3 # tgorikFybClvKJ+YnXBAxD7oFKe+h9L+RYCFOgoTebrbMX54IjjJfeo2DydhHTt7 # IaJnsI+vvAA= # =z6e9 # -----END PGP SIGNATURE----- # gpg: Signature made Wed 18 May 2022 12:40:36 AM PDT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [undefined] # gpg: aka "Thomas Huth <thuth@redhat.com>" [undefined] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-05-18' of https://gitlab.com/thuth/qemu: capstone: Remove the capstone submodule capstone: Allow version 3.0.5 again tests/vm: Add capstone to the NetBSD and OpenBSD VMs docs/about: Update the support statement for Windows tests/qtest: use prctl(PR_SET_PDEATHSIG) as fallback to kill QEMU tests/qtest: fix registration of ABRT handler for QEMU cleanup Remove Ubuntu 18.04 container support from the repository gitlab-ci: Switch the container of the 'check-patch' & 'check-dco' jobs Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-19Merge tag 'pull-target-arm-20220519' of ↵Richard Henderson46-228/+697
https://git.linaro.org/people/pmaydell/qemu-arm into staging target-arm queue: * Implement FEAT_S2FWB * Implement FEAT_IDST * Drop unsupported_encoding() macro * hw/intc/arm_gicv3: Use correct number of priority bits for the CPU * Fix aarch64 debug register names * hw/adc/zynq-xadc: Use qemu_irq typedef * target/arm/helper.c: Delete stray obsolete comment * Make number of counters in PMCR follow the CPU * hw/arm/virt: Fix dtb nits * ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY * target/arm: Fix PAuth keys access checks for disabled SEL2 * Enable FEAT_HCX for -cpu max * Use FIELD definitions for CPACR, CPTR_ELx # -----BEGIN PGP SIGNATURE----- # # iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmKGf/kZHHBldGVyLm1h # eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3h5fD/9+2ymBkwX9jIaaOooejZrJ # CUVCPL2w206eZbPihgE4snZcZdkGjteDhS30kipyJxFNaCE0d2qQLTMrPXQMKyGz # aqCcvSSdb+VraVOP7RpfqYrkzFsj/+K/F5NHn3Vf/T7ULLQJFk0JZ4UWnt7/rkhL # oaXGDm79JrFfMTWUu2AKtCGj132YXyH2YP7GmvYyIty3l+hR9a8mwx3EcFTewuEn # U7AZGZL2GfixGLZU/nNRcTu/BOlkdU6PM1BZoprs7HwbMXR1+pBCX6bwIXK35Q6/ # vCu8e/4+Hi4cd7nxRXqQ7+KuIdcEB+LwupN61othVUl2lnfQgNcvj2hhiWJkxdRI # gpRktnnf6QNWsQ7HWShB5o8HhDN9v82wMf8VSiN1XncN6oYWZSEAMa4NbV/1ditY # yolJww/onnre8A07xTzBqIXqKRViwUMltXSamUpuWx4UsSMOql/ktJYsXqSnJWP+ # cpTqQ+VQKj8cTotvDTnxKsOiI/RraSAzW1amle0x2Ff8I6AN45j1S3GuT9EyJJ3w # CabegyYloJChI2Gnqf5Pc+B108E/GwHlcsmgaN5FEjlGzluKa7Ii0D2f1Cey1tAl # iTqJ3dRFjhkll6a88TN47QRtDJadXp+PjQzzQxtEM1wXhJLWXTxocvBn0cGg2OnY # 4eMY1YLtD9neCnKvdZdw9g== # =F3ow # -----END PGP SIGNATURE----- # gpg: Signature made Thu 19 May 2022 10:35:53 AM PDT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [full] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [full] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [full] * tag 'pull-target-arm-20220519' of https://git.linaro.org/people/pmaydell/qemu-arm: (22 commits) target/arm: Use FIELD definitions for CPACR, CPTR_ELx target/arm: Enable FEAT_HCX for -cpu max target/arm: Fix PAuth keys access checks for disabled SEL2 ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb node hw/arm/virt: Fix incorrect non-secure flash dtb node name target/arm: Make number of counters in PMCR follow the CPU target/arm/helper.c: Delete stray obsolete comment hw/adc/zynq-xadc: Use qemu_irq typedef Fix aarch64 debug register names. hw/intc/arm_gicv3: Provide ich_num_aprs() hw/intc/arm_gicv3: Use correct number of priority bits for the CPU hw/intc/arm_gicv3: Support configurable number of physical priority bits hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parameters target/arm: Drop unsupported_encoding() macro target/arm: Implement FEAT_IDST target/arm: Enable FEAT_S2FWB for -cpu max target/arm: Implement FEAT_S2FWB ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-19target/arm: Use FIELD definitions for CPACR, CPTR_ELxRichard Henderson4-36/+75
We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220517054850.177016-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-19target/arm: Enable FEAT_HCX for -cpu maxRichard Henderson3-0/+71
This feature adds a new register, HCRX_EL2, which controls many of the newer AArch64 features. So far the register is effectively RES0, because none of the new features are done. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220517054850.177016-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-19target/arm: Fix PAuth keys access checks for disabled SEL2Florian Lugou1-1/+1
As per the description of the HCR_EL2.APK field in the ARMv8 ARM, Pointer Authentication keys accesses should only be trapped to Secure EL2 if it is enabled. Signed-off-by: Florian Lugou <florian.lugou@provenrun.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220517145242.1215271-1-florian.lugou@provenrun.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-19ptimer: Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACYPeter Maydell25-36/+44
The traditional ptimer behaviour includes a collection of weird edge case behaviours. In 2016 we improved the ptimer implementation to fix these and generally make the behaviour more flexible, with ptimers opting in to the new behaviour by passing an appropriate set of policy flags to ptimer_init(). For backwards-compatibility, we defined PTIMER_POLICY_DEFAULT (which sets no flags) to give the old weird behaviour. This turns out to be a poor choice of name, because people writing new devices which use ptimers are misled into thinking that the default is probably a sensible choice of flags, when in fact it is almost always not what you want. Rename PTIMER_POLICY_DEFAULT to PTIMER_POLICY_LEGACY and beef up the comment to more clearly say that new devices should not be using it. The code-change part of this commit was produced by sed -i -e 's/PTIMER_POLICY_DEFAULT/PTIMER_POLICY_LEGACY/g' $(git grep -l PTIMER_POLICY_DEFAULT) with the exception of a test name string change in tests/unit/ptimer-test.c which was added manually. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220516103058.162280-1-peter.maydell@linaro.org
2022-05-19hw/arm/virt: Drop #size-cells and #address-cells from gpio-keys dtb nodePeter Maydell1-2/+0
The virt board generates a gpio-keys node in the dtb, but it incorrectly gives this node #size-cells and #address-cells properties. If you dump the dtb with 'machine dumpdtb=file.dtb' and run it through dtc, dtc will warn about this: Warning (avoid_unnecessary_addr_size): /gpio-keys: unnecessary #address-cells/#size-cells without "ranges" or child "reg" property Remove the bogus properties. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220513131316.4081539-3-peter.maydell@linaro.org
2022-05-19hw/arm/virt: Fix incorrect non-secure flash dtb node namePeter Maydell1-1/+1
In the virt board with secure=on we put two nodes in the dtb for flash devices: one for the secure-only flash, and one for the non-secure flash. We get the reg properties for these correct, but in the DT node name, which by convention includes the base address of devices, we used the wrong address. Fix it. Spotted by dtc, which will complain Warning (unique_unit_address): /flash@0: duplicate unit-address (also used in node /secflash@0) if you dump the dtb from QEMU with -machine dumpdtb=file.dtb and then decompile it with dtc. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220513131316.4081539-2-peter.maydell@linaro.org
2022-05-19target/arm: Make number of counters in PMCR follow the CPUPeter Maydell6-12/+47
Currently we give all the v7-and-up CPUs a PMU with 4 counters. This means that we don't provide the 6 counters that are required by the Arm BSA (Base System Architecture) specification if the CPU supports the Virtualization extensions. Instead of having a single PMCR_NUM_COUNTERS, make each CPU type specify the PMCR reset value (obtained from the appropriate TRM), and use the 'N' field of that value to define the number of counters provided. This means that we now supply 6 counters instead of 4 for: Cortex-A9, Cortex-A15, Cortex-A53, Cortex-A57, Cortex-A72, Cortex-A76, Neoverse-N1, '-cpu max' This CPU goes from 4 to 8 counters: A64FX These CPUs remain with 4 counters: Cortex-A7, Cortex-A8 This CPU goes down from 4 to 3 counters: Cortex-R5 Note that because we now use the PMCR reset value of the specific implementation, we no longer set the LC bit out of reset. This has an UNKNOWN value out of reset for all cores with any AArch32 support, so guest software should be setting it anyway if it wants it. This change was originally landed in commit f7fb73b8cdd3f7 (during the 6.0 release cycle) but was then reverted by commit 21c2dd77a6aa517 before that release because it did not work with KVM. This version fixes that by creating the scratch vCPU in kvm_arm_get_host_cpu_features() with the KVM_ARM_VCPU_PMU_V3 feature if KVM supports it, and then only asking KVM for the PMCR_EL0 value if the vCPU has a PMU. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [PMM: Added the correct value for a64fx] Message-id: 20220513122852.4063586-1-peter.maydell@linaro.org
2022-05-19target/arm/helper.c: Delete stray obsolete commentPeter Maydell1-1/+0
In commit 88ce6c6ee85d we switched from directly fishing the number of breakpoints and watchpoints out of the ID register fields to abstracting out functions to do this job, but we forgot to delete the now-obsolete comment in define_debug_regs() about the relation between the ID field value and the actual number of breakpoints and watchpoints. Delete the obsolete comment. Reported-by: CHRIS HOWARD <cvz185@web.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220513131801.4082712-1-peter.maydell@linaro.org
2022-05-19hw/adc/zynq-xadc: Use qemu_irq typedefPhilippe Mathieu-Daudé2-4/+3
Except hw/core/irq.c which implements the forward-declared opaque qemu_irq structure, hw/adc/zynq-xadc.{c,h} are the only files not using the typedef. Fix this single exception. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Message-id: 20220509202035.50335-1-philippe.mathieu.daude@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-19Fix aarch64 debug register names.Chris Howard1-4/+12
Give all the debug registers their correct names including the index, rather than having multiple registers all with the same name string, which is confusing when viewed over the gdbstub interface. Signed-off-by: CHRIS HOWARD <cvz185@web.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 4127D8CA-D54A-47C7-A039-0DB7361E30C0@web.de [PMM: expanded commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-05-19hw/intc/arm_gicv3: Provide ich_num_aprs()Peter Maydell1-6/+10
We previously open-coded the expression for the number of virtual APR registers and the assertion that it was not going to cause us to overflow the cs->ich_apr[] array. Factor this out into a new ich_num_aprs() function, for consistency with the icc_num_aprs() function we just added for the physical APR handling. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-7-peter.maydell@linaro.org Message-id: 20220506162129.2896966-6-peter.maydell@linaro.org
2022-05-19hw/intc/arm_gicv3: Use correct number of priority bits for the CPUPeter Maydell6-5/+27
Make the GICv3 set its number of bits of physical priority from the implementation-specific value provided in the CPU state struct, in the same way we already do for virtual priority bits. Because this would be a migration compatibility break, we provide a property force-8-bit-prio which is enabled for 7.0 and earlier versioned board models to retain the legacy "always use 8 bits" behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-6-peter.maydell@linaro.org Message-id: 20220506162129.2896966-5-peter.maydell@linaro.org
2022-05-19hw/intc/arm_gicv3: Support configurable number of physical priority bitsPeter Maydell2-59/+130
The GICv3 code has always supported a configurable number of virtual priority and preemption bits, but our implementation currently hardcodes the number of physical priority bits at 8. This is not what most hardware implementations provide; for instance the Cortex-A53 provides only 5 bits of physical priority. Make the number of physical priority/preemption bits driven by fields in the GICv3CPUState, the way that we already do for virtual priority/preemption bits. We set cs->pribits to 8, so there is no behavioural change in this commit. A following commit will add the machinery for CPUs to set this to the correct value for their implementation. Note that changing the number of priority bits would be a migration compatibility break, because the semantics of the icc_apr[][] array changes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-5-peter.maydell@linaro.org Message-id: 20220506162129.2896966-4-peter.maydell@linaro.org
2022-05-19hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constantPeter Maydell1-3/+13
The GIC_MIN_BPR constant defines the minimum BPR value that the TCG emulated GICv3 supports. We're currently using this also as the value we reset the KVM GICv3 ICC_BPR registers to, but this is only right by accident. We want to make the emulated GICv3 use a configurable number of priority bits, which means that GIC_MIN_BPR will no longer be a constant. Replace the uses in the KVM reset code with literal 0, plus a constant explaining why this is reasonable. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-4-peter.maydell@linaro.org Message-id: 20220506162129.2896966-3-peter.maydell@linaro.org
2022-05-19hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1Peter Maydell1-1/+1
As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the virtual priority bit setting, not the physical priority bit setting. (For QEMU currently we always implement 8 bits of physical priority, so the PRIbits field was previously 7, since it is defined to be "priority bits - 1".) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-3-peter.maydell@linaro.org Message-id: 20220506162129.2896966-2-peter.maydell@linaro.org
2022-05-19hw/intc/arm_gicv3_cpuif: Handle CPUs that don't specify GICv3 parametersPeter Maydell1-5/+13
We allow a GICv3 to be connected to any CPU, but we don't do anything to handle the case where the CPU type doesn't in hardware have a GICv3 CPU interface and so the various GIC configuration fields (gic_num_lrs, vprebits, vpribits) are not specified. The current behaviour is that we will add the EL1 CPU interface registers, but will not put in the EL2 CPU interface registers, even if the CPU has EL2, which will leave the GIC in a broken state and probably result in the guest crashing as it tries to set it up. This only affects the virt board when using the cortex-a15 or cortex-a7 CPU types (both 32-bit) with -machine gic-version=3 (or 'max') and -machine virtualization=on. Instead of failing to set up the EL2 registers, if the CPU doesn't define the GIC configuration set it to a reasonable default, matching the standard configuration for most Arm CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220512151457.3899052-2-peter.maydell@linaro.org
2022-05-19target/arm: Drop unsupported_encoding() macroPeter Maydell2-13/+4
The unsupported_encoding() macro logs a LOG_UNIMP message and then generates code to raise the usual exception for an unallocated encoding. Back when we were still implementing the A64 decoder this was helpful for flagging up when guest code was using something we hadn't yet implemented. Now we completely cover the A64 instruction set it is barely used. The only remaining uses are for five instructions whose semantics are "UNDEF, unless being run under external halting debug": * HLT (when not being used for semihosting) * DCPSR1, DCPS2, DCPS3 * DRPS QEMU doesn't implement external halting debug, so for us the UNDEF is the architecturally correct behaviour (because it's not possible to execute these instructions with halting debug enabled). The LOG_UNIMP doesn't serve a useful purpose; replace these uses of unsupported_encoding() with unallocated_encoding(), and delete the macro. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220509160443.3561604-1-peter.maydell@linaro.org
2022-05-19target/arm: Implement FEAT_IDSTPeter Maydell6-2/+66
The Armv8.4 feature FEAT_IDST specifies that exceptions generated by read accesses to the feature ID space should report a syndrome code of 0x18 (EC_SYSTEMREGISTERTRAP) rather than 0x00 (EC_UNCATEGORIZED). The feature ID space is defined to be: op0 == 3, op1 == {0,1,3}, CRn == 0, CRm == {0-7}, op2 == {0-7} In our implementation we might return the EC_UNCATEGORIZED syndrome value for a system register access in four cases: * no reginfo struct in the hashtable * cp_access_ok() fails (ie ri->access doesn't permit the access) * ri->accessfn returns CP_ACCESS_TRAP_UNCATEGORIZED at runtime * ri->type includes ARM_CP_RAISES_EXC, and the readfn raises an UNDEF exception at runtime We have very few regdefs that set ARM_CP_RAISES_EXC, and none of them are in the feature ID space. (In the unlikely event that any are added in future they would need to take care of setting the correct syndrome themselves.) This patch deals with the other three cases, and enables FEAT_IDST for AArch64 -cpu max. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220509155457.3560724-1-peter.maydell@linaro.org
2022-05-19target/arm: Enable FEAT_S2FWB for -cpu maxPeter Maydell2-0/+12
Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the inherited CLIDR_EL1 value from the Cortex-A57 has them as 1). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-5-peter.maydell@linaro.org
2022-05-19target/arm: Implement FEAT_S2FWBPeter Maydell2-3/+86
Implement the handling of FEAT_S2FWB; the meat of this is in the new combined_attrs_fwb() function which combines S1 and S2 attributes when HCR_EL2.FWB is set. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-4-peter.maydell@linaro.org
2022-05-19target/arm: Factor out FWB=0 specific part of combine_cacheattrs()Peter Maydell1-38/+50
Factor out the part of combine_cacheattrs() that is specific to handling HCR_EL2.FWB == 0. This is the part where we combine the memory type and cacheability attributes. The "force Outer Shareable for Device or Normal Inner-NC Outer-NC" logic remains in combine_cacheattrs() because it holds regardless (this is the equivalent of the pseudocode EffectiveShareability() function). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-3-peter.maydell@linaro.org
2022-05-19target/arm: Postpone interpretation of stage 2 descriptor attribute bitsPeter Maydell2-7/+42
In the original Arm v8 two-stage translation, both stage 1 and stage 2 specify memory attributes (memory type, cacheability, shareability); these are then combined to produce the overall memory attributes for the whole stage 1+2 access. In QEMU we implement this by having get_phys_addr() fill in an ARMCacheAttrs struct, and we convert both the stage 1 and stage 2 attribute bit formats to the same encoding (an 8-bit attribute value matching the MAIR_EL1 fields, plus a 2-bit shareability value). The new FEAT_S2FWB feature allows the guest to enable a different interpretation of the attribute bits in the stage 2 descriptors. These bits can now be used to control details of how the stage 1 and 2 attributes should be combined (for instance they can say "always use the stage 1 attributes" or "ignore the stage 1 attributes and always be Device memory"). This means we need to pass the raw bit information for stage 2 down to the function which combines the stage 1 and stage 2 information. Add a field to ARMCacheAttrs that indicates whether the attrs field should be interpreted as MAIR format, or as the raw stage 2 attribute bits from the descriptor, and store the appropriate values when filling in cacheattrs. We only need to interpret the attrs field in a few places: * in do_ats_write(), where we know to expect a MAIR value (there is no ATS instruction to do a stage-2-only walk) * in S1_ptw_translate(), where we want to know whether the combined S1 + S2 attributes indicate Device memory that should provoke a fault * in combine_cacheattrs(), which does the S1 + S2 combining Update those places accordingly. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220505183950.2781801-2-peter.maydell@linaro.org
2022-05-18Merge tag 'artist-cursor-fix-final-pull-request' of ↵Richard Henderson3-43/+125
https://github.com/hdeller/qemu-hppa into staging hppa: Artist graphics driver fixes for HP-UX and keyboard fix in firmware boot console This series updates the SeaBIOS-hppa firmware to version 5, in which additional HP fonts were added to the firmware and the firmware boot console was fixed to accept input from the emulated PS/2 keyboard when running in graphical mode (serial console was working before already). To test use the "-boot menu=on" qemu option. The artist graphics card driver got various fixes when running the X11-Windows on HP-UX: - fixes the horizontal and vertical postioning of the X11 cursor with HP-UX - allows X11 to blank the screen (e.g. screensaver) - allows the X11 driver to turn the X11 cursor on/off Signed-off-by: Helge Deller <deller@gmx.de> -- Changes compared to version 2 of this series: - Fixed style issues in the X-cursor positioning patch (noticed by Mark Cave-Ayland) Changes compared to version 1 of this series: - Added some Acked-by's from Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> - SeaBIOS-hppa v5 instead of v4 (PS/2 keyboard now works in boot console) - integrated artist X11 X-cusor positioning fix (which was sent serperately before) -- This series should apply cleanly on git head and can be pulled for testing from: https://github.com/hdeller/qemu-hppa.git artist-cursor-fix-final # -----BEGIN PGP SIGNATURE----- # # iHUEABYKAB0WIQS86RI+GtKfB8BJu973ErUQojoPXwUCYoUcLwAKCRD3ErUQojoP # X/joAQCmuV5MD+BTWf91fRTfzXSfOYSp1XahTaItUldKG2ZBWQD+Lflhsoyg4xLd # 2daeDRN1tH2HWldjnCPyMyZ5Ag97PwY= # =ZrTm # -----END PGP SIGNATURE----- # gpg: Signature made Wed 18 May 2022 09:17:51 AM PDT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * tag 'artist-cursor-fix-final-pull-request' of https://github.com/hdeller/qemu-hppa: artist: Fix X cursor position calculation in X11 artist: Emulate screen blanking artist: Allow to turn cursor on or off artist: Fix vertical X11 cursor position in HP-UX artist: Use human-readable variable names instead of reg_xxx artist: Introduce constant for max cursor size seabios-hppa: Update SeaBIOS-hppa to VERSION 5 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-18capstone: Remove the capstone submoduleThomas Huth8-143/+11
Now that we allow compiling with Capstone v3.0.5 again, all our supported build hosts should provide at least this version of the disassembler library, so we do not need to ship this as a submodule anymore. Message-Id: <20220516145823.148450-4-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18capstone: Allow version 3.0.5 againThomas Huth2-1/+2
According to https://lore.kernel.org/qemu-devel/20200921174118.39352-1-richard.henderson@linaro.org/ there was an issue with Capstone 3.0.4 from Ubuntu 18, which was the reason for bumping our minimum Capstone requirement to version 4.0. And indeed, compiling with that version 3.0.4 from Ubuntu 18.04 still fails (after allowing it with a hack in meson.build). But now that we've dropped support for Ubuntu 18.04, that issue is not relevant anymore. Compiling with Capstone version 3.0.5 (e.g. used in Ubuntu 20.04) seems to work fine, so let's allow that version again. Message-Id: <20220516145823.148450-3-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18tests/vm: Add capstone to the NetBSD and OpenBSD VMsThomas Huth2-2/+4
The Capstone library that is shipped with NetBSD and OpenBSD works fine when compiling QEMU, so let's enable this in our build-test VMs to get a little bit more build-test coverage. Message-Id: <20220516145823.148450-2-thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18docs/about: Update the support statement for WindowsThomas Huth3-6/+12
Our support statement for Windows currently talks about "Vista / Server 2008" - which is related to the API of Windows, and this is not easy to understand for the non-technical users. Additionally, glib sets the _WIN32_WINNT macro to 0x0601 already, which indicates the Windows 7 API, so QEMU effectively depends on the Windows 7 API, too. Thus let's bump the _WIN32_WINNT setting in QEMU to the same level as glib uses and adjust our support statement in the documentation to something similar that we're using for Linux and the *BSD systems (i.e. only the two most recent versions), which should hopefully be easier to understand for the users now. And since we're nowadays also compile-testing QEMU with MSYS2 on Windows itself, I think we could mention this build environment here, too. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/880 Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20220513063958.1181443-1-thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18tests/qtest: use prctl(PR_SET_PDEATHSIG) as fallback to kill QEMUDaniel P. Berrangé1-0/+17
Although we register a ABRT handler to kill off QEMU when g_assert() triggers, we want an extra safety net. The QEMU process might be non-functional and thus not have responded to SIGTERM. The test script might also have crashed with SEGV, in which case the cleanup handlers won't ever run. Using the Linux specific prctl(PR_SET_PDEATHSIG) syscall, we can ensure that QEMU gets sent SIGKILL as soon as the controlling qtest exits, if nothing else has correctly told it to quit. Note, technically the death signal is sent when the *thread* that called fork() exits. IOW, if you are calling qtest_init() in one thread, letting that thread exit, and then expecting to run qtest_quit() in a different thread, things are not going to work out. Fortunately that is not a scenario that exists in qtests, as pairs of qtest_init and qtest_quit are always called from the same thread. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220513154906.206715-3-berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18tests/qtest: fix registration of ABRT handler for QEMU cleanupDaniel P. Berrangé1-2/+2
qtest_init registers a hook to cleanup the running QEMU process should g_assert() fire before qtest_quit is called. When the first hook is registered, it is supposed to triggere registration of the SIGABRT handler. Unfortunately the logic in hook_list_is_empty is inverted, so the SIGABRT handler never gets registered, unless 2 or more QEMU processes are run concurrently. This caused qtest to leak QEMU processes anytime g_assert triggers. Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220513154906.206715-2-berrange@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18Remove Ubuntu 18.04 container support from the repositoryThomas Huth6-170/+4
According to our "Supported build platforms" policy, we now do not support Ubuntu 18.04 anymore. Remove the related container files and entries from our CI. Message-Id: <20220516115912.120951-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-18gitlab-ci: Switch the container of the 'check-patch' & 'check-dco' jobsThomas Huth1-6/+8
The 'check-patch' and 'check-dco' jobs only need Python and git for checking the patches, so it's not really necessary to use a container here that has all the other build dependencies installed. By using a lightweight Alpine container, we can improve the runtime here quite a bit, cutting it down from ca. 1:30 minutes to ca. 45 seconds. Suggested-by: Daniel P. Berrangé <berrange@redhat.com> Message-Id: <20220516082310.33876-1-thuth@redhat.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-05-17Merge tag 'net-pull-request' of https://github.com/jasowang/qemu into stagingRichard Henderson15-6/+1044
# -----BEGIN PGP SIGNATURE----- # Version: GnuPG v1 # # iQEcBAABAgAGBQJig2G8AAoJEO8Ells5jWIR7ocH/j+bduaZwE9HM+a9CbemkdOz # 7iPPEq8eKPvLrcURa8DNmguwGul+NSXv1jonb1m1P/C5Lox/PagdC219irk43WGc # DJBzkAo+wOetmvVeCCQl4ovJbYF4PBftYaxkBfm8KbavnoD1aSUPL70QHVvGmuKi # kxmf9WMQgksw+LirSI4avZSJc1YIsjruEYDagbZmA5r/kTNbm4zobLe8/BV/2mgJ # j5bHbrPeci8feBFhjuBVgZKkbUU7HrJj9kLAzbObdQ8a9VDtaWWfQiwmpeAaItl0 # 5OHSD+tFsGt3MSZn+/LXP9emJeKDnLt+LCxvT0yzGw06iF9N0WFJlSUdd4eYkjI= # =5fRf # -----END PGP SIGNATURE----- # gpg: Signature made Tue 17 May 2022 01:50:04 AM PDT # gpg: using RSA key EF04965B398D6211 # gpg: Good signature from "Jason Wang (Jason Wang on RedHat) <jasowang@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 215D 46F4 8246 689E C77F 3562 EF04 965B 398D 6211 * tag 'net-pull-request' of https://github.com/jasowang/qemu: tulip: Assign default MAC address if not specified net/vmnet: update hmp-commands.hx net/vmnet: update qemu-options.hx net/vmnet: implement bridged mode (vmnet-bridged) net/vmnet: implement host mode (vmnet-host) net/vmnet: implement shared mode (vmnet-shared) net/vmnet: add vmnet backends to qapi/net net/vmnet: add vmnet dependency and customizable option Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-17tulip: Assign default MAC address if not specifiedHelge Deller1-2/+2
The MAC of the tulip card is stored in the EEPROM and at startup tulip_fill_eeprom() is called to initialize the EEPROM with the MAC address given on the command line, e.g.: -device tulip,mac=00:11:22:33:44:55 In case the mac address was not given on the command line, tulip_fill_eeprom() initializes the MAC in EEPROM with 00:00:00:00:00:00 which breaks e.g. a HP-UX guest. Fix this problem by moving qemu_macaddr_default_if_unset() a few lines up, so that a default mac address is assigned before tulip_fill_eeprom() initializes the EEPROM. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: update hmp-commands.hxVladislav Yaroshchuk1-1/+5
Update HMP for supporting vmnet. Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: update qemu-options.hxVladislav Yaroshchuk1-0/+25
Update qemu-options.hx to support vmnet networking backend. Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: implement bridged mode (vmnet-bridged)Vladislav Yaroshchuk1-5/+132
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: implement host mode (vmnet-host)Vladislav Yaroshchuk1-6/+110
Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: implement shared mode (vmnet-shared)Vladislav Yaroshchuk3-5/+491
Interaction with vmnet.framework in different modes differs only on configuration stage, so we can create common `send`, `receive`, etc. procedures and reuse them. Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Phillip Tennen <phillip@axleos.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: add vmnet backends to qapi/netVladislav Yaroshchuk9-2/+277
Create separate netdevs for each vmnet operating mode: - vmnet-host - vmnet-shared - vmnet-bridged Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-17net/vmnet: add vmnet dependency and customizable optionVladislav Yaroshchuk3-1/+18
vmnet.framework dependency is added with 'vmnet' option to enable or disable it. Default value is 'auto'. used vmnet features are available since macOS 11.0, but new backend can be built and work properly with subset of them on 10.15 too. Reviewed-by: Akihiko Odaki <akihiko.odaki@gmail.com> Tested-by: Akihiko Odaki <akihiko.odaki@gmail.com> Signed-off-by: Vladislav Yaroshchuk <Vladislav.Yaroshchuk@jetbrains.com> Signed-off-by: Jason Wang <jasowang@redhat.com>
2022-05-16Merge tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Richard Henderson131-578/+5353
into staging virtio,pc,pci: fixes,cleanups,features most of CXL support fixes, cleanups all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmKCuLIPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpdDUH/12SmWaAo+0+SdIHgWFFxsmg3t/EdcO38fgi # MV+GpYdbp6TlU3jdQhrMZYmFdkVVydBdxk93ujCLbFS0ixTsKj31j0IbZMfdcGgv # SLqnV+E3JdHqnGP39q9a9rdwYWyqhkgHoldxilIFW76ngOSapaZVvnwnOMAMkf77 # 1LieL4/Xq7N9Ho86Zrs3IczQcf0czdJRDaFaSIu8GaHl8ELyuPhlSm6CSqqrEEWR # PA/COQsLDbLOMxbfCi5v88r5aaxmGNZcGbXQbiH9qVHw65nlHyLH9UkNTdJn1du1 # f2GYwwa7eekfw/LCvvVwxO1znJrj02sfFai7aAtQYbXPvjvQiqA= # =xdSk # -----END PGP SIGNATURE----- # gpg: Signature made Mon 16 May 2022 01:48:50 PM PDT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [undefined] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of git://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (86 commits) vhost-user-scsi: avoid unlink(NULL) with fd passing virtio-net: don't handle mq request in userspace handler for vhost-vdpa vhost-vdpa: change name and polarity for vhost_vdpa_one_time_request() vhost-vdpa: backend feature should set only once vhost-net: fix improper cleanup in vhost_net_start vhost-vdpa: fix improper cleanup in net_init_vhost_vdpa virtio-net: align ctrl_vq index for non-mq guest for vhost_vdpa virtio-net: setup vhost_dev and notifiers for cvq only when feature is negotiated hw/i386/amd_iommu: Fix IOMMU event log encoding errors hw/i386: Make pic a property of common x86 base machine type hw/i386: Make pit a property of common x86 base machine type include/hw/pci/pcie_host: Correct PCIE_MMCFG_SIZE_MAX include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK docs/vhost-user: Clarifications for VHOST_USER_ADD/REM_MEM_REG vhost-user: more master/slave things virtio: add vhost support for virtio devices virtio: drop name parameter for virtio_init() virtio/vhost-user: dynamically assign VhostUserHostNotifiers hw/virtio/vhost-user: don't suppress F_CONFIG when supported include/hw: start documenting the vhost API ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-16Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingRichard Henderson25-456/+599
* fix WHPX debugging * misc qga-vss fixes * remove the deprecated CPU model 'Icelake-Client' * support for x86 architectural LBR * remove deprecated properties * replace deprecated -soundhw with -audio # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmJ/hZ4UHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroN2Igf/bFs+yluOikt0eFNmXYnshrGBWPXr # oam0iumPox34vTzZnjpSjF6tJGxHWOgi+wbgIvbwOYHA/ONxx8akW580j+1VhEWa # X29VyUzjZBffgFtmlF4fM74/ELYm7s4c1a1/D9TpVP6Dr0fSWbMujbx4dfeVstvf # sONN+A8sVxaNdV9QKPE6BvqfMlPLoCiigrOetf6iY1KuUtkQDF8xDB0MdzdutqAQ # szAtQ0rrzjxDx9EuGN1SECFM1/riDUbtOOoA9g2C7gGKrx3/iUc6pzrkIcAfWLFK # xXbH7+6Wynia0cbUxnrvRdY4daMIxm4N3wUvN7szXgF9kxYxeQcsdgGsNA== # =n4lu # -----END PGP SIGNATURE----- # gpg: Signature made Sat 14 May 2022 03:34:06 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [undefined] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) configure: remove duplicate help messages configure: remove another dead variable build: remove useless dependency introduce -audio as a replacement for -soundhw soundhw: move help handling to vl.c soundhw: unify initialization for ISA and PCI soundhw soundhw: extract soundhw help to a separate function soundhw: remove ability to create multiple soundcards rng: make opened property read-only crypto: make loaded property read-only target/i386: Support Arch LBR in CPUID enumeration target/i386: introduce helper to access supported CPUID target/i386: Enable Arch LBR migration states in vmstate target/i386: Add MSR access interface for Arch LBR target/i386: Add XSAVES support for Arch LBR target/i386: Enable support for XSAVES based features target/i386: Add kvm_get_one_msr helper target/i386: Add lbr-fmt vPMU option to support guest LBR qdev-properties: Add a new macro with bitmask check for uint64_t property i386/cpu: Remove the deprecated cpu model 'Icelake-Client' ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-05-16vhost-user-scsi: avoid unlink(NULL) with fd passingStefan Hajnoczi1-1/+4
Commit 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend Program conventions for vhost-user-scsi") introduced fd-passing support as part of implementing the vhost-user backend program conventions. When fd passing is used the UNIX domain socket path is NULL and we must not call unlink(2). The unlink(2) call is necessary when the listen socket, lsock, was created successfully since that means the UNIX domain socket is visible in the file system. Fixes: Coverity CID 1488353 Fixes: 747421e949fc1eb3ba66b5fcccdb7ba051918241 ("Implements Backend Program conventions for vhost-user-scsi") Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20220516155701.1789638-1-stefanha@redhat.com> Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.1 at 2024-12-28 01:41:43 +0000