aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-01-10gqa-win: get_pci_info: Add g_autofree for few variablesKostiantyn Kostiuk1-4/+2
Signed-off-by: Kostiantyn Kostiuk <konstantin@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
2022-01-10gqa-win: get_pci_info: Split logic to separate functionsKostiantyn Kostiuk1-74/+87
Signed-off-by: Kostiantyn Kostiuk <konstantin@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
2022-01-10gqa-win: get_pci_info: Free parent_dev_info properlyKostiantyn Kostiuk1-2/+5
In case when the function fails to get parent device data, the parent_dev_info variable will be initialized, but not freed. Signed-off-by: Kostiantyn Kostiuk <konstantin@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
2022-01-10gqa-win: get_pci_info: Use common 'end' labelKostiantyn Kostiuk1-13/+12
To prevent memory leaks, always try to free initialized variables. Signed-off-by: Kostiantyn Kostiuk <konstantin@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
2022-01-10gqa-win: get_pci_info: Clean dev_info if handle is validKostiantyn Kostiuk1-2/+4
Signed-off-by: Kostiantyn Kostiuk <konstantin@daynix.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com>
2022-01-10MAINTAINERS: Add entry for QEMU Guest Agent Windows componentsKostiantyn Kostiuk1-0/+8
Signed-off-by: Kostiantyn Kostiuk <kkostiuk@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael Roth <michael.roth@amd.com>
2022-01-08Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into stagingRichard Henderson24-350/+1214
bsd-user: arm (32-bit) support This series of patches brings in 32-bit arm support for bsd-user. It implements all the bits needed to do image activation, signal handling, stack management and threading. This allows us to get to the "Hello World" level. The arm and x86 code are now the same as in the bsd-user fork. For full context, the fork is at https://github.com/qemu-bsd-user/qemu-bsd-user/tree/blitz (though the the recent sig{bus,segv} needed updates are incomplete). v5 changes: o Moved to using the CPUArchState typedef and move set_sigtramp_args, get_mcontext, set_mcontext, and get_ucontext_sigreturn prototypes to bsd-user/freebsd/target_os_ucontext.h o Fix issues with arm's set_mcontext related to masking and remove an unnecessary check. We're down to only one hunk needing review: bsd-user/arm/target_arch_signal.c: arm set_mcontext Warnings that should be ignored: o make checkpatch has a couple of complaints about the comments for the signal trampoline, since it's a false positive IMHO. WARNING: Block comments use a leading /* on a separate line + /* 8 */ sys_sigreturn, WARNING: Block comments use a leading /* on a separate line + /* 9 */ sys_exit # gpg: Signature made Fri 07 Jan 2022 11:36:37 PM PST # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu: (37 commits) bsd-user: add arm target build bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZE bsd-user/arm/signal.c: arm get_ucontext_sigreturn bsd-user/arm/signal.c: arm set_mcontext bsd-user/arm/signal.c: arm get_mcontext bsd-user/arm/signal.c: arm set_sigtramp_args bsd-user/arm/target_arch_signal.h: Define size of *context_t bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signals bsd-user/arm/target_arch_signal.h: arm specific signal registers and stack bsd-user/arm/target_arch_elf.h: arm get_hwcap2 impl bsd-user/arm/target_arch_elf.h: arm get hwcap bsd-user/arm/target_arch_elf.h: arm defines for ELF bsd-user/arm/target_arch_thread.h: Routines to create and switch to a thread bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for arm bsd-user/arm/target_arch_vmparam.h: Parameters for arm address space bsd-user/arm/target_arch_reg.h: Implement core dump register copying bsd-user/arm/target_arch_cpu.h: Implement system call dispatch bsd-user/arm/target_arch_cpu.h: Implement data abort exceptions bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptions bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementation ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into ↵Richard Henderson81-749/+2317
staging Second RISC-V PR for QEMU 7.0 - Fix illegal instruction when PMP is disabled - SiFive PDMA 64-bit support - SiFive PLIC cleanups - Mark Hypervisor extension as non experimental - Enable Hypervisor extension by default - Support 32 cores on the virt machine - Corrections for the Vector extension - Experimental support for 128-bit CPUs - stval and mtval support for illegal instructions # gpg: Signature made Fri 07 Jan 2022 09:50:11 PM PST # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu: (37 commits) target/riscv: Implement the stval/mtval illegal instruction target/riscv: Fixup setting GVA target/riscv: Set the opcode in DisasContext target/riscv: actual functions to realize crs 128-bit insns target/riscv: modification of the trans_csrxx for 128-bit support target/riscv: helper functions to wrap calls to 128-bit csr insns target/riscv: adding high part of some csrs target/riscv: support for 128-bit M extension target/riscv: support for 128-bit arithmetic instructions target/riscv: support for 128-bit shift instructions target/riscv: support for 128-bit U-type instructions target/riscv: support for 128-bit bitwise instructions target/riscv: accessors to registers upper part and 128-bit load/store target/riscv: moving some insns close to similar insns target/riscv: setup everything for rv64 to support rv128 execution target/riscv: array for the 64 upper bits of 128-bit registers target/riscv: separation of bitwise logic and arithmetic helpers target/riscv: additional macros to check instruction support qemu/int128: addition of div/rem 128-bit operations exec/memop: Adding signed quad and octo defines ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user: add arm target buildWarner Losh1-0/+2
CC: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZEWarner Losh1-2/+0
Now that all architecutres define TARGET_[MU]CONTEXT_SIZE, enforce requiring them and always check the sizeof target_{u,m}context_t sizes. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm get_ucontext_sigreturnWarner Losh1-0/+9
Update ucontext to implement sigreturn. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm set_mcontextWarner Losh1-0/+76
Move the machine context to the CPU state. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm get_mcontextWarner Losh1-0/+51
Get the machine context from the CPU state. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/signal.c: arm set_sigtramp_argsWarner Losh1-0/+60
Implement set_sigtramp_args to setup the arguments to the sigtramp calls. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_signal.h: Define size of *context_tWarner Losh1-0/+3
Define the native sizes of mcontext_t and ucontext_t so that the tests in target_os_ucontext.h ensure the size of arm's version of these structures is correct. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signalsWarner Losh1-0/+28
Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_signal.h: arm specific signal registers and stackWarner Losh1-0/+57
Defines for registers and stack layout related to signals. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_elf.h: arm get_hwcap2 implWarner Losh1-0/+22
Implement the extended HW capabilities for HWCAP2. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_elf.h: arm get hwcapWarner Losh1-1/+71
Implement get_elf_hwcap to get the first word of hardware capabilities. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_elf.h: arm defines for ELFWarner Losh1-0/+36
Basic set of defines needed for arm ELF file activation. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_thread.h: Routines to create and switch to a threadWarner Losh1-0/+82
Implement target_thread_init (to create a thread) and target_set_upcall (to switch to a thread) for arm. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org>
2022-01-07bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for armWarner Losh1-0/+49
Copy of the signal trampoline code for arm, as well as setup_sigtramp to write it to the stack. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_vmparam.h: Parameters for arm address spaceWarner Losh1-0/+48
Various parameters describing the layout of the ARM address space. In addition, define routines to get the stack pointer and to set the second return value. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_reg.h: Implement core dump register copyingWarner Losh1-0/+60
Implement the register copying routines to extract registers from the cpu for core dump generation. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement system call dispatchWarner Losh1-0/+94
Implement the system call dispatch. This implements all three kinds of system call: direct and the two indirect variants. It handles all the special cases for thumb as well. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement data abort exceptionsWarner Losh1-0/+11
Implement EXCP_PREFETCH_ABORT AND EXCP_DATA_ABORT. Both of these data exceptions cause a SIGSEGV. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Olivier Houchard <cognet@ci0.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptionsWarner Losh1-0/+33
Implement EXCP_UDEF, EXCP_DEBUG, EXCP_INTERRUPT, EXCP_ATOMIC and EXCP_YIELD. The first two generate a signal to the emulated binary. EXCP_ATOMIC handles atomic operations. The remainder are fancy nops. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Mikaël Urankar <mikael.urankar@gmail.com> Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementationWarner Losh1-0/+22
Add a boiler plate CPU loop that does nothing except return an error for all traps. Signed-off-by: Sean Bruno <sbruno@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regsWarner Losh1-0/+8
Implement target_cpu_clone_regs to clone the resister state on a fork. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.h: CPU Loop definitionsWarner Losh1-0/+43
target_arch_cpu.h is for CPU loop definitions. Create the file and define target_cpu_init and target_cpu_reset for arm. Signed-off-by: Olivier Houchard <cognet@ci0.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_cpu.c: Target specific TLS routinesWarner Losh2-0/+67
Target specific TLS routines to get and set the TLS values. Signed-off-by: Kyle Evans <kevans@FreeBSD.org> Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_syscall.h: Add copyright and update nameWarner Losh1-4/+23
The preferred name for the 32-bit arm is now armv7. Update the name to reflect that. In addition, add Stacey's copyright to this file and update the include guards to the new convention. Signed-off-by: Stacey Son <sson@FreeBSD.org> Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/arm/target_arch_sysarch.h: Use consistent include guardsWarner Losh1-3/+3
As part of upstreaming, the include guards have been made more consistent. Update this file to use the new guards. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Kyle Evans <kevans@FreeBSD.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/target_os_signal.h: Move signal prototypes to target_os_ucontext.hWarner Losh3-18/+11
Switch to the CPUArchState typedef and move target-provided prototypes to target_os_ucontext.h. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/x86_64: Move functions into signal.cWarner Losh2-36/+63
Move the current inline functions into sigal.c. This will increate the flexibility of implementation in the future. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/x86_64/target_arch_signal.h: Fill in mcontext_tWarner Losh1-0/+54
Fill in target_mcontext match the FreeBSD mcontext_t structure. Also define the size correctly. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.hWarner Losh1-8/+1
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontextWarner Losh1-4/+0
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext. Remove vestigial target_sigcontext. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/i386: Move the inlines into signal.cWarner Losh2-36/+63
Move the (now stubbed out) inlines into bsd-user/i386/signal.c. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/i386/target_arch_signal.h: Update mcontext_t to match FreeBSDWarner Losh1-0/+46
Fill in target_mcontext_t to match the FreeBSD mcontex_t. Also tag the current size of mcontext and ucontext to enable size checking for i386. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.hWarner Losh1-8/+1
Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/i386/target_arch_signal.h: Remove target_sigcontextWarner Losh1-4/+0
In FreeBSD, sigcontext was retired in favor of ucontext/mcontext. Remove vestigial target_sigcontext. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user: create a per-arch signal.c fileWarner Losh3-1/+3
Create a place-holder signal.c file for each of the architectures that are currently built. In the future, some code that's currently inlined in target_arch_signal.h will live here. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/freebsd: Create common target_os_ucontext.h fileWarner Losh2-3/+35
FreeBSD has a MI ucontext structure that contains the MD mcontext machine state and other things that are machine independent. Create an include file for all the ucontext stuff. It needs to be included in the arch specific files after target_mcontext is defined. This is largely copied from sys/_ucontext.h with the comments about layout removed because we don't support ancient FreeBSD binaries. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-07bsd-user/mips*: Remove mips supportWarner Losh4-243/+0
FreeBSD is dropping support for mips starting with FreeBSD 14. mips support has been removed from the bsd-user fork because updating it for new signal requirements will take too much time. Remove it here since it is a distraction. Signed-off-by: Warner Losh <imp@bsdimp.com> Acked-by: Richard Henderson <richard.henderson@linaro.org>
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis3-0/+8
The stval and mtval registers can optionally contain the faulting instruction on an illegal instruction exception. This patch adds support for setting the stval and mtval registers. The RISC-V spec states that "The stval register can optionally also be used to return the faulting instruction bits on an illegal instruction exception...". In this case we are always writing the value on an illegal instruction. This doesn't match all CPUs (some CPUs won't write the data), but in QEMU let's just populate the value on illegal instructions. This won't break any guest software, but will provide more information to guests. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211220064916.107241-4-alistair.francis@opensource.wdc.com
2022-01-08target/riscv: Fixup setting GVAAlistair Francis1-15/+6
In preparation for adding support for the illegal instruction address let's fixup the Hypervisor extension setting GVA logic and improve the variable names. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211220064916.107241-3-alistair.francis@opensource.wdc.com
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis1-0/+2
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 20211220064916.107241-2-alistair.francis@opensource.wdc.com
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot3-30/+175
The csrs are accessed through function pointers: we add 128-bit read operations in the table for three csrs (writes fallback to the 64-bit version as the upper 64-bit information is handled elsewhere): - misa, as mxl is needed for proper operation, - mstatus and sstatus, to return sd In addition, we also add read and write accesses to the machine and supervisor scratch registers. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-19-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-01-08target/riscv: modification of the trans_csrxx for 128-bit supportFrédéric Pétrot1-43/+158
As opposed to the gen_arith and gen_shift generation helpers, the csr insns do not have a common prototype, so the choice to generate 32/64 or 128-bit helper calls is done in the trans_csrxx functions. Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220106210108.138226-18-frederic.petrot@univ-grenoble-alpes.fr Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2024-12-26 05:18:30 +0000