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2017-02-28armv7m: QOMify the armv7m containerPeter Maydell2-12/+178
Create a proper QOM object for the armv7m container, which holds the CPU, the NVIC and the bitband regions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-4-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Move NVICState struct definition into headerPeter Maydell2-48/+67
Move the NVICState struct definition into a header, so we can embed it into other QOM objects like SoCs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-3-git-send-email-peter.maydell@linaro.org
2017-02-28armv7m: Abstract out the "load kernel" codePeter Maydell2-5/+30
Abstract the "load kernel" code out of armv7m_init() into its own function. This includes the registration of the CPU reset function, to parallel how we handle this for A profile cores. We make the function public so that boards which choose to directly instantiate an ARMv7M device object can call it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1487604965-23220-2-git-send-email-peter.maydell@linaro.org
2017-02-28Merge remote-tracking branch ↵Peter Maydell26-331/+1897
'remotes/pmaydell/tags/pull-target-arm-20170228' into staging target-arm queue: * raspi2: implement RNG module * raspi2: implement new SD card controller (but don't wire it up) * sdhci: bugfixes for block transfers * virt: fix cpu object reference leak * Add missing fp_access_check() to aarch64 crypto instructions * cputlb: Don't assume do_unassigned_access() never returns * virt: Add a user option to disallow ITS instantiation * i.MX timers: fix reset handling * ARMv7M NVIC: rewrite to fix broken priority handling and masking * exynos: Fix proper mapping of CPUs by providing real cluster ID * exynos: Fix Linux kernel division by zero for PLLs # gpg: Signature made Tue 28 Feb 2017 12:40:51 GMT # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20170228: (27 commits) hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster ID hw/arm/exynos: Fix Linux kernel division by zero for PLLs bcm2835_sdhost: add bcm2835 sdhost controller armv7m: Allow SHCSR writes to change pending and active bits armv7m: Raise correct kind of UsageFault for attempts to execute ARM code armv7m: Check exception return consistency armv7m: Extract "exception taken" code into functions armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLE armv7m: Simpler and faster exception start armv7m: Remove unused armv7m_nvic_acknowledge_irq() return value armv7m: Escalate exceptions to HardFault if necessary arm: gic: Remove references to NVIC armv7m: Fix condition check for taking exceptions armv7m: Rewrite NVIC to not use any GIC code armv7m: Implement reading and writing of PRIGROUP armv7m: Rename nvic_state to NVICState ARM i.MX timers: fix reset handling hw/arm/virt: Add a user option to disallow ITS instantiation cputlb: Don't assume do_unassigned_access() never returns Add missing fp_access_check() to aarch64 crypto instructions ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into stagingPeter Maydell2-10/+10
# gpg: Signature made Tue 28 Feb 2017 04:34:34 GMT # gpg: using RSA key 0xBDBE7B27C0DE3057 # gpg: Good signature from "Jeffrey Cody <jcody@redhat.com>" # gpg: aka "Jeffrey Cody <jeff@codyprime.org>" # gpg: aka "Jeffrey Cody <codyprime@gmail.com>" # Primary key fingerprint: 9957 4B4D 3474 90E7 9D98 D624 BDBE 7B27 C0DE 3057 * remotes/cody/tags/block-pull-request: iscsi: add missing colons to the qapi docs block/mirror: fix broken sparseness detection Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20170228' into stagingPeter Maydell2-0/+4
Enable MTTCG for Alpha guest # gpg: Signature made Tue 28 Feb 2017 00:43:17 GMT # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-axp-20170228: target/alpha: Enable MTTCG by default Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/arm/exynos: Fix proper mapping of CPUs by providing real cluster IDKrzysztof Kozlowski1-0/+12
The Exynos4210 has cluster ID 0x9 in its MPIDR register (raw value 0x8000090x). If this cluster ID is not provided, then Linux kernel cannot map DeviceTree nodes to MPIDR values resulting in kernel warning and lack of any secondary CPUs: DT missing boot CPU MPIDR[23:0], fall back to default cpu_logical_map ... smp: Bringing up secondary CPUs ... smp: Brought up 1 node, 1 CPU SMP: Total of 1 processors activated (24.00 BogoMIPS). Provide a cluster ID so Linux will see proper MPIDR and will try to bring the secondary CPU online. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Message-id: 20170226200142.31169-2-krzk@kernel.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/arm/exynos: Fix Linux kernel division by zero for PLLsKrzysztof Kozlowski3-1/+171
Without any clock controller, the Linux kernel was hitting division by zero during boot or with clk_summary: [ 0.000000] [<c031054c>] (unwind_backtrace) from [<c030ba6c>] (show_stack+0x10/0x14) [ 0.000000] [<c030ba6c>] (show_stack) from [<c05b2660>] (dump_stack+0x88/0x9c) [ 0.000000] [<c05b2660>] (dump_stack) from [<c05b11a4>] (Ldiv0+0x8/0x10) [ 0.000000] [<c05b11a4>] (Ldiv0) from [<c06ad1e0>] (samsung_pll45xx_recalc_rate+0x58/0x74) [ 0.000000] [<c06ad1e0>] (samsung_pll45xx_recalc_rate) from [<c0692ec0>] (clk_register+0x39c/0x63c) [ 0.000000] [<c0692ec0>] (clk_register) from [<c125d360>] (samsung_clk_register_pll+0x2e0/0x3d4) [ 0.000000] [<c125d360>] (samsung_clk_register_pll) from [<c125d7e8>] (exynos4_clk_init+0x1b0/0x5e4) [ 0.000000] [<c125d7e8>] (exynos4_clk_init) from [<c12335f4>] (of_clk_init+0x17c/0x210) [ 0.000000] [<c12335f4>] (of_clk_init) from [<c1204700>] (time_init+0x24/0x2c) [ 0.000000] [<c1204700>] (time_init) from [<c1200b2c>] (start_kernel+0x24c/0x38c) [ 0.000000] [<c1200b2c>] (start_kernel) from [<4020807c>] (0x4020807c) Provide stub for clock controller returning reset values for PLLs. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Message-id: 20170226200142.31169-1-krzk@kernel.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28bcm2835_sdhost: add bcm2835 sdhost controllerClement Deschamps3-0/+478
This adds the BCM2835 SDHost controller from Arasan. Signed-off-by: Clement Deschamps <clement.deschamps@antfield.fr> Message-id: 20170224164021.9066-2-clement.deschamps@antfield.fr Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28armv7m: Allow SHCSR writes to change pending and active bitsPeter Maydell1-2/+11
Implement the NVIC SHCSR write behaviour which allows pending and active status of some exceptions to be changed. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Raise correct kind of UsageFault for attempts to execute ARM codePeter Maydell4-2/+12
M profile doesn't implement ARM, and the architecturally required behaviour for attempts to execute with the Thumb bit clear is to generate a UsageFault with the CFSR INVSTATE bit set. We were incorrectly implementing this as generating an UNDEFINSTR UsageFault; fix this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Check exception return consistencyPeter Maydell3-13/+123
Implement the exception return consistency checks described in the v7M pseudocode ExceptionReturn(). Inspired by a patch from Michael Davidsaver's series, but this is a reimplementation from scratch based on the ARM ARM pseudocode. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Extract "exception taken" code into functionsPeter Maydell1-50/+68
Extract the code from the tail end of arm_v7m_do_interrupt() which enters the exception handler into a pair of utility functions v7m_exception_taken() and v7m_push_stack(), which correspond roughly to the pseudocode PushStack() and ExceptionTaken(). This also requires us to move the arm_v7m_load_vector() utility routine up so we can call it. Handling illegal exception returns has some cases where we want to take a UsageFault either on an existing stack frame or with a new stack frame but with a specific LR value, so we want to be able to call these without having to go via arm_v7m_cpu_do_interrupt(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: VECTCLRACTIVE and VECTRESET are UNPREDICTABLEMichael Davidsaver1-2/+6
The VECTCLRACTIVE and VECTRESET bits in the AIRCR are both documented as UNPREDICTABLE if you write a 1 to them when the processor is not halted in Debug state (ie stopped and under the control of an external JTAG debugger). Since we don't implement Debug state or emulated JTAG these bits are always UNPREDICTABLE for us. Instead of logging them as unimplemented we can simply log writes as guest errors and ignore them. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: change extracted from another patch; commit message constructed from scratch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Simpler and faster exception startMichael Davidsaver1-6/+9
All the places in armv7m_cpu_do_interrupt() which pend an exception in the NVIC are doing so for synchronous exceptions. We know that we will always take some exception in this case, so we can just acknowledge it immediately, rather than returning and then immediately being called again because the NVIC has raised its outbound IRQ line. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: tweaked commit message; added DEBUG to the set of exceptions we handle immediately, since it is synchronous when it results from the BKPT instruction] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Remove unused armv7m_nvic_acknowledge_irq() return valuePeter Maydell3-5/+3
Having armv7m_nvic_acknowledge_irq() return the new value of env->v7m.exception and its one caller assign the return value back to env->v7m.exception is pointless. Just make the return type void instead. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Escalate exceptions to HardFault if necessaryMichael Davidsaver2-2/+53
The v7M exception architecture requires that if a synchronous exception cannot be taken immediately (because it is disabled or at too low a priority) then it should be escalated to HardFault (and the HardFault exception is then taken). Implement this escalation logic. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: extracted from another patch] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28arm: gic: Remove references to NVICMichael Davidsaver3-46/+15
Now that the NVIC is its own separate implementation, we can clean up the GIC code by removing REV_NVIC and conditionals which use it. Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Fix condition check for taking exceptionsPeter Maydell3-8/+23
The M profile condition for when we can take a pending exception or interrupt is not the same as that for A/R profile. The code originally copied from the A/R profile version of the cpu_exec_interrupt function only worked by chance for the very simple case of exceptions being masked by PRIMASK. Replace it with a call to a function in the NVIC code that correctly compares the priority of the pending exception against the current execution priority of the CPU. [Michael Davidsaver's patchset had a patch to do something similar but the implementation ended up being a rewrite.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Rewrite NVIC to not use any GIC codeMichael Davidsaver2-144/+609
Despite some superficial similarities of register layout, the M-profile NVIC is really very different from the A-profile GIC. Our current attempt to reuse the GIC code means that we have significant bugs in our NVIC. Implement the NVIC as an entirely separate device, to give us somewhere we can get the behaviour correct. This initial commit does not attempt to implement exception priority escalation, since the GIC-based code didn't either. It does fix a few bugs in passing: * ICSR.RETTOBASE polarity was wrong and didn't account for internal exceptions * ICSR.VECTPENDING was 16 too high if the pending exception was for an external interrupt * UsageFault, BusFault and MemFault were not disabled on reset as they are supposed to be Signed-off-by: Michael Davidsaver <mdavidsaver@gmail.com> [PMM: reworked, various bugs and stylistic cleanups] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Implement reading and writing of PRIGROUPPeter Maydell1-6/+8
Add a state field for the v7M PRIGROUP register and implent reading and writing it. The current NVIC doesn't honour the values written, but the new version will. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28armv7m: Rename nvic_state to NVICStatePeter Maydell1-22/+22
Rename the nvic_state struct to NVICState, to match our naming conventions. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2017-02-28ARM i.MX timers: fix reset handlingKurban Mallachiev1-8/+25
The i.MX timer device can be reset by writing to the SWR bit of the CR register. This has to behave differently from hard (power-on) reset because it does not reset all of the bits in the CR register. We were incorrectly implementing soft reset and hard reset the same way, and in addition had a logic error which meant that we were clearing the bits that soft-reset is supposed to preserve and not touching the bits that soft-reset clears. This was not correct behaviour for either kind of reset. Separate out the soft reset and hard reset code paths, and correct the handling of reset of the CR register so that it is correct in both cases. Signed-off-by: Kurban Mallachiev <mallachiev@ispras.ru> [PMM: rephrased commit message, spacing on operators; use bool rather than int for is_soft_reset] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/arm/virt: Add a user option to disallow ITS instantiationEric Auger2-2/+30
In 2.9 ITS will block save/restore and migration use cases. As such, let's introduce a user option that allows to turn its instantiation off, along with GICv3. With the "its" option turned false, migration will be possible, obviously at the expense of MSI support (with GICv3). Signed-off-by: Eric Auger <eric.auger@redhat.com> Message-id: 1487681108-14452-1-git-send-email-eric.auger@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28cputlb: Don't assume do_unassigned_access() never returnsPeter Maydell1-8/+7
In get_page_addr_code(), if the guest PC doesn't correspond to RAM then we currently run the CPU's do_unassigned_access() hook if it has one, and otherwise we give up and exit QEMU with a more-or-less useful message. This code assumes that the do_unassigned_access hook will never return, because if it does then we'll plough on attempting to use a non-RAM TLB entry to get a RAM address and will abort() in qemu_ram_addr_from_host_nofail(). Unfortunately some CPU implementations of this hook do return: Microblaze, SPARC and the ARM v7M. Change the code to call report_bad_exec() if the hook returns, as well as if it didn't have one. This means we can tidy it up to use the cpu_unassigned_access() function which wraps the "get the CPU class and call the hook if it has one" work, since we aren't trying to distinguish "no hook" from "hook existed and returned" any more. This brings the handling of this hook into line with the handling used for data accesses, where "hook returned" is treated the same as "no hook existed" and gets you the default behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
2017-02-28Add missing fp_access_check() to aarch64 crypto instructionsNick Reilly1-0/+12
The aarch64 crypto instructions for AES and SHA are missing the check for if the FPU is enabled. Signed-off-by: Nick Reilly <nreilly@blackberry.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28hw/arm/virt: fix cpu object reference leakIgor Mammedov1-0/+1
object_new(FOO) returns an object with ref_cnt == 1 and following object_property_set_bool(cpuobj, true, "realized", NULL) set parent of cpuobj to '/machine/unattached' which makes ref_cnt == 2. Since machvirt_init() doesn't take ownership of cpuobj returned by object_new() it should explicitly drop reference to cpuobj when dangling pointer is about to go out of scope like it's done pc_new_cpu() to avoid object leak. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1487253461-269218-1-git-send-email-imammedo@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28sd: sdhci: Remove block count enable check in single block transfersPrasad J Pandit1-5/+1
In SDHCI protocol, the 'Block count enable' bit of the Transfer Mode register is relevant only in multi block transfers. We need not check it in single block transfers. Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20170214185225.7994-5-ppandit@redhat.com Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28sd: sdhci: conditionally invoke multi block transferPrasad J Pandit1-1/+5
In sdhci_write invoke multi block transfer if it is enabled in the transfer mode register 's->trnmod'. Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20170214185225.7994-4-ppandit@redhat.com Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28sd: sdhci: check transfer mode register in multi block transferPrasad J Pandit1-5/+5
In the SDHCI protocol, the transfer mode register value is used during multi block transfer to check if block count register is enabled and should be updated. Transfer mode register could be set such that, block count register would not be updated, thus leading to an infinite loop. Add check to avoid it. Reported-by: Wjjzhang <wjjzhang@tencent.com> Reported-by: Jiang Xin <jiangxin1@huawei.com> Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Message-id: 20170214185225.7994-3-ppandit@redhat.com Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28sd: sdhci: mask transfer mode register valuePrasad J Pandit1-1/+2
In SDHCI protocol, the transfer mode register is defined to be of 6 bits. Mask its value with '0x0037' so that an invalid value could not be assigned. Signed-off-by: Prasad J Pandit <pjp@fedoraproject.org> Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Message-id: 20170214185225.7994-2-ppandit@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28bcm2835_rng: Use qcrypto_random_bytes() rather than rand()Peter Maydell1-1/+26
Switch to using qcrypto_random_bytes() rather than rand() as our source of randomness for the BCM2835 RNG. If qcrypto_random_bytes() fails, we don't want to return the guest a non-random value in case they're really using it for cryptographic purposes, so the best we can do is a fatal error. This shouldn't happen unless something's broken, though. In theory we could implement this device's full FIFO and interrupt semantics and then just stop filling the FIFO. That's a lot of work, though, and doesn't really give a very nice diagnostic to the user since the guest will just seem to hang. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Daniel P. Berrange <berrange@redhat.com>
2017-02-28target-arm: Implement BCM2835 hardware RNGMarcin Chojnacki5-0/+169
Recent vanilla Raspberry Pi kernels started to make use of the hardware random number generator in BCM2835 SoC. As a result, those kernels wouldn't work anymore under QEMU but rather just freeze during the boot process. This patch implements a trivial BCM2835 compatible RNG, and adds it as a peripheral to BCM2835 platform, which allows to boot a vanilla Raspberry Pi kernel under Qemu. Changes since v1: * Prevented guest from writing [31..20] bits in rng_status * Removed redundant minimum_version_id_old * Added field entries for the state * Changed realize function to reset Signed-off-by: Marcin Chojnacki <marcinch7@gmail.com> Message-id: 20170210210857.47893-1-marcinch7@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28Merge remote-tracking branch ↵Peter Maydell5-61/+395
'remotes/vivier2/tags/linux-user-for-upstream-pull-request' into staging # gpg: Signature made Mon 27 Feb 2017 22:15:47 GMT # gpg: using RSA key 0xF30C38BD3F2FBE3C # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" # gpg: aka "Laurent Vivier <laurent@vivier.eu>" # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/vivier2/tags/linux-user-for-upstream-pull-request: syscall: fixed mincore(2) not failing with ENOMEM linux-user: fix do_rt_sigreturn on m68k linux userspace emulation linux-user: correctly manage SR in ucontext linux-user: Add signal handling support for x86_64 linux-user: Add sockopts for IPv6 ping and IPv6 traceroute linux-user: fix fork() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-28Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into ↵Peter Maydell3-32/+98
staging # gpg: Signature made Mon 27 Feb 2017 16:33:23 GMT # gpg: using RSA key 0x9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/block-pull-request: tests-aio-multithread: use atomic_read properly iscsi: do not use aio_context_acquire/release nfs: do not use aio_context_acquire/release curl: do not use aio_context_acquire/release Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-27iscsi: add missing colons to the qapi docsJeff Cody1-9/+9
The missing colons make the iscsi part of the documentation not render quite as nicely, so add those in. Signed-off-by: Jeff Cody <jcody@redhat.com>
2017-02-28target/alpha: Enable MTTCG by defaultRichard Henderson2-0/+4
Alpha has a weak memory ordering and issues all of the required barriers. Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-02-27syscall: fixed mincore(2) not failing with ENOMEMFranklin \"Snaipe\" Mathieu1-3/+8
The current implementation of the mincore(2) syscall sets errno to EFAULT when the region identified by the first two parameters is invalid. This goes against the man page specification, where mincore(2) should only fail with EFAULT when the third parameter is an invalid address; and fail with ENOMEM when the checked region does not point to mapped memory. Signed-off-by: Franklin "Snaipe" Mathieu <snaipe@diacritic.io> Cc: Riku Voipio <riku.voipio@linaro.org> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170217085800.28873-2-snaipe@diacritic.io> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-27linux-user: fix do_rt_sigreturn on m68k linux userspace emulationMichael Karcher1-2/+1
do_rt_sigreturn uses an uninitialised local variable instead of fetching the old signal mask directly from the signal frame when restoring the mask, so the signal mask is undefined after do_rt_sigreturn. As the signal frame data is in target-endian order, target_to_host_sigset instead of target_to_host_sigset_internal is required. do_sigreturn is correct in using target_to_host_sigset_internal, because get_user already did the endianness conversion. Signed-off-by: Michael Karcher <karcher@physik.fu-berlin.de> Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170225110517.2832-3-laurent@vivier.eu>
2017-02-27linux-user: correctly manage SR in ucontextLaurent Vivier1-2/+3
Use cpu_m68k_get_ccr()/cpu_m68k_set_ccr() to setup and restore correctly the value of SR in the ucontext structure Signed-off-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170225110517.2832-2-laurent@vivier.eu>
2017-02-27linux-user: Add signal handling support for x86_64Pranith Kumar3-51/+241
Note that x86_64 has only _rt signal handlers. This implementation attempts to share code with the x86_32 implementation. CC: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Allan Wirth <awirth@akamai.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20170226165345.8757-1-bobby.prani@gmail.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-27linux-user: Add sockopts for IPv6 ping and IPv6 tracerouteHelge Deller2-1/+139
Add the neccessary sockopts for ping and traceroute on IPv6. This fixes the following qemu warnings with IPv6: Unsupported ancillary data: 0/2 Unsupported ancillary data: 0/11 Unsupported ancillary data: 41/25 Unsupported setsockopt level=0 optname=12 Unsupported setsockopt level=41 optname=16 Unsupported setsockopt level=41 optname=25 Unsupported setsockopt level=41 optname=50 Unsupported setsockopt level=41 optname=51 Unsupported setsockopt level=41 optname=8 Unsupported setsockopt level=58 optname=1 Tested with hppa-linux-user (big-endian) on x86_64 (little-endian). Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170218223130.GA25278@ls3530.fritz.box> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2017-02-27linux-user: fix fork()Laurent Vivier1-2/+3
Since commit 5ea2fc8 ("linux-user: Sanity check clone flags"), trying to run fork() fails with old distro on some architectures. This is the case with HP-PA and Debian 5 (Lenny). It fails on: if ((flags & CSIGNAL) != TARGET_SIGCHLD) { return -TARGET_EINVAL; } because flags is 17, whereas on HP-PA, SIGCHLD is 18. 17 is the SIGCHLD value of my host (x86_64). It appears that for TARGET_NR_fork and TARGET_NR_vfork, QEMU calls do_fork() with SIGCHLD instead of TARGET_SIGCHLD. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170216173707.16209-1-laurent@vivier.eu>
2017-02-27Merge remote-tracking branch 'remotes/kraxel/tags/pull-ui-20170227-1' into ↵Peter Maydell14-97/+178
staging gtk: fix kbd on xwayland vnc: fix double free issues opengl improvements # gpg: Signature made Mon 27 Feb 2017 16:11:30 GMT # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/pull-ui-20170227-1: vnc: fix double free issues spice: add display & head options ui: Use XkbGetMap and XkbGetNames instead of XkbGetKeyboard gtk-egl: add scanout_disable support sdl2: add scanout_disable support spice: add scanout_disable support virtio-gpu: use dpy_gl_scanout_disable console: add dpy_gl_scanout_disable console: rename dpy_gl_scanout to dpy_gl_scanout_texture Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-27block/mirror: fix broken sparseness detectionJohn Snow1-1/+1
int64_t is in all likelihood the actual scalar type we want. Yep, really. Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=1219541 Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Jeff Cody <jcody@redhat.com> Signed-off-by: Jeff Cody <jcody@redhat.com>
2017-02-27Merge remote-tracking branch ↵Peter Maydell2-6/+3
'remotes/berrange/tags/pull-qcrypto-2017-02-27-1' into staging Merge qcrypto 2017/02/27 v1 # gpg: Signature made Mon 27 Feb 2017 13:37:34 GMT # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qcrypto-2017-02-27-1: crypto: assert cipher algorithm is always valid crypto: fix leak in ivgen essiv init Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-02-27vnc: fix double free issuesGerd Hoffmann1-0/+3
Reported by Coverity: CID 1371242, 1371243, 1371244. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1487682332-29154-1-git-send-email-kraxel@redhat.com
2017-02-27spice: add display & head optionsGerd Hoffmann2-1/+27
This allows to specify display and head to use, simliar to vnc. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 1487663858-11731-1-git-send-email-kraxel@redhat.com
2017-02-27ui: Use XkbGetMap and XkbGetNames instead of XkbGetKeyboardDaniel P. Berrange2-7/+10
XkbGetKeyboard does not work in XWayland and even on non-Wayland X11 servers its use is discouraged: https://bugs.freedesktop.org/show_bug.cgi?id=89240 This resolves a problem whereby QEMU prints "could not lookup keycode name" on startup when running under XWayland. Keymap handling is however still broken after this commit, since Xwayland is reporting a keymap we can't handle "unknown keycodes `(unnamed)', please report to qemu-devel@nongnu.org" NB, native Wayland support (which is the default under GTK3) is not affected - only XWayland (which can be requested with GDK_BACKEND on GTK3, and is the only option for GTK2). Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-id: 20170227132343.30824-1-berrange@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2017-02-27gtk-egl: add scanout_disable supportGerd Hoffmann3-5/+12
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1487669841-13668-7-git-send-email-kraxel@redhat.com
generated by cgit v1.1 at 2025-01-28 14:12:53 +0000