riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-06-19	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	Bin Meng	3	-15/+17
2020-06-19	target/riscv: Rename IBEX CPU init routine	Bin Meng	1	-2/+2
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng	2	-0/+8
2020-06-19	hw/riscv: sifive_u: Rename serial property get/set functions to a generic name	Bin Meng	1	-6/+8
2020-06-19	hw/riscv: sifive_u: Add reset functionality	Bin Meng	1	-1/+23
2020-06-19	hw/riscv: sifive_gpio: Do not blindly trigger output IRQs	Bin Meng	1	-1/+3
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng	2	-2/+60
2020-06-19	hw/riscv: sifive_gpio: Add a new 'ngpio' property	Bin Meng	2	-11/+22
2020-06-19	hw/riscv: sifive_gpio: Clean up the codes	Bin Meng	2	-11/+9
2020-06-19	hw/riscv: sifive_u: Generate device tree node for OTP	Bin Meng	1	-0/+11
2020-06-19	hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit	Bin Meng	1	-6/+1
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-15/+14
2020-06-19	hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-12/+12
2020-06-19	target/riscv: Use a smaller guess size for no-MMU PMP	Alistair Francis	1	-5/+9
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis	2	-2/+36
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis	2	-2/+15
2020-06-19	hw/intc: Initial commit of lowRISC Ibex PLIC	Alistair Francis	4	-0/+327
2020-06-19	hw/char: Initial commit of Ibex UART	Alistair Francis	5	-0/+609
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis	1	-1/+2
2020-06-19	target/riscv: Implement checks for hfence	Alistair Francis	3	-26/+24
2020-06-19	target/riscv: Move the hfence instructions to the rvh decode	Alistair Francis	4	-41/+63
2020-06-19	target/riscv: Report errors validating 2nd-stage PTEs	Alistair Francis	1	-2/+7
2020-06-19	target/riscv: Set access as data_load when validating stage-2 PTEs	Alistair Francis	1	-1/+1
2020-06-19	riscv: Keep the CPU init routine names consistent	Bin Meng	1	-4/+4
2020-06-19	riscv: Generalize CPU init routine for the imacu CPU	Bin Meng	1	-21/+10
2020-06-19	riscv: Generalize CPU init routine for the gcsu CPU	Bin Meng	1	-14/+6
2020-06-19	riscv: Generalize CPU init routine for the base CPU	Bin Meng	1	-13/+5
2020-06-19	sifive_e: Support the revB machine	Alistair Francis	2	-4/+31
2020-06-19	riscv: Add helper to make NaN-boxing for FP register	Ian Jiang	1	-2/+15
2020-06-19	Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into staging	Peter Maydell	32	-78/+1075
2020-06-18	Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...	Peter Maydell	19	-449/+905
2020-06-18	Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a'...	Peter Maydell	7	-51/+56
2020-06-18	net: Drop the NetLegacy structure, always use Netdev instead	Thomas Huth	2	-110/+13
2020-06-18	net: Drop the legacy "name" parameter from the -net option	Thomas Huth	3	-18/+10
2020-06-18	hw/net/e1000e: Do not abort() on invalid PSRCTL register value	Philippe Mathieu-Daudé	1	-3/+7
2020-06-18	colo-compare: Fix memory leak in packet_enqueue()	Derek Su	2	-8/+16
2020-06-18	net/colo-compare.c: Correct ordering in complete and finalize	Lukas Straub	1	-22/+23
2020-06-18	net/colo-compare.c: Check that colo-compare is active	Lukas Straub	1	-6/+29
2020-06-18	net/colo-compare.c: Only hexdump packets if tracing is enabled	Lukas Straub	1	-4/+6
2020-06-18	net/colo-compare.c: Fix deadlock in compare_chr_send	Lukas Straub	3	-45/+156
2020-06-18	chardev/char.c: Use qemu_co_sleep_ns if in coroutine	Lukas Straub	1	-1/+6
2020-06-18	net/colo-compare.c: Create event_bh with the right AioContext	Lukas Straub	1	-1/+2
2020-06-18	net: use peer when purging queue in qemu_flush_or_purge_queue_packets()	Jason Wang	1	-1/+1
2020-06-18	net: cadence_gem: Fix RX address filtering	Tong Ho	1	-15/+11
2020-06-18	net: cadence_gem: TX_LAST bit should be set by guest	Sai Pavan Boddu	1	-6/+0
2020-06-18	net: cadence_gem: Update the reset value for interrupt mask register	Sai Pavan Boddu	1	-0/+1
2020-06-18	net: cadnece_gem: Update irq_read_clear field of designcfg_debug1 reg	Sai Pavan Boddu	1	-1/+1
2020-06-18	net: cadence_gem: Add support for jumbo frames	Sai Pavan Boddu	2	-6/+49
2020-06-18	net: cadence_gem: Fix up code style	Sai Pavan Boddu	1	-101/+103
2020-06-18	net: cadence_gem: Move tx/rx packet buffert to CadenceGEMState	Sai Pavan Boddu	2	-21/+21