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2023-05-05target/riscv: Use check for relationship between Zdinx/Zhinx{min} and ZfinxWeiwei Li1-2/+3
2023-05-05target/riscv: Legalize MPP value in write_mstatusWeiwei Li2-6/+34
2023-05-05target/riscv: Use PRV_RESERVED instead of PRV_HWeiwei Li5-5/+5
2023-05-05target/riscv: Fix the mstatus.MPP value after executing MRETWeiwei Li1-1/+2
2023-05-05target/riscv/cpu.c: redesign register_cpu_props()Daniel Henrique Barboza2-35/+11
2023-05-05target/riscv: add RVG and remove cpu->cfg.ext_gDaniel Henrique Barboza2-10/+9
2023-05-05target/riscv: remove cfg.ext_g setup from rv64_thead_c906_cpu_init()Daniel Henrique Barboza1-2/+1
2023-05-05target/riscv: remove riscv_cpu_sync_misa_cfg()Daniel Henrique Barboza1-52/+0
2023-05-05target/riscv: remove cpu->cfg.ext_vDaniel Henrique Barboza2-8/+5
2023-05-05target/riscv: remove cpu->cfg.ext_jDaniel Henrique Barboza2-4/+3
2023-05-05target/riscv: remove cpu->cfg.ext_hDaniel Henrique Barboza2-6/+5
2023-05-05target/riscv: remove cpu->cfg.ext_uDaniel Henrique Barboza2-6/+4
2023-05-05target/riscv: remove cpu->cfg.ext_sDaniel Henrique Barboza2-7/+5
2023-05-05target/riscv: remove cpu->cfg.ext_mDaniel Henrique Barboza2-6/+5
2023-05-05target/riscv: remove cpu->cfg.ext_eDaniel Henrique Barboza3-7/+6
2023-05-05target/riscv: remove cpu->cfg.ext_iDaniel Henrique Barboza2-9/+7
2023-05-05target/riscv: remove cpu->cfg.ext_fDaniel Henrique Barboza2-14/+13
2023-05-05target/riscv: remove cpu->cfg.ext_dDaniel Henrique Barboza2-10/+8
2023-05-05target/riscv: remove cpu->cfg.ext_cDaniel Henrique Barboza2-6/+4
2023-05-05target/riscv: remove cpu->cfg.ext_aDaniel Henrique Barboza2-9/+8
2023-05-05target/riscv: introduce riscv_cpu_add_misa_properties()Daniel Henrique Barboza1-0/+65
2023-05-05target/riscv/cpu.c: remove 'multi_letter' from isa_ext_dataDaniel Henrique Barboza1-67/+65
2023-05-05target/riscv: remove MISA properties from isa_edata_arr[]Daniel Henrique Barboza1-2/+17
2023-05-05target/riscv: sync env->misa_ext* with cpu->cfg in realize()Daniel Henrique Barboza1-38/+56
2023-05-05hw/riscv: Add signature dump function for spike to run ACT testsWeiwei Li3-1/+59
2023-05-05target/riscv: Fix lines with over 80 charactersWeiwei Li9-56/+91
2023-05-05target/riscv: Fix format for commentsWeiwei Li11-104/+151
2023-05-05target/riscv: Fix format for indentationWeiwei Li12-241/+247
2023-05-05target/riscv: Remove riscv_cpu_virt_enabled()Weiwei Li8-70/+64
2023-05-05target/riscv: Set opcode to env->bins for illegal/virtual instruction faultWeiwei Li1-0/+2
2023-05-05target/riscv: Fix addr type for get_physical_addressWeiwei Li1-2/+2
2023-05-05target/riscv: Remove redundant parenthesesWeiwei Li1-1/+1
2023-05-05target/riscv: Convert env->virt to a bool env->virt_enabledLIU Zhiwei5-12/+9
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_set_virt_enabledWeiwei Li1-4/+1
2023-05-05target/riscv: Remove check on RVH for riscv_cpu_virt_enabledWeiwei Li1-4/+0
2023-05-05target/riscv: Remove redundant check on RVHWeiwei Li1-2/+1
2023-05-05target/riscv: Remove redundant call to riscv_cpu_virt_enabledWeiwei Li1-3/+1
2023-05-05target/riscv: Fix itrigger when icount is usedLIU Zhiwei1-0/+6
2023-05-05target/riscv: Add support for ZceWeiwei Li2-0/+13
2023-05-05disas/riscv.c: add disasm support for Zc*Weiwei Li1-1/+227
2023-05-05target/riscv: expose properties for Zc* extensionWeiwei Li1-0/+14
2023-05-05target/riscv: add support for Zcmt extensionWeiwei Li9-5/+157
2023-05-05target/riscv: add support for Zcmp extensionWeiwei Li3-1/+209
2023-05-05target/riscv: add support for Zcb extensionWeiwei Li3-0/+125
2023-05-05target/riscv: add support for Zcd extensionWeiwei Li2-4/+22
2023-05-05target/riscv: add support for Zcf extensionWeiwei Li2-4/+22
2023-05-05target/riscv: add support for Zca extensionWeiwei Li2-4/+8
2023-05-05target/riscv: add cfg properties for Zc* extensionWeiwei Li2-0/+49
2023-05-05target/riscv: fix invalid riscv,event-to-mhpmcounters entryConor Dooley1-1/+1
2023-05-05target/riscv: redirect XVentanaCondOps to use the Zicond functionsPhilipp Tomsich2-16/+4
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