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2022-01-10Revert "virtio-mmio: add support for configure interrupt"Michael S. Tsirkin1-27/+0
2022-01-10Revert "virtio-pci: add support for configure interrupt"Michael S. Tsirkin2-83/+13
2022-01-10Merge remote-tracking branch 'remotes/vivier/tags/m68k-for-7.0-pull-request' ...Peter Maydell4-5/+16
2022-01-09target/m68k: don't word align SP in stack frame if M68K_FEATURE_UNALIGNED_DAT...Mark Cave-Ayland1-1/+4
2022-01-09macfb: fix VRAM dirty memory region loggingMark Cave-Ayland1-1/+1
2022-01-09q800: fix segfault with invalid MacROMLaurent Vivier1-2/+3
2022-01-09hw: m68k: Add virt compat machine type for 7.0Laurent Vivier1-1/+8
2022-01-08Merge tag 'bsd-user-arm-pull-request' of gitlab.com:bsdimp/qemu into stagingRichard Henderson24-350/+1214
2022-01-07Merge tag 'pull-riscv-to-apply-20220108' of github.com:alistair23/qemu into s...Richard Henderson81-749/+2317
2022-01-07bsd-user: add arm target buildWarner Losh1-0/+2
2022-01-07bsd-user/freebsd/target_os_ucontext.h: Require TARGET_*CONTEXT_SIZEWarner Losh1-2/+0
2022-01-07bsd-user/arm/signal.c: arm get_ucontext_sigreturnWarner Losh1-0/+9
2022-01-07bsd-user/arm/signal.c: arm set_mcontextWarner Losh1-0/+76
2022-01-07bsd-user/arm/signal.c: arm get_mcontextWarner Losh1-0/+51
2022-01-07bsd-user/arm/signal.c: arm set_sigtramp_argsWarner Losh1-0/+60
2022-01-07bsd-user/arm/target_arch_signal.h: Define size of *context_tWarner Losh1-0/+3
2022-01-07bsd-user/arm/target_arch_signal.h: arm machine context and trapframe for signalsWarner Losh1-0/+28
2022-01-07bsd-user/arm/target_arch_signal.h: arm specific signal registers and stackWarner Losh1-0/+57
2022-01-07bsd-user/arm/target_arch_elf.h: arm get_hwcap2 implWarner Losh1-0/+22
2022-01-07bsd-user/arm/target_arch_elf.h: arm get hwcapWarner Losh1-1/+71
2022-01-07bsd-user/arm/target_arch_elf.h: arm defines for ELFWarner Losh1-0/+36
2022-01-07bsd-user/arm/target_arch_thread.h: Routines to create and switch to a threadWarner Losh1-0/+82
2022-01-07bsd-user/arm/target_arch_sigtramp.h: Signal Trampoline for armWarner Losh1-0/+49
2022-01-07bsd-user/arm/target_arch_vmparam.h: Parameters for arm address spaceWarner Losh1-0/+48
2022-01-07bsd-user/arm/target_arch_reg.h: Implement core dump register copyingWarner Losh1-0/+60
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement system call dispatchWarner Losh1-0/+94
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement data abort exceptionsWarner Losh1-0/+11
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement trivial EXCP exceptionsWarner Losh1-0/+33
2022-01-07bsd-user/arm/target_arch_cpu.h: Dummy target_cpu_loop implementationWarner Losh1-0/+22
2022-01-07bsd-user/arm/target_arch_cpu.h: Implement target_cpu_clone_regsWarner Losh1-0/+8
2022-01-07bsd-user/arm/target_arch_cpu.h: CPU Loop definitionsWarner Losh1-0/+43
2022-01-07bsd-user/arm/target_arch_cpu.c: Target specific TLS routinesWarner Losh2-0/+67
2022-01-07bsd-user/arm/target_syscall.h: Add copyright and update nameWarner Losh1-4/+23
2022-01-07bsd-user/arm/target_arch_sysarch.h: Use consistent include guardsWarner Losh1-3/+3
2022-01-07bsd-user/target_os_signal.h: Move signal prototypes to target_os_ucontext.hWarner Losh3-18/+11
2022-01-07bsd-user/x86_64: Move functions into signal.cWarner Losh2-36/+63
2022-01-07bsd-user/x86_64/target_arch_signal.h: Fill in mcontext_tWarner Losh1-0/+54
2022-01-07bsd-user/x86_64/target_arch_signal.h: use new target_os_ucontext.hWarner Losh1-8/+1
2022-01-07bsd-user/x86_64/target_arch_signal.h: Remove target_sigcontextWarner Losh1-4/+0
2022-01-07bsd-user/i386: Move the inlines into signal.cWarner Losh2-36/+63
2022-01-07bsd-user/i386/target_arch_signal.h: Update mcontext_t to match FreeBSDWarner Losh1-0/+46
2022-01-07bsd-user/i386/target_arch_signal.h: use new target_os_ucontext.hWarner Losh1-8/+1
2022-01-07bsd-user/i386/target_arch_signal.h: Remove target_sigcontextWarner Losh1-4/+0
2022-01-07bsd-user: create a per-arch signal.c fileWarner Losh3-1/+3
2022-01-07bsd-user/freebsd: Create common target_os_ucontext.h fileWarner Losh2-3/+35
2022-01-07bsd-user/mips*: Remove mips supportWarner Losh4-243/+0
2022-01-08target/riscv: Implement the stval/mtval illegal instructionAlistair Francis3-0/+8
2022-01-08target/riscv: Fixup setting GVAAlistair Francis1-15/+6
2022-01-08target/riscv: Set the opcode in DisasContextAlistair Francis1-0/+2
2022-01-08target/riscv: actual functions to realize crs 128-bit insnsFrédéric Pétrot3-30/+175
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