aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2019-01-03target/mips: Support R5900 three-operand MADD1 and MADDU1 instructionsFredrik Noring1-3/+9
2019-01-03target/mips: Support R5900 three-operand MADD and MADDU instructionsPhilippe Mathieu-Daudé1-5/+53
2019-01-03target/mips: MXU: Add handler for an align instructionAleksandar Markovic1-3/+194
2019-01-03target/mips: MXU: Add handlers for max/min instructionsAleksandar Markovic1-21/+279
2019-01-03target/mips: MXU: Add handlers for logic instructionsAleksandar Markovic1-34/+205
2019-01-03target/mips: MXU: Improve the comment containing MXU overviewAleksandar Markovic1-30/+44
2019-01-03target/mips: MXU: Add generic naming for optn2 constantsAleksandar Markovic1-0/+5
2019-01-03target/mips: MXU: Add missing opcodes/decoding for LX* instructionsAleksandar Markovic1-38/+102
2019-01-03atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32Paul Burton1-2/+3
2019-01-03MAINTAINERS: Add Aleksandar Rikalo as a reviewer for MIPS contentAleksandar Markovic1-0/+9
2019-01-03MAINTAINERS: target/mips: Reorder items alphabeticallyAleksandar Markovic1-5/+5
2019-01-03MAINTAINERS: target/mips: Add filter for mips in email subjectsAleksandar Markovic1-0/+1
2019-01-03MAINTAINERS: target/mips: Add MIPS files under default-configs directoryAleksandar Markovic1-0/+1
2019-01-03Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part1'...Peter Maydell15-43/+231
2019-01-03Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181226' into stagingPeter Maydell19-164/+2945
2018-12-26tcg: Improve call argument loadingRichard Henderson1-1/+2
2018-12-26tcg: Record register preferences during livenessRichard Henderson1-32/+165
2018-12-26tcg: Add TCG_OPF_BB_EXITRichard Henderson3-10/+16
2018-12-26tcg: Split out more subroutines from liveness_pass_1Richard Henderson1-12/+23
2018-12-26tcg: Rename and adjust liveness_pass_1 helpersRichard Henderson1-8/+5
2018-12-26tcg: Reindent parts of liveness_pass_1Richard Henderson1-67/+70
2018-12-26tcg: Dump register preference info with livenessRichard Henderson2-10/+37
2018-12-26tcg: Improve register allocation for matching constraintsRichard Henderson1-12/+24
2018-12-26tcg: Add output_pref to TCGOpRichard Henderson2-7/+14
2018-12-26tcg: Add preferred_reg argument to tcg_reg_alloc_do_moviRichard Henderson1-4/+5
2018-12-26tcg: Add preferred_reg argument to temp_syncRichard Henderson1-8/+8
2018-12-26tcg: Add preferred_reg argument to temp_loadRichard Henderson1-9/+9
2018-12-26tcg: Add preferred_reg argument to tcg_reg_allocRichard Henderson1-22/+81
2018-12-26tcg: Add reachable_code_passRichard Henderson1-0/+76
2018-12-26tcg: Reference count labelsRichard Henderson4-1/+25
2018-12-26tcg: Add TCG_CALL_NO_RETURNRichard Henderson3-7/+29
2018-12-26tcg: Renumber TCG_CALL_* flagsRichard Henderson1-3/+3
2018-12-26linux-user: Add safe_syscall for riscv64 hostRichard Henderson2-0/+100
2018-12-26disas/microblaze: Remove unused REG_SP macroRichard Henderson1-1/+0
2018-12-26configure: Add support for building RISC-V hostAlistair Francis1-2/+10
2018-12-26disas: Add RISC-V supportAlistair Francis1-2/+8
2018-12-26tcg: Add RISC-V cpu signal handlerAlistair Francis1-0/+75
2018-12-26tcg/riscv: Add the target init codeAlistair Francis1-0/+31
2018-12-26tcg/riscv: Add the prologue generation and register the JITAlistair Francis1-0/+111
2018-12-26tcg/riscv: Add the out op decoderAlistair Francis1-0/+496
2018-12-26tcg/riscv: Add direct load and store instructionsAlistair Francis1-0/+158
2018-12-26tcg/riscv: Add slowpath load and store instructionsAlistair Francis1-0/+256
2018-12-26tcg/riscv: Add branch and jump instructionsAlistair Francis1-0/+145
2018-12-26tcg/riscv: Add the add2 and sub2 instructionsAlistair Francis1-0/+55
2018-12-26tcg/riscv: Add the out load and store instructionsAlistair Francis1-0/+65
2018-12-26tcg/riscv: Add the extract instructionsAlistair Francis1-0/+34
2018-12-26tcg/riscv: Add the mov and movi instructionAlistair Francis1-0/+86
2018-12-26tcg/riscv: Add the relocation functionsAlistair Francis1-0/+88
2018-12-26tcg/riscv: Add the instruction emittersAlistair Francis1-0/+48
2018-12-26tcg/riscv: Add the immediate encodersAlistair Francis1-0/+90
generated by cgit v1.1 at 2024-12-29 10:51:50 +0000