riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-09-21	hw/core: Make do_unaligned_access noreturn	Richard Henderson	12	-21/+23
2021-09-21	tcg/sparc: Introduce tcg_out_mov_delay	Richard Henderson	1	-6/+15
2021-09-21	tcg/sparc: Drop inline markers	Richard Henderson	1	-23/+22
2021-09-21	tcg/mips: Drop special alignment for code_gen_buffer	Richard Henderson	1	-91/+0
2021-09-21	tcg/mips: Unset TCG_TARGET_HAS_direct_jump	Richard Henderson	2	-25/+10
2021-09-21	tcg/mips: Allow JAL to be out of range in tcg_out_bswap_subr	Richard Henderson	1	-2/+4
2021-09-21	tcg/mips: Drop inline markers	Richard Henderson	1	-49/+27
2021-09-21	accel/tcg: Restrict cpu_handle_halt() to sysemu	Philippe Mathieu-Daudé	1	-2/+4
2021-09-21	include/exec: Move cpu_signal_handler declaration	Richard Henderson	22	-89/+13
2021-09-21	Merge remote-tracking branch 'remotes/alistair23/tags/pull-riscv-to-apply-202...	Richard Henderson	34	-669/+1844
2021-09-21	Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210921'...	Peter Maydell	24	-168/+1825
2021-09-21	target/arm: Optimize MVE 1op-immediate insns	Peter Maydell	1	-5/+21
2021-09-21	target/arm: Optimize MVE VSLI and VSRI	Peter Maydell	1	-2/+2
2021-09-21	target/arm: Optimize MVE VSHLL and VMOVL	Peter Maydell	1	-8/+59
2021-09-21	target/arm: Optimize MVE VSHL, VSHR immediate forms	Peter Maydell	1	-20/+63
2021-09-21	target/arm: Optimize MVE VMVN	Peter Maydell	1	-1/+1
2021-09-21	target/arm: Optimize MVE VDUP	Peter Maydell	1	-4/+8
2021-09-21	target/arm: Optimize MVE VNEG, VABS	Peter Maydell	1	-10/+22
2021-09-21	target/arm: Optimize MVE arithmetic ops	Peter Maydell	1	-9/+11
2021-09-21	target/arm: Optimize MVE logic ops	Peter Maydell	1	-15/+36
2021-09-21	target/arm: Add TB flag for "MVE insns not predicated"	Peter Maydell	7	-9/+92
2021-09-21	target/arm: Enforce that FPDSCR.LTPSIZE is 4 on inbound migration	Peter Maydell	1	-0/+13
2021-09-21	target/arm: Avoid goto_tb if we're trying to exit to the main loop	Peter Maydell	1	-1/+33
2021-09-21	hvf: arm: Add rudimentary PMC support	Alexander Graf	1	-0/+179
2021-09-21	arm: Add Hypervisor.framework build target	Alexander Graf	3	-0/+12
2021-09-21	hvf: arm: Implement PSCI handling	Alexander Graf	3	-7/+139
2021-09-21	hvf: arm: Implement -cpu host	Peter Maydell	5	-6/+124
2021-09-21	arm/hvf: Add a WFI handler	Peter Collingbourne	3	-3/+82
2021-09-21	Merge remote-tracking branch 'remotes/legoater/tags/pull-aspeed-20210920' int...	Peter Maydell	15	-76/+529
2021-09-21	hw/riscv: opentitan: Correct the USB Dev address	Alistair Francis	1	-1/+1
2021-09-21	target/riscv: csr: Rename HCOUNTEREN_CY and friends	Bin Meng	2	-16/+16
2021-09-21	target/riscv: Backup/restore mstatus.SD bit when virtual register swapped	Frank Chang	1	-1/+2
2021-09-21	docs/system/riscv: sifive_u: Update U-Boot instructions	Bin Meng	1	-23/+26
2021-09-21	hw/dma: sifive_pdma: don't set Control.error if 0 bytes to transfer	Frank Chang	1	-6/+6
2021-09-21	hw/dma: sifive_pdma: allow non-multiple transaction size transactions	Green Wan	1	-6/+10
2021-09-21	hw/dma: sifive_pdma: claim bit must be set before DMA transactions	Frank Chang	1	-0/+9
2021-09-21	hw/dma: sifive_pdma: reset Next* registers when Control.claim is set	Frank Chang	1	-0/+19
2021-09-21	hw/riscv: virt: Add optional ACLINT support to virt machine	Anup Patel	3	-1/+124
2021-09-21	hw/riscv: virt: Re-factor FDT generation	Anup Patel	1	-200/+327
2021-09-21	hw/intc: Upgrade the SiFive CLINT implementation to RISC-V ACLINT	Anup Patel	8	-156/+339
2021-09-21	hw/intc: Rename sifive_clint sources to riscv_aclint sources	Anup Patel	11	-15/+15
2021-09-21	sifive_u: Connect the SiFive PWM device	Alistair Francis	4	-2/+69
2021-09-21	hw/timer: Add SiFive PWM support	Alistair Francis	5	-0/+540
2021-09-21	hw/intc: ibex_timer: Convert the timer to use RISC-V CPU GPIO lines	Alistair Francis	3	-5/+17
2021-09-21	hw/intc: sifive_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis	7	-12/+33
2021-09-21	hw/intc: ibex_plic: Convert the PLIC to use RISC-V CPU GPIO lines	Alistair Francis	3	-11/+16
2021-09-21	hw/intc: sifive_clint: Use RISC-V CPU GPIO lines	Alistair Francis	2	-20/+50
2021-09-21	target/riscv: Expose interrupt pending bits as GPIO lines	Alistair Francis	1	-0/+30
2021-09-21	target/riscv: Fix satp write	LIU Zhiwei	1	-1/+1
2021-09-21	target/riscv: Update the ePMP CSR address	Alistair Francis	2	-2/+3