riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2021-12-21	ui/vdagent: add CHECK_SPICE_PROTOCOL_VERSION	Marc-André Lureau	2	-0/+13
2021-12-20	Merge tag 'pull-user-20211220' of https://gitlab.com/rth7680/qemu into staging	Richard Henderson	80	-930/+1097
2021-12-20	Merge tag 'pull-riscv-to-apply-20211220-1' of github.com:alistair23/qemu into...	Richard Henderson	16	-3099/+4997
2021-12-20	meson: Move bsd_user_ss to bsd-user/	Richard Henderson	2	-3/+4
2021-12-20	meson: Move linux_user_ss to linux-user/	Richard Henderson	2	-3/+4
2021-12-20	linux-user: Move thunk.c from top-level	Richard Henderson	4	-2/+1
2021-12-20	common-user: Adjust system call return on FreeBSD	Richard Henderson	4	-1/+44
2021-12-20	common-user: Move safe-syscall.* from linux-user	Richard Henderson	19	-15/+42
2021-12-20	hw/riscv: Use load address rather than entry point for fw_dynamic next_addr	Jessica Clarke	1	-3/+10
2021-12-20	target/riscv: Enable bitmanip Zb[abcs] instructions	Vineet Gupta	1	-4/+4
2021-12-20	riscv: Set 5.4 as minimum kernel version for riscv32	Khem Raj	1	-1/+2
2021-12-20	target/riscv: rvv-1.0: Add ELEN checks for widening and narrowing instructions	Frank Chang	2	-6/+13
2021-12-20	target/riscv: rvv-1.0: update opivv_vadc_check() comment	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: rename vmandnot.mm and vmornot.mm to vmandn.mm and vmo...	Frank Chang	4	-8/+8
2021-12-20	target/riscv: rvv-1.0: add vector unit-stride mask load/store insns	Frank Chang	4	-0/+67
2021-12-20	target/riscv: rvv-1.0: add evl parameter to vext_ldst_us()	Frank Chang	1	-18/+18
2021-12-20	target/riscv: rvv-1.0: add vsetivli instruction	Frank Chang	2	-0/+29
2021-12-20	target/riscv: rvv-1.0: rename r2_zimm to r2_zimm11	Frank Chang	1	-2/+2
2021-12-20	target/riscv: rvv-1.0: floating-point reciprocal estimate instruction	Frank Chang	4	-0/+197
2021-12-20	target/riscv: rvv-1.0: floating-point reciprocal square-root estimate instruc...	Frank Chang	4	-0/+189
2021-12-20	target/riscv: gdb: support vector registers for rv64 & rv32	Hsiangkai Wang	3	-0/+187
2021-12-20	target/riscv: rvv-1.0: trigger illegal instruction exception if frm is not valid	Frank Chang	1	-0/+22
2021-12-20	target/riscv: rvv-1.0: implement vstart CSR	Frank Chang	5	-103/+199
2021-12-20	target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits	Frank Chang	3	-4/+4
2021-12-20	target/riscv: rvv-1.0: narrowing floating-point/integer type-convert	Frank Chang	4	-44/+97
2021-12-20	target/riscv: add "set round to odd" rounding mode helper function	Frank Chang	4	-0/+14
2021-12-20	target/riscv: rvv-1.0: widening floating-point/integer type-convert	Frank Chang	4	-14/+63
2021-12-20	target/riscv: rvv-1.0: floating-point/integer type-convert instructions	Frank Chang	2	-36/+59
2021-12-20	target/riscv: introduce floating-point rounding mode enum	Frank Chang	3	-15/+24
2021-12-20	target/riscv: rvv-1.0: floating-point min/max instructions	Frank Chang	1	-12/+12
2021-12-20	target/riscv: rvv-1.0: remove integer extract instruction	Frank Chang	2	-24/+0
2021-12-20	target/riscv: rvv-1.0: remove vmford.vv and vmford.vf	Frank Chang	4	-17/+0
2021-12-20	target/riscv: rvv-1.0: remove widening saturating scaled multiply-add	Frank Chang	4	-243/+0
2021-12-20	target/riscv: rvv-1.0: single-width scaling shift instructions	Frank Chang	1	-2/+2
2021-12-20	target/riscv: rvv-1.0: widening floating-point reduction instructions	Frank Chang	1	-1/+8
2021-12-20	target/riscv: rvv-1.0: single-width floating-point reduction	Frank Chang	2	-9/+15
2021-12-20	target/riscv: rvv-1.0: narrowing fixed-point clip instructions	Frank Chang	4	-50/+50
2021-12-20	target/riscv: rvv-1.0: floating-point slide instructions	Frank Chang	4	-45/+121
2021-12-20	target/riscv: rvv-1.0: slide instructions	Frank Chang	1	-7/+12
2021-12-20	target/riscv: rvv-1.0: mask-register logical instructions	Frank Chang	2	-5/+2
2021-12-20	target/riscv: rvv-1.0: floating-point compare instructions	Frank Chang	1	-9/+0
2021-12-20	target/riscv: rvv-1.0: integer comparison instructions	Frank Chang	2	-11/+2
2021-12-20	target/riscv: rvv-1.0: single-width saturating add and subtract instructions	Frank Chang	1	-1/+1
2021-12-20	target/riscv: rvv-1.0: widening integer multiply-add instructions	Frank Chang	1	-3/+3
2021-12-20	target/riscv: rvv-1.0: narrowing integer right shift instructions	Frank Chang	4	-51/+51
2021-12-20	target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow	Frank Chang	3	-26/+17
2021-12-20	target/riscv: rvv-1.0: single-width bit shift instructions	Frank Chang	1	-3/+3
2021-12-20	target/riscv: rvv-1.0: single-width averaging add and subtract instructions	Frank Chang	4	-6/+102
2021-12-20	target/riscv: rvv-1.0: integer extension instructions	Frank Chang	4	-0/+133
2021-12-20	target/riscv: rvv-1.0: whole register move instructions	Frank Chang	2	-0/+29