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2013-12-20Add xxpermdiTom Musta1-1/+40
2013-12-20Add stxvd2xTom Musta1-0/+18
2013-12-20Add lxvd2xTom Musta1-0/+18
2013-12-20Add VSR to Global RegistersTom Musta1-0/+27
2013-12-20Add VSX Instruction DecodersTom Musta1-0/+11
2013-12-20Add MSR VSX and Associated ExceptionTom Musta4-2/+18
2013-12-20Declare and Enable VSXTom Musta2-3/+8
2013-12-20powerpc: add PVR mask supportAlexey Kardashevskiy5-0/+56
2013-12-20target-ppc: add stubs for KVM breakpointsGreg Kurz1-0/+28
2013-12-19Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into st...Anthony Liguori50-694/+5229
2013-12-18s390x/ioinst: CHSC has to set a condition codeThomas Huth1-0/+1
2013-12-18s390x/kvm: Fixed condition code for unknown SIGP ordersThomas Huth1-6/+11
2013-12-18s390x/kvm: Simplified the calculation of the SIGP order codeThomas Huth1-5/+3
2013-12-18s390x/kvm: Implemented SIGP STARTThomas Huth1-0/+11
2013-12-18s390x/kvm: Fix coding style in handle_sigp()Thomas Huth1-12/+12
2013-12-18s390x/kvm: Removed s390_store_status stubThomas Huth1-22/+0
2013-12-18s390x/kvm: Removed duplicated SIGP definesThomas Huth1-5/+0
2013-12-18s390x/kvm: Fix diagnose handling.Cornelia Huck2-6/+16
2013-12-17MAINTAINERS: add myself to maintain allwinner-a10liguang1-0/+7
2013-12-17hw/arm: add cubieboard supportliguang3-1/+71
2013-12-17hw/arm: add allwinner a10 SoC supportliguang4-0/+140
2013-12-17hw/intc: add allwinner A10 interrupt controllerliguang4-0/+242
2013-12-17hw/timer: add allwinner a10 timerliguang4-0/+316
2013-12-17vmstate: Add support for an array of ptimer_state *Peter Maydell2-0/+14
2013-12-17MAINTAINERS: Document 'Canon DIGIC' machineAntony Pavlov1-0/+6
2013-12-17hw/arm/digic: add NOR ROM supportAntony Pavlov1-0/+78
2013-12-17hw/arm/digic: add UART supportAntony Pavlov5-0/+261
2013-12-17hw/arm/digic: add timer supportAntony Pavlov5-0/+244
2013-12-17hw/arm/digic: prepare DIGIC-based boards supportAntony Pavlov3-0/+86
2013-12-17hw/arm: add very initial support for Canon DIGIC SoCAntony Pavlov4-0/+108
2013-12-17target-arm: A64: add support for logical (immediate) insnsAlexander Graf1-2/+173
2013-12-17target-arm: A64: add support for 1-src CLS insnClaudio Fontana3-1/+31
2013-12-17host-utils: add clrsb32/64 - count leading redundant sign bitsClaudio Fontana1-0/+32
2013-12-17target-arm: A64: add support for bitfield insnsClaudio Fontana1-2/+54
2013-12-17target-arm: A64: add support for 1-src REV insnsClaudio Fontana1-1/+72
2013-12-17target-arm: A64: add support for 1-src RBIT insnAlexander Graf3-0/+39
2013-12-17target-arm: A64: add support for 1-src data processing and CLZClaudio Fontana3-2/+56
2013-12-17target-arm: A64: add support for 2-src shift reg insnsAlexander Graf1-0/+22
2013-12-17target-arm: A64: add support for 2-src data processing and DIVAlexander Graf3-2/+93
2013-12-17target-arm: A64: add support for EXTRAlexander Graf1-2/+47
2013-12-17target-arm: A64: add support for ADR and ADRPAlexander Graf1-2/+23
2013-12-17target-arm: A64: add support for logical (shifted register)Alexander Graf1-6/+191
2013-12-17target-arm: A64: add support for conditional selectClaudio Fontana1-2/+65
2013-12-17target-arm: A64: add support for compare and branch immAlexander Graf1-2/+44
2013-12-17target-arm: A64: add support for 'test and branch' immAlexander Graf1-2/+25
2013-12-17target-arm: A64: add support for conditional branchesAlexander Graf3-7/+38
2013-12-17target-arm: A64: add support for BR, BLR and RET insnsAlexander Graf1-2/+41
2013-12-17target-arm: A64: add support for B and BL insnsAlexander Graf2-2/+65
2013-12-17target-arm: A64: expand decoding skeleton for system instructionsClaudio Fontana1-2/+129
2013-12-17target-arm: A64: provide skeleton for a64 insn decodingClaudio Fontana1-8/+362
generated by cgit v1.1 at 2025-01-17 23:54:28 +0000