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2015-05-29hw/acpi/aml-build: Add ToUUID macroShannon Zhao2-0/+54
Add ToUUID macro, this is useful for generating PCIe ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1432522520-8068-16-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Make aml_buffer() definition consistent with the specShannon Zhao2-3/+15
According to ACPI spec, DefBuffer can take two parameters: BufferSize and ByteList. Make it consistent with the spec. Uninitialized buffer could be requested by passing ByteList as NULL to reserve space. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1432522520-8068-15-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate MCFG tableShannon Zhao1-0/+23
Generate MCFG table for PCIe controller. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-14-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate RSDP tableShannon Zhao1-1/+34
RSDP points to RSDT which in turn points to other tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-13-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate RSDT tableShannon Zhao4-24/+29
RSDT points to other tables FADT, MADT, GTDT. This code is shared with x86. Here we still use RSDT as UEFI puts ACPI tables below 4G address space, and UEFI ignore the RSDT or XSDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-12-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate GTDT tableShannon Zhao4-4/+75
ACPI v5.1 defines GTDT for ARM devices as a place to describe timer related information in the system. The Arch Timer interrupts must be provided for GTDT. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-11-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate MADT tableShannon Zhao3-1/+97
MADT describes GIC enabled ARM platforms. The GICC and GICD subtables are used to define the GIC regions. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-10-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generate FADT table and update ACPI headersShannon Zhao2-37/+129
In the case of mach virt, it is used to set the Hardware Reduced bit and enable PSCI SMP booting through HVC. So ignore FACS and FADT points to DSDT. Update the header definitions for FADT taking into account the new additions of ACPI v5.1 in `include/hw/acpi/acpi-defs.h` Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-9-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Generation of DSDT table for virt devicesShannon Zhao1-0/+132
DSDT consists of the usual common table header plus a definition block in AML encoding which describes all devices in the platform. After initializing DSDT with header information the namespace is created which is followed by the device encodings. The devices are described using the Resource Template for the 32-Bit Fixed Memory Range and the Extended Interrupt Descriptors. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-8-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Add aml_interrupt() termShannon Zhao2-0/+69
Add aml_interrupt() for describing device interrupt in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-7-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Add aml_memory32_fixed() termShannon Zhao2-0/+30
Add aml_memory32_fixed() for describing device mmio region in resource template. These can be used to generating DSDT table for ACPI on ARM. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-id: 1432522520-8068-6-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt-acpi-build: Basic framework for building ACPI tables on ARMShannon Zhao5-1/+228
Introduce a preliminary framework in virt-acpi-build.c with the main ACPI build functions. It exposes the generated ACPI contents to guest over fw_cfg. The required ACPI v5.1 tables for ARM are: - RSDP: Initial table that points to XSDT - RSDT: Points to FADT GTDT MADT tables - FADT: Generic information about the machine - GTDT: Generic timer description table - MADT: Multiple APIC description table - DSDT: Holds all information about system devices/peripherals, pointed by FADT Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-5-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Record PCIe ranges in MemMapEntry arrayShannon Zhao2-24/+16
To generate ACPI table for PCIe controller, we need the base and size of the PCIe ranges. Record these ranges in MemMapEntry array, then we could share and use them for generating ACPI table. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Message-id: 1432522520-8068-4-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/arm/virt: Move common definitions to virt.hShannon Zhao2-20/+57
Move some common definitions to virt.h. These will be used by generating ACPI tables. Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1432522520-8068-3-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29hw/acpi/aml-build: Make enum values to be upper case to match coding styleShannon Zhao3-69/+69
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com> Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1432522520-8068-2-git-send-email-zhaoshenglong@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Add WFx instruction trap supportGreg Bellows1-1/+59
Add support for trapping WFI and WFE instructions to the proper EL when SCTLR/SCR/HCR settings apply. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: removed unnecessary tweaking of syn_wfx() prototype; use raise_exception(); don't trap on WFE (and add comment explaining why not); remove unnecessary ARM_FEATURE checks; trap to EL3, not EL1, if in S-EL0 and SCTLR check fires] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Don't halt on WFI unless we don't have any workPeter Maydell3-0/+15
Just NOP the WFI instruction if we have work to do. This doesn't make much difference currently (though it does avoid jumping out to the top level loop and immediately restarting), but the distinction between "halt" and "don't halt" will become more important when the decision to halt requires us to trap to a higher exception level instead. Suggested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Move TB flags down to fill gapPeter Maydell1-2/+2
Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Extend FP checks to use an ELGreg Bellows4-37/+82
Extend the ARM disassemble context to take a target exception EL instead of a boolean enable. This change reverses the polarity of the check making a value of 0 indicate floating point enabled (no exception). Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: Use a common TB flag field for AArch32 and AArch64; CPTR_EL2 exists in v7; CPTR_EL2 should trap for EL2 accesses; CPTR_EL2 should not trap for secure accesses; CPTR_EL3 should trap for EL3 accesses; CPACR traps for secure accesses should trap to EL3 if EL3 is AArch32] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Make singlestate TB flags common between AArch32/64Peter Maydell2-44/+29
Currently we keep the TB flags PSTATE_SS and SS_ACTIVE in different bit positions for AArch64 and AArch32. Replace these separate definitions with a single common flag in the upper part of the flags word. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Add AArch64 CPTR registersGreg Bellows2-1/+44
Adds CPTR_EL2/3 system registers definitions and access function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> [PMM: merge CPTR_EL2 and HCPTR definitions into a single def using STATE_BOTH; don't use readfn/writefn to implement RAZ/WI registers; don't use accessfn for the no-EL2 CPTR_EL2; fix cpacr_access logic to catch EL2 accesses to CPACR being trapped to EL3; use new CP_ACCESS_TRAP_EL[23] rather than setting exception.target_el directly] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Allow cp access functions to indicate traps to EL2 or EL3Peter Maydell2-2/+19
Some coprocessor access functions will need to indicate that the instruction should trap to EL2 or EL3 rather than the default target exception level; add corresponding CPAccessResult enum entries and handling code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Update interrupt handling to use target ELGreg Bellows4-61/+50
Updated the interrupt handling to utilize and report through the target EL exception field. This includes consolidating and cleaning up code where needed. Target EL is now calculated once in arm_cpu_exec_interrupt() and do_interrupt was updated to use the target_el exception field. The necessary code from arm_excp_target_el() was merged in where needed and the function removed. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Make raise_exception() take syndrome and target ELPeter Maydell1-40/+28
Rather than making every caller of raise_exception set the syndrome and target EL by hand, make these arguments to raise_exception() and have that do the job. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Set exception target EL in tlb_fillPeter Maydell1-0/+1
Set the exception target EL for MMU faults in tlb_fill. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Move setting of exception info into tlb_fillPeter Maydell5-44/+52
Move the code which sets exception information out of arm_cpu_handle_mmu_fault and into tlb_fill. tlb_fill is the only caller which wants to raise_exception() so it makes more sense for it to handle the whole of the exception setup. As part of this cleanup, move the user-mode-only implementation function for the handle_mmu_fault CPU method into cpu.c so we don't need to make it globally visible, and rename the softmmu-only utility function arm_cpu_handle_mmu_fault to arm_tlb_fill so it's clear that it's not the same thing. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Set correct syndrome for faults on MSR DAIF*, immPeter Maydell1-0/+3
If the SCTLR.UMA trap bit is set then attempts by EL0 to update the PSTATE DAIF bits via "MSR DAIFSet, imm" and "MSR DAIFClr, imm" instructions will raise an exception. We were failing to set the syndrome information for this exception, which meant that it would be reported as a repeat of whatever the previous exception was. Set the correct syndrome information. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
2015-05-29target-arm: Extend helpers to route exceptionsGreg Bellows1-0/+21
Updated the various helper routines to set the target EL as needed using a dedicated function. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-3-git-send-email-greg.bellows@linaro.org [PMM: Also set target_el in fault cases in access_check_cp_reg()] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29target-arm: Add exception target el infrastructureGreg Bellows6-37/+83
Add a CPU state exception target EL field that will be used for communicating the EL to which an exception should be routed. Add a disassembly context field for tracking the EL3 architecture needed for determining the target exception EL. Add a target EL argument to the generic exception helper for callers to specify the EL to which the exception should be routed. Extended the helper to set the newly added CPU state exception target el. Added a function for setting the target exception EL and updated calls to helpers to call it. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 1429722561-12651-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29Merge remote-tracking branch 'remotes/spice/tags/pull-spice-20150529-1' into ↵Peter Maydell4-1/+27
staging spice: misc fixes. # gpg: Signature made Fri May 29 09:16:29 2015 BST using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/spice/tags/pull-spice-20150529-1: spice: fix spice_chr_add_watch() pre-condition spice: don't update mm_time when spice-server is stopped. spice-char: notify the server when chardev is writable virtio-console: notify chardev when writable Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-29spice: fix spice_chr_add_watch() pre-conditionMarc-André Lureau1-1/+1
Since e02bc6de30c44fd668dc0d6e1cd1804f2eed3ed3, add_watch() is called with G_IO_HUP. Even if spice-qemu-char ignores this flag, the precondition must be changed. https://bugzilla.redhat.com/show_bug.cgi?id=1128992 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-05-29spice: don't update mm_time when spice-server is stopped.Gerd Hoffmann2-0/+5
Skip mm_time updates (in qxl device memory) in case the guest is stopped. Guest isn't able to look anyway, and it causes problems with migration. Also make sure the initial state for spice server is stopped. Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-05-29spice-char: notify the server when chardev is writableMarc-André Lureau1-0/+11
The spice server is polling on write, unless SPICE_CHAR_DEVICE_NOTIFY_WRITABLE flag is set. In this case, qemu must call spice_server_char_device_wakeup() when the frontend is writable. Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-05-29virtio-console: notify chardev when writableMarc-André Lureau1-0/+10
When the virtio serial is writable, notify the chardev backend with qemu_chr_accept_input(). Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2015-05-28Revert "gdbstub: Do not kill target in system emulation mode"Fabien Chouteau1-2/+0
The requirements described in this patch are implemented by "Add GDB qAttached support". This reverts commit 00e94dbc7fd0110b0555d59592b004333adfb4b8. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-28Add GDB qAttached supportJan Kiszka1-0/+10
With this patch QEMU handles qAttached request from gdb. When QEMU replies 1, GDB sends a "detach" command at the end of a debugging session otherwise GDB sends "kill". The default value for qAttached is 1 on system emulation and 0 on user emulation. Based on original version by Fabien Chouteau. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-28gdbstub: Introduce an is is_query_packet helperJan Kiszka1-2/+10
This helper supports parsing of query packets with optional extensions. The separator can be specified so that we can use it already for both qqemu.sstep[=] and qSupported[:feature]. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-28gdbstub: Fix qOffsets packet detectionJan Kiszka1-1/+1
qOffsets has no additional optional parameters. So match the complete string to avoid stumbling over possible future commands with identical prefix. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-28Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20150528' into stagingPeter Maydell11-43/+357
A set of patches add support for vector registers on s390x. Notable: Floating point registers and vector registers overlap, so extra care is needed so that we end up with a consistent state in all cases. # gpg: Signature made Thu May 28 09:37:27 2015 BST using RSA key ID C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" * remotes/cohuck/tags/s390x-20150528: s390x: Enable vector processing capability s390x: Migrate vector registers s390x: Add vector registers to ELF dump linux/elf.h update s390x: Add vector registers to HMP output s390x: gdb updates for vector registers gdb-xml: Include XML for s390 vector registers s390x: Store Additional Status SIGP order s390x: Vector Register IOCTLs s390x: Common access to floating point registers Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-28Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into ↵Peter Maydell19-239/+331
staging # gpg: Signature made Wed May 27 11:02:55 2015 BST using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/net-pull-request: net/net: Record usage status of mac address tap: Improve -netdev/netdev_add/-net/... tap error reporting tap: Finish conversion of tap_open() to Error tap-solaris: Convert tap_open() to Error tap-bsd: Convert tap_open() to Error tap-linux: Convert tap_open() to Error tap: Permit incremental conversion of tap_open() to Error tap: Convert launch_script() to Error tap: Convert net_init_tap_one() to Error tap: Convert tap_set_sndbuf() to Error tap: Improve -netdev/netdev_add/-net/... bridge error reporting tap: net_tap_fd_init() can't fail, drop dead error handling net/dump: Improve -net/host_net_add dump error reporting net: Improve -net nic error reporting net: Permit incremental conversion of init functions to Error net: Improve error message for -net hubport a bit net: Change help text to list -netdev instead of -net by default Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2015-05-27s390x: Enable vector processing capabilityEric Farman1-0/+1
Everything is finally in place, inform the kernel that user space supports vector registers. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: Migrate vector registersEric Farman2-0/+75
When migrating a guest, be sure to include the vector registers. The vector registers are defined in a subsection, similar to the existing subsection for floating point registers. Since the floating point registers are always present (and thus migrated), we can skip them when performing the migration of the vector registers which may or may not be present. Suggested-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: Add vector registers to ELF dumpEric Farman1-0/+39
Create ELF notes for the vector registers where applicable, so that their contents can be examined by utilities such as crash or readelf. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27linux/elf.h updateEric Farman1-0/+2
Sync with kernel elf.h updates to get s390x vector register definitions. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: Add vector registers to HMP outputEric Farman1-0/+6
There are mechanisms to dump registers via the qemu HMP interface, such as the "info registers" command. Expand this output to dump the new vector registers. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: gdb updates for vector registersEric Farman2-1/+47
gdb allows registers to be displayed/modified, and is being updated to account for the new vector registers. Mirror these changes in the gdb stub in qemu so that this can be performed when gdb is attached to the qemu gdbserver. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27gdb-xml: Include XML for s390 vector registersEric Farman1-0/+59
Include the vector registers XML file that is provided by gdb, and can be used by the qemu gdbserver interface. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: Store Additional Status SIGP orderEric Farman2-0/+56
Add handling for the Store Additional Status at Address order that exists for the Signal Processor (SIGP) instruction. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: Vector Register IOCTLsEric Farman4-35/+56
Handle the actual syncing of the vector registers with kernel space, via the get/put register IOCTLs. The vector registers that were introduced with the z13 overlay the existing floating point registers. FP registers 0-15 are the high-halves of vector registers 0-15. Thus, remove the freg fields and replace them with the equivalent vector field to avoid errors in duplication. Moreover, synchronize either the vector registers via kvm_sync_regs, or floating point registers via the GET/SET FPU IOCTLs. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
2015-05-27s390x: Common access to floating point registersEric Farman7-10/+19
Provide a routine to access the correct floating point register, to simplify future expansion. Suggested-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
generated by cgit v1.1 at 2025-01-09 18:39:19 +0000