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2019-09-17
riscv: sifive_u: Fix broken GEM support
Bin Meng
3
-5
/
+23
2019-09-17
riscv: sifive_u: Instantiate OTP memory with a serial number
Bin Meng
2
-0
/
+12
2019-09-17
riscv: sifive: Implement a model for SiFive FU540 OTP
Bin Meng
3
-0
/
+272
2019-09-17
riscv: roms: Update default bios for sifive_u machine
Bin Meng
2
-2
/
+2
2019-09-17
riscv: sifive_u: Change UART node name in device tree
Bin Meng
1
-1
/
+1
2019-09-17
riscv: sifive_u: Update UART base addresses and IRQs
Bin Meng
2
-4
/
+4
2019-09-17
riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes
Bin Meng
2
-3
/
+14
2019-09-17
riscv: sifive_u: Add PRCI block to the SoC
Bin Meng
2
-1
/
+26
2019-09-17
riscv: sifive_u: Generate hfclk and rtcclk nodes
Bin Meng
2
-0
/
+25
2019-09-17
riscv: sifive: Implement PRCI model for FU540
Bin Meng
3
-0
/
+251
2019-09-17
riscv: sifive_u: Update PLIC hart topology configuration string
Bin Meng
1
-3
/
+4
2019-09-17
riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC
Bin Meng
2
-26
/
+72
2019-09-17
riscv: sifive_u: Set the minimum number of cpus to 2
Bin Meng
2
-1
/
+6
2019-09-17
riscv: hart: Add a "hartid-base" property to RISC-V hart array
Bin Meng
2
-1
/
+3
2019-09-17
riscv: hart: Extract hart realize to a separate routine
Bin Meng
1
-13
/
+20
2019-09-17
riscv: Add a sifive_cpu.h to include both E and U cpu type defines
Bin Meng
3
-12
/
+33
2019-09-17
riscv: sifive_e: Drop sifive_mmio_emulate()
Bin Meng
2
-15
/
+9
2019-09-17
riscv: sifive_e: prci: Update the PRCI register block size
Bin Meng
2
-1
/
+3
2019-09-17
riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming
Bin Meng
1
-1
/
+1
2019-09-17
riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}
Bin Meng
5
-114
/
+111
2019-09-17
riscv: sifive_u: Remove the unnecessary include of prci header
Bin Meng
1
-1
/
+0
2019-09-17
riscv: roms: Remove executable attribute of opensbi images
Bin Meng
3
-0
/
+0
2019-09-17
riscv: hw: Remove the unnecessary include of target/riscv/cpu.h
Bin Meng
3
-3
/
+0
2019-09-17
riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead
Bin Meng
3
-9
/
+13
2019-09-17
riscv: hw: Change create_fdt() to return void
Bin Meng
2
-14
/
+8
2019-09-17
riscv: hw: Remove not needed PLIC properties in device tree
Bin Meng
2
-4
/
+0
2019-09-17
riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell
Bin Meng
2
-21
/
+21
2019-09-17
riscv: hw: Remove superfluous "linux, phandle" property
Bin Meng
3
-8
/
+0
2019-09-17
riscv: hw: Remove duplicated "hw/hw.h" inclusion
Bin Meng
2
-2
/
+0
2019-09-17
riscv: sifive_test: Add reset functionality
Bin Meng
2
-1
/
+6
2019-09-17
riscv: hmp: Add a command to show virtual memory mappings
Bin Meng
3
-1
/
+234
2019-09-17
riscv: Resolve full path of the given bios image
Bin Meng
1
-3
/
+3
2019-09-17
riscv: Add a helper routine for finding firmware
Bin Meng
2
-7
/
+16
2019-09-17
riscv: rv32: Root page table address can be larger than 32-bit
Bin Meng
1
-5
/
+5
2019-09-17
target/riscv: Update the Hypervisor CSRs to v0.4
Alistair Francis
1
-17
/
+18
2019-09-17
target/riscv: Create function to test if FP is enabled
Alistair Francis
3
-10
/
+26
2019-09-17
riscv: plic: Remove unused interrupt functions
Alistair Francis
2
-15
/
+0
2019-09-17
target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events
Philippe Mathieu-Daudé
2
-21
/
+16
2019-09-17
target/riscv/pmp: Restrict priviledged PMP to system-mode emulation
Philippe Mathieu-Daudé
2
-5
/
+2
2019-09-17
riscv: sifive_u: Fix clock-names property for ethernet node
Guenter Roeck
1
-1
/
+1
2019-09-17
riscv: sivive_u: Add dummy serial clock and aliases entry for uart
Guenter Roeck
1
-2
/
+17
2019-09-17
riscv: sifive_u: Add support for loading initrd
Guenter Roeck
1
-3
/
+17
2019-09-17
target/sparc: Switch to do_transaction_failed() hook
Peter Maydell
3
-8
/
+18
2019-09-17
target/sparc: Remove unused ldl_phys from dump_mmu()
Peter Maydell
1
-3
/
+1
2019-09-17
target/sparc: Handle bus errors in mmu_probe()
Peter Maydell
1
-4
/
+25
2019-09-17
target/sparc: Correctly handle bus errors in page table walks
Peter Maydell
1
-4
/
+20
2019-09-17
target/sparc: Check for transaction failures in MXCC stream ASI accesses
Peter Maydell
1
-20
/
+37
2019-09-17
target/sparc: Check for transaction failures in MMU passthrough ASIs
Peter Maydell
1
-16
/
+33
2019-09-17
target/sparc: Factor out the body of sparc_cpu_unassigned_access()
Peter Maydell
1
-95
/
+106
2019-09-17
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell
28
-380
/
+456
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