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2017-10-15pci: Add INTERFACE_PCIE_DEVICE to all PCIe devicesEduardo Habkost8-0/+31
Change all devices that set is_express=1 to implement INTERFACE_PCIE_DEVICE. Cc: Keith Busch <keith.busch@intel.com> Cc: Kevin Wolf <kwolf@redhat.com> Cc: Max Reitz <mreitz@redhat.com> Cc: Dmitry Fleytman <dmitry@daynix.com> Cc: Jason Wang <jasowang@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Cc: Paul Burton <paul.burton@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Hannes Reinecke <hare@suse.com> Cc: qemu-block@nongnu.org Reviewed-by: Alistair Francis <alistair.francis@xilinx.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: Add interface names to hybrid PCI devicesEduardo Habkost5-0/+22
The following devices support both PCI Express and Conventional PCI, by including special code to handle the QEMU_PCI_CAP_EXPRESS flag and/or conditional pcie_endpoint_cap_init() calls: * vfio-pci (is_express=1, but legacy PCI handled by vfio_populate_device()) * vmxnet3 (is_express=0, but PCIe handled by vmxnet3_realize()) * pvscsi (is_express=0, but PCIe handled by pvscsi_realize()) * virtio-pci (is_express=0, but PCIe handled by virtio_pci_dc_realize(), and additional legacy PCI code at virtio_pci_realize()) * base-xhci (is_express=1, but pcie_endpoint_cap_init() call is conditional on pci_bus_is_express(dev->bus) * Note that xhci does not clear QEMU_PCI_CAP_EXPRESS like the other hybrid devices Cc: Dmitry Fleytman <dmitry@daynix.com> Cc: Jason Wang <jasowang@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Alex Williamson <alex.williamson@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: conventional-pci-device and pci-express-device interfacesEduardo Habkost2-0/+18
Those two interfaces will be used to indicate which device types support Conventional PCI or PCI Express buses. Management software will be able to use the qom-list-types QMP command to query that information. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15PCI: PCIe access should always be little endianMatt Redfearn1-1/+1
PCIe busses are always little endian, so set the endianness of the memory region to little endian rather than native such that operations work as expected on big endian targets. Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15virtio/pci/migration: Convert to VMStateDr. David Alan Gilbert1-81/+27
Convert the 'modern_state' part of virtio-pci to modern migration macros. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15hw/pci-bridge/pcie_pci_bridge: properly handle MSI unavailability caseAleksandr Bezzubikov1-6/+18
QEMU with the pcie-pci-bridge device crashes if the guest board doesn't support MSI, e.g. 'qemu-system-ppc64 -M prep -device pcie-pci-bridge'. This is caused by wrong pcie-pci-bridge instantiation error handling. This patch fixes this issue by falling back to legacy INTx if MSI is not available. Also set the bridge's 'msi' property default value to 'auto' in order to trigger errors only when user explicitly set msi=on. Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Aleksandr Bezzubikov <zuban32s@gmail.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: allow 32-bit PCI IO accesses to pass through the PCI bridgeMark Cave-Ayland1-1/+2
Whilst the underlying PCI bridge implementation supports 32-bit PCI IO accesses, unfortunately they are truncated at the legacy 64K limit. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15virtio/vhost: reset dev->log after syncingFelipe Franciosi1-2/+3
vhost_log_put() is called to decomission the dirty log between qemu and a vhost device when stopping the device. Such a call can happen from migration_completion(). Present code sets dev->log_size to zero too early in vhost_log_put(), causing the sync check to always return false. As a consequence, the last pass on the dirty bitmap never happens at the end of migration. If a vhost device was busy (writing to guest memory) until the last moments before vhost_virtqueue_stop(), this error will result in guest memory corruption (at least) following migrations. Signed-off-by: Felipe Franciosi <felipe@nutanix.com> Acked-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15MAINTAINERS: add Dump maintainersMarc-André Lureau1-0/+11
Proposing myself, since I have some familiarity with the code now. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Acked-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15scripts/dump-guest-memory.py: add vmcoreinfoMarc-André Lureau1-0/+61
Add a vmcoreinfo ELF note in the dump if vmcoreinfo device has the memory location details. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15kdump: set vmcoreinfo locationMarc-André Lureau1-0/+24
kdump header provides offset and size of the vmcoreinfo content, append it if available (skip the ELF note header). crash-7.1.9 was the first version that started looking in the vmcoreinfo data for phys_base instead of in the kdump_sub_header. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15dump: update phys_base header field based on VMCOREINFO contentMarc-André Lureau2-2/+62
If the guest note is VMCOREINFO, try to get phys_base from it. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15dump: add guest ELF noteMarc-André Lureau2-0/+109
Read the guest ELF PT_NOTE from guest memory when fw_cfg etc/vmcoreinfo entry provides the location, and write it as an additional note in the dump. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15hw/misc: add vmcoreinfo deviceMarc-André Lureau4-0/+184
See docs/specs/vmcoreinfo.txt for details. "etc/vmcoreinfo" fw_cfg entry is added when using "-device vmcoreinfo". Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15fw_cfg: add write callbackMarc-André Lureau6-9/+18
Reintroduce the write callback that was removed when write support was removed in commit 023e3148567ac898c7258138f8e86c3c2bb40d07. Contrary to the previous callback implementation, the write_cb callback is called whenever a write happened, so handlers must be ready to handle partial write as necessary. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15pci: Set err to errp directly rather than through error_propagate()Mao Zhongyi1-3/+1
ioh3420_interrupts_init() pass error message to local_err, then propagate it to errp by error_propagate(), which is not necessary. So eliminate it and pass errp directly instead of local_err. Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Marcel Apfelbaum <marcel@redhat.com> Signed-off-by: Mao Zhongyi <maozy.fnst@cn.fujitsu.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-15xio3130_downstream: Report error if pcie_chassis_add_slot() failedEduardo Habkost1-0/+1
On commit f8cd1b02 ("pci: Convert to realize"), no error_set*() call was added for the pcie_chassis_add_slot() error case. pcie_chassis_add_slot() errors get ignored, making QEMU crash later. e.g.: $ qemu-system-x86_64 -device ioh3420 -device xio3130-downstream qemu-system-x86_64: memory.c:2166: memory_region_del_subregion: Assertion `subregion->container == mr' failed. Aborted (core dumped) Fix it by reporting the error using error_setg(). Fixes: f8cd1b0201c41d88bb97dcafb80348a0e88d8805 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Marcel Apfelbaum <marcel@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2017-10-12Merge remote-tracking branch ↵Peter Maydell7-115/+521
'remotes/pmaydell/tags/pull-target-arm-20171012' into staging target-arm queue: * v8M: SG, BLXNS, secure-return * v8M: fixes for coverity issues in previous patches * arm: fix armv7m_init() declaration to match definition * watchdog/aspeed: fix variable type to store reload value # gpg: Signature made Thu 12 Oct 2017 17:02:49 BST # gpg: using RSA key 0x3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20171012: nvic: Fix miscalculation of offsets into ITNS array nvic: Add missing 'break' target/arm: Implement SG instruction corner cases target/arm: Support some Thumb insns being always unconditional target-arm: Simplify insn_crosses_page() target/arm: Pull Thumb insn word loads up to top level target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1 target/arm: Implement secure function return target/arm: Implement BLXNS target/arm: Implement SG instruction target/arm: Add M profile secure MMU index values to get_a32_user_mem_index() arm: fix armv7m_init() declaration to match definition watchdog/aspeed: fix variable type to store reload value Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-12nvic: Fix miscalculation of offsets into ITNS arrayPeter Maydell1-2/+2
This calculation of the first exception vector in the ITNS<n> register being accessed: int startvec = 32 * (offset - 0x380) + NVIC_FIRST_IRQ; is incorrect, because offset is in bytes, so we only want to multiply by 8. Spotted by Coverity (CID 1381484, CID 1381488), though it is not correct that it actually overflows the buffer, because we have a 'startvec + i < s->num_irq' guard. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507650856-11718-1-git-send-email-peter.maydell@linaro.org
2017-10-12nvic: Add missing 'break'Peter Maydell1-0/+1
Coverity points out that we forgot the 'break' for the SAU_CTRL write case (CID1381683). This has no actual visible consequences because it happens that the following case is effectively a no-op. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1507742676-9908-1-git-send-email-peter.maydell@linaro.org Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2017-10-12target/arm: Implement SG instruction corner casesPeter Maydell1-1/+22
The common situation of the SG instruction is that it is executed from S&NSC memory by a CPU in NS state. That case is handled by v7m_handle_execute_nsc(). However the instruction also has defined behaviour in a couple of other cases: * SG instruction in NS memory (behaves as a NOP) * SG in S memory but CPU already secure (clears IT bits and does nothing else) * SG instruction in v8M without Security Extension (NOP) These can be implemented in translate.c. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-10-git-send-email-peter.maydell@linaro.org
2017-10-12target/arm: Support some Thumb insns being always unconditionalPeter Maydell1-1/+47
A few Thumb instructions are always unconditional even inside an IT block (as opposed to being UNPREDICTABLE if used inside an IT block): BKPT, the v8M SG instruction, and the A profile HLT (debug halt) instruction. This means we need to suppress the jump-over-instruction-on-condfail code generation (though the IT state still advances as usual and subsequent insns in the IT block may be conditional). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-9-git-send-email-peter.maydell@linaro.org
2017-10-12target-arm: Simplify insn_crosses_page()Peter Maydell1-21/+6
Recent changes have left insn_crosses_page() more complicated than it needed to be: * it's only called from thumb_tr_translate_insn() so we know for certain that we're looking at a Thumb insn * the caller's check for dc->pc >= dc->next_page_start - 3 means that dc->pc can't possibly be 4 aligned, so there's no need to check that (the check was partly there to ensure that we didn't treat an ARM insn as Thumb, I think) * we now have thumb_insn_is_16bit() which lets us do a precise check of the length of the next insn, rather than opencoding an inaccurate check Simplify it down to just loading the first half of the insn and calling thumb_insn_is_16bit() on it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-8-git-send-email-peter.maydell@linaro.org
2017-10-12target/arm: Pull Thumb insn word loads up to top levelPeter Maydell1-70/+108
Refactor the Thumb decode to do the loads of the instruction words at the top level rather than only loading the second half of a 32-bit Thumb insn in the middle of the decode. This is simple apart from the awkward case of Thumb1, where the BL/BLX prefix and suffix instructions live in what in Thumb2 is the 32-bit insn space. To handle these we decode enough to identify whether we're looking at a prefix/suffix that we handle as a 16 bit insn, or a prefix that we're going to merge with the following suffix to consider as a 32 bit insn. The translation of the 16 bit cases then moves from disas_thumb2_insn() to disas_thumb_insn(). The refactoring has the benefit that we don't need to pass the CPUARMState* down into the decoder code any more, but the major reason for doing this is that some Thumb instructions must be always unconditional regardless of the IT state bits, so we need to know the whole insn before we emit the "skip this insn if the IT bits and cond state tell us to" code. (The always unconditional insns are BKPT, HLT and SG; the last of these is 32 bits.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-7-git-send-email-peter.maydell@linaro.org
2017-10-12target-arm: Don't check for "Thumb2 or M profile" for not-Thumb1Peter Maydell1-2/+1
The code which implements the Thumb1 split BL/BLX instructions is guarded by a check on "not M or THUMB2". All we really need to check here is "not THUMB2" (and we assume that elsewhere too, eg in the ARCH(6T2) test that UNDEFs the Thumb2 insns). This doesn't change behaviour because all M profile cores have Thumb2 and so ARM_FEATURE_M implies ARM_FEATURE_THUMB2. (v6M implements a very restricted subset of Thumb2, but we can cross that bridge when we get to it with appropriate feature bits.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-6-git-send-email-peter.maydell@linaro.org
2017-10-12target/arm: Implement secure function returnPeter Maydell3-10/+126
Secure function return happens when a non-secure function has been called using BLXNS and so has a particular magic LR value (either 0xfefffffe or 0xfeffffff). The function return via BX behaves specially when the new PC value is this magic value, in the same way that exception returns are handled. Adjust our BX excret guards so that they recognize the function return magic number as well, and perform the function-return unstacking in do_v7m_exception_exit(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-5-git-send-email-peter.maydell@linaro.org
2017-10-12target/arm: Implement BLXNSPeter Maydell4-2/+76
Implement the BLXNS instruction, which allows secure code to call non-secure code. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-4-git-send-email-peter.maydell@linaro.org
2017-10-12target/arm: Implement SG instructionPeter Maydell1-5/+127
Implement the SG instruction, which we emulate 'by hand' in the exception handling code path. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-3-git-send-email-peter.maydell@linaro.org
2017-10-12target/arm: Add M profile secure MMU index values to get_a32_user_mem_index()Peter Maydell1-0/+4
Add the M profile secure MMU index values to the switch in get_a32_user_mem_index() so that LDRT/STRT work correctly rather than asserting at translate time. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 1507556919-24992-2-git-send-email-peter.maydell@linaro.org
2017-10-12arm: fix armv7m_init() declaration to match definitionIgor Mammedov1-1/+1
s/cpu_model/cpu_type/ that has been forgotten during conversion (ba1ba5cc), while touching the line also fixup alignment. Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-id: 1507710805-221721-1-git-send-email-imammedo@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-12watchdog/aspeed: fix variable type to store reload valueCédric Le Goater1-2/+2
Initially from Anton D. Kachalov" <mouse@yandex-team.ru> but the SoB was missing. Signed-off-by: Cédric Le Goater <clg@kaod.org> Acked-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20170920064915.30027-1-clg@kaod.org [clg: change commit log and subject replace UL suffix by ULL ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-12Merge remote-tracking branch ↵Peter Maydell6-23/+30
'remotes/ehabkost/tags/python-next-pull-request' into staging Python queue, 2017-10-11 # gpg: Signature made Wed 11 Oct 2017 19:49:40 BST # gpg: using RSA key 0x2807936F984DC5A6 # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/python-next-pull-request: scripts: Remove debug parameter from QEMUMachine scripts: Remove debug parameter from QEMUMonitorProtocol guestperf: Configure logging on all shell frontends basevm: Call logging.basicConfig() iotests: Set up Python logging Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-11scripts: Remove debug parameter from QEMUMachineEduardo Habkost3-10/+4
All scripts that use the QEMUMachine and QEMUQtestMachine classes (device-crash-test, tests/migration/*, iotests.py, basevm.py) already configure logging. The basicConfig() call inside QEMUMachine.__init__() is being kept just to make sure a script would still work if it didn't configure logging. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20171005172013.3098-4-ehabkost@redhat.com> Reviewed-by: Lukáš Doktor <ldoktor@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-11scripts: Remove debug parameter from QEMUMonitorProtocolEduardo Habkost2-11/+8
Use logging module for the QMP debug messages. The only scripts that set debug=True are iotests.py and guestperf/engine.py, and they already call logging.basicConfig() to set up logging. Scripts that don't configure logging are safe as long as they don't need debugging output, because debug messages don't trigger the "No handlers could be found for logger" message from the Python logging module. Scripts that already configure logging but don't use debug=True (e.g. scripts/vm/basevm.py) will get QMP debugging enabled for free. Cc: "Alex Bennée" <alex.bennee@linaro.org> Cc: Fam Zheng <famz@redhat.com> Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20171005172013.3098-3-ehabkost@redhat.com> Reviewed-by: Lukáš Doktor <ldoktor@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-11guestperf: Configure logging on all shell frontendsEduardo Habkost1-0/+13
The logging module will eventually replace the 'debug' parameter in QEMUMachine and QEMUMonitorProtocol. Cc: Daniel P. Berrange <berrange@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20171005172013.3098-2-ehabkost@redhat.com> Reviewed-by: Lukáš Doktor <ldoktor@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-11basevm: Call logging.basicConfig()Eduardo Habkost1-2/+2
Just setting level=DEBUG when debug is enabled is not enough: we need to set up a log handler if we want debug messages generated using logging.getLogger(...).debug() to be printed. This was not a problem before because logging.debug() calls logging.basicConfig() implicitly, but it's safer to not rely on that. Cc: "Alex Bennée" <alex.bennee@linaro.org> Cc: Fam Zheng <famz@redhat.com> Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170927130339.21444-4-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Lukáš Doktor <ldoktor@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-11iotests: Set up Python loggingEduardo Habkost1-0/+3
Set up Python logging module instead of relying on QEMUMachine._debug to enable debugging messages. Cc: Kevin Wolf <kwolf@redhat.com> Cc: Max Reitz <mreitz@redhat.com> Cc: qemu-block@nongnu.org Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <20170927130339.21444-3-ehabkost@redhat.com> Reviewed-by: Daniel P. Berrange <berrange@redhat.com> Reviewed-by: Lukáš Doktor <ldoktor@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2017-10-11Merge remote-tracking branch 'remotes/elmarco/tags/vus-pull-request' into ↵Peter Maydell10-547/+315
staging # gpg: Signature made Tue 10 Oct 2017 22:33:56 BST # gpg: using RSA key 0xDAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/vus-pull-request: (27 commits) vhost-user-scsi: remove server_sock from VusDev vhost-user-scsi: use libvhost-user glib helper libvhost-user: add glib source helper vhost-user-scsi: use glib logging vhost-user-scsi: simplify source handling vhost-user-scsi: drop extra callback pointer vhost-user-scsi: don't copy iscsi/scsi-lowlevel.h vhost-user-scsi: avoid use of iscsi_ namespace vhost-user-scsi: rename VUS types vhost-user-scsi: remove unimplemented functions vhost-user-scsi: remove VUS_MAX_LUNS vhost-user-scsi: remove vdev_scsi_add_iscsi_lun() vhost-user-scsi: assert() in iscsi_add_lun() vhost-user-scsi: use NULL pointer vhost-user-scsi: simplify unix path cleanup vhost-user-scsi: remove vdev_scsi_find_by_vu() vhost-user-scsi: also free the gtree vhost-user-scsi: glib calls that allocate don't return NULL vhost-user-scsi: use glib allocation vhost-user-scsi: code style fixes ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-11Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20171010' into stagingPeter Maydell29-434/+521
Queued TCG patches # gpg: Signature made Tue 10 Oct 2017 20:23:12 BST # gpg: using RSA key 0x64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20171010: tcg/mips: delete commented out extern keyword. tcg: define TCG_HIGHWATER util: move qemu_real_host_page_size/mask to osdep.h tcg: take .helpers out of TCGContext tci: move tci_regs to tcg_qemu_tb_exec's stack exec-all: extract tb->tc_* into a separate struct tc_tb translate-all: define and use DEBUG_TB_CHECK_GATE translate-all: define and use DEBUG_TB_INVALIDATE_GATE exec-all: introduce TB_PAGE_ADDR_FMT translate-all: define and use DEBUG_TB_FLUSH_GATE exec-all: bring tb->invalid into tb->cflags tcg: consolidate TB lookups in tb_lookup__cpu_state tcg: remove addr argument from lookup_tb_ptr tcg/mips: constify tcg_target_callee_save_regs tcg/i386: constify tcg_target_callee_save_regs cpu-exec: rename have_tb_lock to acquired_tb_lock in tb_find translate-all: make have_tb_lock static exec-all: fix typos in TranslationBlock's documentation tcg: fix corruption of code_time profiling counter upon tb_flush cputlb: bring back tlb_flush_count under !TLB_DEBUG Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-10-10vhost-user-scsi: remove server_sock from VusDevMarc-André Lureau1-53/+24
It is unneeded in the VusDev device structure, and also simplify a bit the code. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-10vhost-user-scsi: use libvhost-user glib helperMarc-André Lureau1-146/+16
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-10libvhost-user: add glib source helperMarc-André Lureau3-1/+187
This file implements a bridge from the vu_init API of libvhost-user to GSource, so that libvhost-user can be used inside a GLib main loop. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-10vhost-user-scsi: use glib loggingMarc-André Lureau1-56/+21
- PLOG is unused - code is compiled out unless debug is enabled - logging is too verbose - you can pipe to ts to have timestamp if needed, or use structured logging with more recent glib Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-10vhost-user-scsi: simplify source handlingMarc-André Lureau1-33/+12
Using a hashtable. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-10vhost-user-scsi: drop extra callback pointerMarc-André Lureau1-9/+3
Use the one from the source with casting, like any other glib source. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-10vhost-user-scsi: don't copy iscsi/scsi-lowlevel.hMarc-André Lureau1-87/+9
There is no need to include hw/virtio/virtio-scsi.h, then the conflict with SCSI_XFER enum goes away. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-10vhost-user-scsi: avoid use of iscsi_ namespaceMarc-André Lureau1-2/+2
It is confusing and could easily conflict with future versions. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-10vhost-user-scsi: rename VUS typesMarc-André Lureau1-23/+23
- use Vus prefix consistently - use CamelCase, since that's glib & libvhost-user style - avoid _t postfix, usually for system headers Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2017-10-10vhost-user-scsi: remove unimplemented functionsMarc-André Lureau1-18/+3
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2017-10-10vhost-user-scsi: remove VUS_MAX_LUNSMarc-André Lureau1-5/+3
There is no code to support more than 1 yet, no need for that today. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
generated by cgit v1.1 at 2024-12-29 06:44:02 +0000