index
:
riscv-gnu-toolchain/qemu.git
block
master
stable-0.10
stable-0.11
stable-0.12
stable-0.13
stable-0.14
stable-0.15
stable-1.0
stable-1.1
stable-1.2
stable-1.3
stable-1.4
stable-1.5
stable-1.6
stable-1.7
stable-2.0
stable-2.1
stable-2.10
stable-2.11
stable-2.12
stable-2.2
stable-2.3
stable-2.4
stable-2.5
stable-2.6
stable-2.7
stable-2.8
stable-2.9
stable-3.0
stable-3.1
stable-4.0
stable-4.1
stable-4.2
stable-5.0
stable-6.0
stable-6.1
stable-7.2
stable-8.0
stable-8.1
stable-8.2
stable-9.0
stable-9.1
stable-9.2
staging
staging-7.2
staging-8.0
staging-8.1
staging-8.2
staging-9.0
staging-9.1
staging-9.2
Unnamed repository; edit this file 'description' to name the repository.
root
about
summary
refs
log
tree
commit
diff
log msg
author
committer
range
Age
Commit message (
Expand
)
Author
Files
Lines
2021-05-11
hw/opentitan: Update the interrupt layout
Alistair Francis
3
-22
/
+22
2021-05-11
MAINTAINERS: Update the RISC-V CPU Maintainers
Alistair Francis
1
-3
/
+2
2021-05-11
target/riscv: Use RISCVException enum for CSR access
Alistair Francis
4
-36
/
+38
2021-05-11
target/riscv: Use the RISCVException enum for CSR operations
Alistair Francis
2
-261
/
+382
2021-05-11
target/riscv: Fix 32-bit HS mode access permissions
Alistair Francis
1
-1
/
+5
2021-05-11
target/riscv: Use the RISCVException enum for CSR predicates
Alistair Francis
2
-37
/
+46
2021-05-11
target/riscv: Convert the RISC-V exceptions to an enum
Alistair Francis
3
-24
/
+26
2021-05-11
hw/riscv: Connect Shakti UART to Shakti platform
Vijai Kumar K
2
-0
/
+10
2021-05-11
hw/char: Add Shakti UART emulation
Vijai Kumar K
5
-0
/
+266
2021-05-11
riscv: Add initial support for Shakti C machine
Vijai Kumar K
6
-0
/
+265
2021-05-11
target/riscv: Add Shakti C class CPU
Vijai Kumar K
2
-0
/
+2
2021-05-11
hw/riscv: sifive_e: Add 'const' to sifive_e_memmap[]
Bin Meng
1
-1
/
+1
2021-05-11
target/riscv: Align the data type of reset vector address
Dylan Jhong
1
-1
/
+1
2021-05-11
docs/system/generic-loader.rst: Fix style
Axel Heider
1
-3
/
+6
2021-05-11
target/riscv: Remove privilege v1.9 specific CSR related code
Atish Patra
7
-72
/
+23
2021-05-11
main-loop: remove dead code
Paolo Bonzini
2
-79
/
+0
2021-05-11
target/i386: use mmu_translate for NPT walk
Paolo Bonzini
1
-207
/
+36
2021-05-11
target/i386: allow customizing the next phase of the translation
Paolo Bonzini
1
-12
/
+18
2021-05-11
target/i386: extend pg_mode to more CR0 and CR4 bits
Paolo Bonzini
3
-16
/
+39
2021-05-11
target/i386: pass cr3 to mmu_translate
Paolo Bonzini
1
-6
/
+6
2021-05-11
target/i386: extract mmu_translate
Paolo Bonzini
1
-65
/
+86
2021-05-11
target/i386: move paging mode constants from SVM to cpu.h
Paolo Bonzini
4
-21
/
+31
2021-05-11
target/i386: merge SVM_NPTEXIT_* with PF_ERROR_* constants
Paolo Bonzini
2
-10
/
+5
2021-05-10
accel: add init_accel_cpu for adapting accel behavior to CPU type
Claudio Fontana
3
-1
/
+26
2021-05-10
accel: move call to accel_init_interfaces
Claudio Fontana
4
-3
/
+3
2021-05-10
i386: make cpu_load_efer sysemu-only
Claudio Fontana
2
-15
/
+18
2021-05-10
target/i386: gdbstub: only write CR0/CR2/CR3/EFER for sysemu
Claudio Fontana
1
-0
/
+10
2021-05-10
target/i386: gdbstub: introduce aux functions to read/write CS64 regs
Claudio Fontana
1
-104
/
+51
2021-05-10
i386: split off sysemu part of cpu.c
Claudio Fontana
4
-379
/
+429
2021-05-10
i386: split seg_helper into user-only and sysemu parts
Claudio Fontana
7
-229
/
+311
2021-05-10
i386: split svm_helper into sysemu and stub-only user
Claudio Fontana
5
-61
/
+80
2021-05-10
i386: separate fpu_helper sysemu-only parts
Claudio Fontana
4
-39
/
+63
2021-05-10
i386: split misc helper user stubs and sysemu part
Claudio Fontana
5
-467
/
+519
2021-05-10
i386: move TCG bpt_helper into sysemu/
Claudio Fontana
6
-277
/
+311
2021-05-10
i386: split tcg excp_helper into sysemu and user parts
Claudio Fontana
5
-573
/
+623
2021-05-10
i386: split smm helper (sysemu)
Claudio Fontana
6
-18
/
+16
2021-05-10
i386: split off sysemu-only functionality in tcg-cpu
Paolo Bonzini
7
-71
/
+121
2021-05-10
accel-cpu: make cpu_realizefn return a bool
Claudio Fontana
8
-14
/
+18
2021-05-10
target/i386: fix host_cpu_adjust_phys_bits error handling
Claudio Fontana
1
-10
/
+12
2021-05-10
accel: introduce new accessor functions
Claudio Fontana
4
-12
/
+35
2021-05-10
cpu: call AccelCPUClass::cpu_realizefn in cpu_exec_realizefn
Claudio Fontana
2
-13
/
+13
2021-05-10
i386: split cpu accelerators from cpu.c, using AccelCPUClass
Claudio Fontana
15
-379
/
+652
2021-05-10
target/i386: Split out do_fsave, do_frstor, do_fxsave, do_fxrstor
Richard Henderson
1
-16
/
+34
2021-05-10
target/i386: Rename helper_fldt, helper_fstt
Richard Henderson
1
-10
/
+9
2021-05-10
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20210505-pull-request' ...
Peter Maydell
10
-14
/
+40
2021-05-10
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210510-...
Peter Maydell
27
-413
/
+720
2021-05-10
hw/arm/xlnx: Fix PHY address for xilinx-zynq-a9
Guenter Roeck
1
-1
/
+1
2021-05-10
hw/arm/mps2-tz: Implement AN524 memory remapping via machine property
Peter Maydell
2
-1
/
+117
2021-05-10
hw/misc/mps2-scc: Support using CFG0 bit 0 for remapping
Peter Maydell
2
-3
/
+19
2021-05-10
hw/misc/mps2-scc: Add "QEMU interface" comment
Peter Maydell
1
-0
/
+12
[prev]
[next]