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2019-09-20ipmi: Fix SSIF ACPI handling to use the right CRSCorey Minyard4-9/+10
Pass in the CRS so that it can be set to the SMBus for IPMI later. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20acpi: Add i2c serial bus CRS handlingCorey Minyard2-0/+58
This will be required for getting IPMI SSIF (SMBus interface) into the ACPI tables. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20ipmi: Add an SMBus IPMI interfaceCorey Minyard5-0/+392
Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20ipmi: Add PCI IPMI interfacesCorey Minyard7-0/+309
Pretty straightforward, just hook the current KCS and BT code into the PCI system with the proper configuration. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20smbios:ipmi: Ignore IPMI devices with no fwinfo functionCorey Minyard1-0/+3
Not all devices have fwinfo (like the coming PCI one), so ignore them if the their fwinfo function is NULL. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20ipmi: Allow a size value to be passed for I/O spaceCorey Minyard7-11/+44
PCI device I/O must be >= 8 bytes in length or they don't work. Allow the size to be passed in, the default size of 2 or 3 won't work. Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20ipmi: Split out BT-specific code from ISA BT codeCorey Minyard4-421/+520
Get ready for PCI and other BT interfaces. No functional changes, just split the code into generic BT code and ISA-specific BT code. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-20ipmi: Split out KCS-specific code from ISA KCS codeCorey Minyard4-397/+505
Get ready for PCI and other KCS interfaces. No functional changes, just split the code into the generic KCS code and the ISA-specific code. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-09-20ipmi: Add a UUID device propertyCorey Minyard2-11/+21
Using the UUID that qemu generates probably isn't the best thing to do, allow it to be passed in via properties, and use QemuUUID for the type. If the UUID is not set, return an unsupported command error. This way we are not providing an all-zero (or randomly generated) GUID to the IPMI user. This lets the host fall back to the other method of using the get device id command to determind the BMC being accessed. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Cédric Le Goater <clg@kaod.org> Cc: David Gibson <david@gibson.dropbear.id.au> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com>
2019-09-20qdev: Add a no default uuid propertyCorey Minyard1-0/+7
This is for IPMI, which will behave differently if the UUID is not set. Signed-off-by: Corey Minyard <cminyard@mvista.com> Cc: Fam Zheng <famz@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
2019-09-20tests:ipmi: Fix IPMI BT testsCorey Minyard2-4/+5
The IPMI BT tests had a race condition, if it receive an IPMI command to enable interrupt, it would write the message to enable interrupts after it wrote the command response. So the test code could receive the command response and issue the next command before the device handled the interrupt enable command, and thus no interrupt. So send the message to enable interrupt before the command response. Also add some sleeps to give qemu time to handle responses, there was no delay before, and it could result in an invalid timeout. And re-enable the tests, as hopefully they are fixed now. Note that I was unable to reproduce this even with the instructions Peter gave me, but hopefully this fixes the issue. Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20ipmi: Generate an interrupt on watchdog pretimeout expiryCorey Minyard1-1/+3
Add the watchdog pretimeout to the bits that cause an interrupt on attn. Otherwise the user won't know. Signed-off-by: Corey Minyard <cminyard@mvista.com>
2019-09-20ipmi: Fix the get watchdog commandCorey Minyard1-0/+2
It wasn't returning the set timeout like it should have been. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-20ipmi: Fix watchdog NMI handlingCorey Minyard2-4/+4
The wrong logic was used for detection (so it wouldn't work at all) and the wrong interface was used to inject the NMI if the detection logic was correct. Signed-off-by: Corey Minyard <cminyard@mvista.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
2019-09-19Merge remote-tracking branch 'remotes/kraxel/tags/ui-20190919-pull-request' ↵Peter Maydell13-169/+1409
into staging ui: add barrier client. ui: bugfixes for vnc & egl. # gpg: Signature made Thu 19 Sep 2019 08:09:05 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20190919-pull-request: vnc: fix memory leak when vnc disconnect ui: add an embedded Barrier client vnc: fix websocket field in events ui/egl: fix framebuffer reads Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-19Merge remote-tracking branch 'remotes/kraxel/tags/ati-20190919-pull-request' ↵Peter Maydell4-35/+60
into staging vga: fix cursor code in ati-vga. # gpg: Signature made Thu 19 Sep 2019 10:10:32 BST # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ati-20190919-pull-request: ati: use vga_read_byte in ati_cursor_define vga: move access helpers to separate include file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-19Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' ↵Peter Maydell10-12/+23
into staging Pull request # gpg: Signature made Wed 18 Sep 2019 14:17:59 BST # gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full] # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" [full] # Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8 * remotes/stefanha/tags/tracing-pull-request: trace: Forbid event format ending with newline character trace: Remove trailing newline in events loader: Trace loaded images Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-19Merge remote-tracking branch ↵Peter Maydell41-444/+1366
'remotes/palmer/tags/riscv-for-master-4.2-sf1-v3' into staging RISC-V Patches for the 4.2 Soft Freeze, Part 1, v3 This contains quite a few patches that I'd like to target for 4.2. They're mostly emulation fixes for the sifive_u board, which now much more closely matches the hardware and can therefor run the same fireware as what gets loaded onto the board. Additional user-visible improvements include: * support for loading initrd files from the command line into Linux, via /chosen/linux,initrd-{start,end} device tree nodes. * The conversion of LOG_TRACE to trace events. * The addition of clock DT nodes for our uart and ethernet. This also includes some preliminary work for the H extension patches, but does not include the H extension patches as I haven't had time to review them yet. This passes my OE boot test on 32-bit and 64-bit virt machines, as well as a 64-bit upstream Linux boot on the sifive_u machine. It has been fixed to actually pass "make check" this time. Changes since v2 (never made it to the list): * Sets the sifive_u machine default core count to 2 instead of 5. Changes since v1 <20190910190513.21160-1-palmer@sifive.com>: * Sets the sifive_u machine default core count to 5 instead of 1, as it's impossible to have a single core sifive_u machine. # gpg: Signature made Tue 17 Sep 2019 16:43:30 BST # gpg: using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41 # gpg: issuer "palmer@dabbelt.com" # gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown] # gpg: aka "Palmer Dabbelt <palmer@sifive.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 00CE 76D1 8349 60DF CE88 6DF8 EF4C A150 2CCB AB41 * remotes/palmer/tags/riscv-for-master-4.2-sf1-v3: (48 commits) gdbstub: riscv: fix the fflags registers target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point target/riscv: Fix mstatus dirty mask target/riscv: Use both register name and ABI name riscv: sifive_u: Update model and compatible strings in device tree riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet riscv: sifive_u: Fix broken GEM support riscv: sifive_u: Instantiate OTP memory with a serial number riscv: sifive: Implement a model for SiFive FU540 OTP riscv: roms: Update default bios for sifive_u machine riscv: sifive_u: Change UART node name in device tree riscv: sifive_u: Update UART base addresses and IRQs riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes riscv: sifive_u: Add PRCI block to the SoC riscv: sifive_u: Generate hfclk and rtcclk nodes riscv: sifive: Implement PRCI model for FU540 riscv: sifive_u: Update PLIC hart topology configuration string riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC riscv: sifive_u: Set the minimum number of cpus to 2 riscv: hart: Add a "hartid-base" property to RISC-V hart array ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-09-19ati: use vga_read_byte in ati_cursor_defineGerd Hoffmann1-9/+10
This makes sure reads are confined to vga video memory. v3: use uint32_t, fix cut+paste bug. v2: fix ati_cursor_draw_line too. Reported-by: xu hang <flier_m@outlook.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190917111441.27405-3-kraxel@redhat.com
2019-09-19vga: move access helpers to separate include fileGerd Hoffmann3-26/+50
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190917111441.27405-2-kraxel@redhat.com
2019-09-18trace: Forbid event format ending with newline characterPhilippe Mathieu-Daudé2-0/+5
Event format ending with newlines confuse the trace reports. Forbid them. Add a check to refuse new format added with trailing newline: $ make [...] GEN hw/misc/trace.h Traceback (most recent call last): File "scripts/tracetool.py", line 152, in <module> main(sys.argv) File "scripts/tracetool.py", line 143, in main events.extend(tracetool.read_events(fh, arg)) File "scripts/tracetool/__init__.py", line 367, in read_events event = Event.build(line) File "scripts/tracetool/__init__.py", line 281, in build raise ValueError("Event format can not end with a newline character") ValueError: Error at hw/misc/trace-events:121: Event format can not end with a newline character Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190916095121.29506-3-philmd@redhat.com Message-Id: <20190916095121.29506-3-philmd@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-09-18trace: Remove trailing newline in eventsPhilippe Mathieu-Daudé5-12/+12
While the tracing framework does not forbid trailing newline in events format string, using them lead to confuse output. It is the responsibility of the backend to properly end an event line. Some of our formats have trailing newlines, remove them. [Fixed typo in commit description reported by Eric Blake <eblake@redhat.com> --Stefan] Reviewed-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190916095121.29506-2-philmd@redhat.com Message-Id: <20190916095121.29506-2-philmd@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-09-18loader: Trace loaded imagesAlexey Kardashevskiy3-0/+6
This adds a trace point which prints every loaded image. This includes bios/firmware/kernel/initradmdisk/pcirom. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20190613050937.124903-1-aik@ozlabs.ru> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2019-09-17gdbstub: riscv: fix the fflags registersKONRAD Frederic1-2/+4
While debugging an application with GDB the following might happen: (gdb) return Make xxx return now? (y or n) y Could not fetch register "fflags"; remote failure reply 'E14' This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr number (8). It should use the csr_register_map in order to reach the riscv_cpu_get_fflags callback. Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17target/riscv: Use TB_FLAGS_MSTATUS_FS for floating pointAlistair Francis1-1/+1
Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb flags. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17target/riscv: Fix mstatus dirty maskAlistair Francis1-1/+1
This is meant to mask off the hypervisor bits, but a typo caused it to mask MPP instead. Fixes: 1f0419cb04 ("target/riscv: Allow setting mstatus virtulisation bits") Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17target/riscv: Use both register name and ABI nameAtish Patra1-8/+11
Use both the generic register name and ABI name for the general purpose registers and floating point registers. Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Update model and compatible strings in device treeBin Meng1-2/+3
This updates model and compatible strings to use the same strings as used in the Linux kernel device tree (hifive-unleashed-a00.dts). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernetBin Meng2-25/+2
In the past we did not have a model for PRCI, hence two handcrafted clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the purpose of supplying hard-coded clock frequencies. But now since we have added the PRCI support in QEMU, we don't need them any more. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Fix broken GEM supportBin Meng3-5/+23
At present the GEM support in sifive_u machine is seriously broken. The GEM block register base was set to a weird number (0x100900FC), which for no way could work with the cadence_gem model in QEMU. Not like other GEM variants, the FU540-specific GEM has a management block to control 10/100/1000Mbps link speed changes, that is mapped to 0x100a0000. We can simply map it into MMIO space without special handling using create_unimplemented_device(). Update the GEM node compatible string to use the official name used by the upstream Linux kernel, and add the management block reg base & size to the <reg> property encoding. Tested with upstream U-Boot and Linux kernel MACB drivers. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Instantiate OTP memory with a serial numberBin Meng2-0/+12
This adds an OTP memory with a given serial number to the sifive_u machine. With such support, the upstream U-Boot for sifive_fu540 boots out of the box on the sifive_u machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive: Implement a model for SiFive FU540 OTPBin Meng3-0/+272
This implements a simple model for SiFive FU540 OTP (One-Time Programmable) Memory interface, primarily for reading out the stored serial number from the first 1 KiB of the 16 KiB OTP memory reserved by SiFive for internal use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: roms: Update default bios for sifive_u machineBin Meng2-2/+2
With the support of heterogeneous harts and PRCI model, it's now possible to use the OpenSBI image (PLATFORM=sifive/fu540) built for the real hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Change UART node name in device treeBin Meng1-1/+1
OpenSBI for fu540 does DT fix up (see fu540_modify_dt()) by updating chosen "stdout-path" to point to "/soc/serial@...", and U-Boot will use this information to locate the serial node and probe its driver. However currently we generate the UART node name as "/soc/uart@...", causing U-Boot fail to find the serial node in DT. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Update UART base addresses and IRQsBin Meng2-4/+4
This updates the UART base address and IRQs to match the hardware. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jonathan Behrens <fintelia@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodesBin Meng2-3/+14
Now that we have added a PRCI node, update existing UART and ethernet nodes to reference PRCI as their clock sources, to keep in sync with the Linux kernel device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Add PRCI block to the SoCBin Meng2-1/+26
Add PRCI mmio base address and size mappings to sifive_u machine, and generate the corresponding device tree node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Generate hfclk and rtcclk nodesBin Meng2-0/+25
To keep in sync with Linux kernel device tree, generate hfclk and rtcclk nodes in the device tree, to be referenced by PRCI node. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive: Implement PRCI model for FU540Bin Meng3-0/+251
This adds a simple PRCI model for FU540 (sifive_u). It has different register layout from the existing PRCI model for FE310 (sifive_e). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Update PLIC hart topology configuration stringBin Meng1-3/+4
With heterogeneous harts config, the PLIC hart topology configuration string are "M,MS,.." because of the monitor hart #0. Suggested-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Update hart configuration to reflect the real FU540 SoCBin Meng2-26/+72
The FU540-C000 includes a 64-bit E51 RISC-V core and four 64-bit U54 RISC-V cores. Currently the sifive_u machine only populates 4 U54 cores. Update the max cpu number to 5 to reflect the real hardware, by creating 2 CPU clusters as containers for RISC-V hart arrays to populate heterogeneous harts. The cpu nodes in the generated DTS have been updated as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Set the minimum number of cpus to 2Bin Meng2-1/+6
It is not useful if we only have one management CPU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> [Palmer: Set default CPUs to 2] Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: hart: Add a "hartid-base" property to RISC-V hart arrayBin Meng2-1/+3
At present each hart's hartid in a RISC-V hart array is assigned the same value of its index in the hart array. But for a system that has multiple hart arrays, this is not the case any more. Add a new "hartid-base" property so that hartid number can be assigned based on the property value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: hart: Extract hart realize to a separate routineBin Meng1-13/+20
Currently riscv_harts_realize() creates all harts based on the same cpu type given in the hart array property. With current implementation it can only create homogeneous harts. Exact the hart realize to a separate routine in preparation for supporting multiple hart arrays. Note the file header says the RISC-V hart array holds the state of a heterogeneous array of RISC-V harts, which is not true. Update the comment to mention homogeneous array of RISC-V harts. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: Add a sifive_cpu.h to include both E and U cpu type definesBin Meng3-12/+33
Group SiFive E and U cpu type defines into one header file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_e: Drop sifive_mmio_emulate()Bin Meng2-15/+9
Use create_unimplemented_device() instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_e: prci: Update the PRCI register block sizeBin Meng2-1/+3
Currently the PRCI register block size is set to 0x8000, but in fact 0x1000 is enough, which is also what the manual says. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_e: prci: Fix a typo of hfxosccfg register programmingBin Meng1-1/+1
For hfxosccfg register programming, SIFIVE_E_PRCI_HFXOSCCFG_RDY and SIFIVE_E_PRCI_HFXOSCCFG_EN should be used. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}Bin Meng5-114/+111
Current SiFive PRCI model only works with sifive_e machine, as it only emulates registers or PRCI block in the FE310 SoC. Rename the file name to make it clear that it is for sifive_e. This also prefix "sifive_e"/"SIFIVE_E" for all macros, variables and functions. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-09-17riscv: sifive_u: Remove the unnecessary include of prci headerBin Meng1-1/+0
sifive_u machine does not use PRCI as of today. Remove the prci header inclusion. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
generated by cgit v1.1 at 2025-01-01 13:01:50 +0000