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2014-12-22fw_cfg: hard separation between the MMIO and I/O port mappingsLaszlo Ersek3-55/+126
We are going to introduce a wide data register for fw_cfg, but only for the MMIO mapped device. The wide data register will also require the tightening of endiannesses. However we don't want to touch the I/O port mapped fw_cfg device at all. Currently QEMU provides a single fw_cfg device type that can handle both I/O port and MMIO mapping. This flexibility is not actually exploited by any board in the tree, but it renders restricting the above changes to MMIO very hard. Therefore, let's derive two classes from TYPE_FW_CFG: TYPE_FW_CFG_IO and TYPE_FW_CFG_MEM. TYPE_FW_CFG_IO incorporates the base I/O port and the related combined MemoryRegion. (NB: all boards in the tree that use the I/O port mapped flavor opt for the combined mapping; that is, when the data port overlays the high address byte of the selector port. Therefore we can drop the capability to map those I/O ports separately.) TYPE_FW_CFG_MEM incorporates the base addresses for the MMIO selector and data registers, and their respective MemoryRegions. The "realize" and "props" class members are specific to each new derived class, and become unused for the base class. The base class retains the "reset" member and the "vmsd" member, because the reset functionality and the set of migrated data are not specific to the mapping. The new functions fw_cfg_init_io() and fw_cfg_init_mem() expose the possible mappings in separation. For now fw_cfg_init() is retained as a compatibility shim that enforces the above assumptions. Signed-off-by: Laszlo Ersek <lersek@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1419250305-31062-2-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: add cpu feature EL3 to CPUs with Security ExtensionsFabian Aggeler1-0/+4
Set ARM_FEATURE_EL3 feature for CPUs that implement Security Extensions. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-16-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Disable EL3 on unsupported machinesGreg Bellows6-0/+71
Disables the CPU ARM_FEATURE_EL3 featuere on machine models that can be configured to use Cortex-A9, Cortex-A15, and ARM1176 but don't officially support EL3. This preserves backwards compatibility. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-15-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Breakout integratorcp and versatilepb cpu initGreg Bellows2-4/+35
This commit changes the integratorcp and versatilepb CPU initialization from using the generic ARM cpu_arm_init function to doing it inline. This is necessary in order to allow CPU configuration changes to occur between CPU instance initialization and realization. Specifically, this change is in preparation for disabling CPU EL3 support. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-14-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Set CPU has_el3 prop during virt initGreg Bellows1-0/+5
Adds setting of the CPU has_el3 property based on the virt machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during virt CPU initialization. Also disables the ARM secure boot by default. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418684992-8996-13-git-send-email-greg.bellows@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Enable CPU has_el3 prop during VE initGreg Bellows1-3/+9
Adds setting of the CPU has_el3 property based on the vexpress machine secure state property during initialization. This enables/disables EL3 state during start-up. Changes include adding an additional secure state boolean during vexpress CPU initialization. Also enables the ARM secure boot by default. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418684992-8996-12-git-send-email-greg.bellows@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add arm_boot_info secure_boot controlGreg Bellows2-0/+14
Adds the secure_boot boolean field to the arm_boot_info descriptor. This fields is used to indicate whether Linux should boot into secure or non-secure state if the ARM EL3 feature is enabled. The default is to leave the CPU in an unaltered reset state. On EL3 enabled systems, the reset state is secure and can be overridden by setting the added field to false. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-11-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add ARMCPU secure propertyGreg Bellows2-0/+25
Added a "has_el3" state property to the ARMCPU descriptor. This property indicates whether the ARMCPU has security extensions enabled (EL3) or not. By default it is disabled at this time. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-10-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add feature unset functionGreg Bellows1-0/+5
Add an unset_feature() function to compliment the set_feature() function. This will be used to disable functions after they have been enabled during initialization. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-9-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add virt machine secure propertyGreg Bellows1-0/+30
Add "secure" virt machine specific property to allow override of the default secure state configuration. By default, when using the QEMU -kernel command line argument, virt machines boot into NS/SVC. When using the QEMU -bios command line argument, virt machines boot into S/SVC. The secure state can be changed from the default specifying the secure state as a machine property. For example, the below command line would disable security extensions on a -kernel Linux boot: aarch64-softmmu/qemu-system-aarch64 -machine type=virt,secure=off -kernel ... Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-8-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add virt class and machine typesGreg Bellows1-6/+34
Switch virt qemu machine support to use the newer object type, class, and instance model. Added virt TypeInfo with static registration along with virt specific class and machine structs. Also added virt class initialization method. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-7-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Change vexpress daughterboard init argGreg Bellows1-5/+5
Change the Vexpress daughterboard initialization method to take a vexpress machine state pointer instead of the daughterboard struct pointer. The machine state now contains the daughterboard pointer. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-6-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add vexpress machine secure propertyGreg Bellows1-0/+30
Add "secure" Vexpress machine specific property to allow override of the default secure state configuration. By default, when using the QEMU -kernel command line argument, Vexpress machines boot into NS/SVC. When using the QEMU -bios command line argument, Vexpress machines boot into S/SVC. The secure state can be changed from the default specifying the secure state as a machine property. For example, the below command line would disable security extensions on a -kernel Linux boot: aarch64-softmmu/qemu-system-aarch64 -machine type=vexpress-a15,secure=off -kernel ... Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-5-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Switch to common vexpress machine initGreg Bellows1-22/+4
Switched the Vexpress machine initialization to use the common function with the machine pointer to board info. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-4-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add vexpress a9 & a15 machine objectsGreg Bellows1-14/+36
Add Vexpress machine objects for the the Cortex A9 & A15 variants. The older style QEMUMachine types were replaced with dedicated TypeInfo objects. The new objects include dedicated class init functions that currently ustilze dedicated machine init methods. The previous qemu_register_machine calls were replaced with the newer type_register_status calls. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-3-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Add vexpress class and machine typesGreg Bellows1-0/+45
Adds base Vexpress class and machine objects and infrastructure. This is in preparation for switching to the full QEMU object model. The base vexpress infrastructure is intended to handle common vexpress details. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418684992-8996-2-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22vl.c: add HMP help to machineMarcel Apfelbaum1-0/+28
The help is based on the actual machine properties exposing only the relevant options. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418217570-15517-4-git-send-email-marcel.a@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22vl.c: simplified machine_set_propertyMarcel Apfelbaum1-4/+1
Refactored the code to re-use object_property_parse. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418217570-15517-3-git-send-email-marcel.a@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22machine: remove qemu_machine_opts global listMarcel Apfelbaum4-78/+61
QEMU has support for options per machine, keeping a global list of options is no longer necessary. Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418217570-15517-2-git-send-email-marcel.a@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22target-arm: Merge EL3 CP15 register listsGreg Bellows1-31/+24
Merge of the v8_el2_cp_reginfo and el3_cp_reginfo ARMCPRegInfo lists. Previously, some EL3 registers were restricted to the ARMv8 list under the impression that they were not needed on ARMv7. However, this is not the case as the ARMv7/32-bit variants rely on the ARMv8/64-bit variants to handle migration and reset. For this reason they must always exist. Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Message-id: 1418406450-14961-1-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22audio: Don't free hw resources until after hw backend is stoppedPeter Maydell1-1/+1
When stopping an audio voice, call the audio backend's fini method before calling audio_pcm_hw_free_resources_ rather than afterwards. This allows backends which use helper threads (like pulseaudio) to terminate those threads before the conv_buf or mix_buf are freed and avoids race conditions where the helper may access a NULL pointer or freed memory. Cc: qemu-stable@nongnu.org Reviewed-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1418406239-9838-1-git-send-email-peter.maydell@linaro.org
2014-12-22Merge remote-tracking branch 'remotes/gonglei/tags/bootdevice-next-20141222' ↵Peter Maydell10-97/+118
into staging bootdevice: Refactor and improvement # gpg: Signature made Mon 22 Dec 2014 06:44:08 GMT using RSA key ID DDE30FBB # gpg: Can't check signature: public key not found * remotes/gonglei/tags/bootdevice-next-20141222: bootdevice: add Error **errp argument for QEMUBootSetHandler bootdevice: add validate check for qemu_boot_set() bootdevice: add Error **errp argument for qemu_boot_set() bootdevice: add Error **errp argument for validate_bootdevices() bootdevice: move code about bootorder from vl.c to bootdevice.c Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22Merge remote-tracking branch ↵Peter Maydell4-94/+2104
'remotes/bkoppelmann/tags/pull-tricore-20141221' into staging TriCore RR, RR1 insn added and several bug fixes # gpg: Signature made Sun 21 Dec 2014 18:39:11 GMT using RSA key ID 6B69CA14 # gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>" * remotes/bkoppelmann/tags/pull-tricore-20141221: target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as first opcode target-tricore: Fix MFCR/MTCR insn and B format offset. target-tricore: Add missing 1.6 insn of BOL opcode format target-tricore: Add instructions of RR opcode format, that have 0x4b as the first opcode target-tricore: Add instructions of RR opcode format, that have 0x1 as the first opcode target-tricore: Add instructions of RR opcode format, that have 0xf as the first opcode target-tricore: Add instructions of RR opcode format, that have 0xb as the first opcode target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32 target-tricore: Fix mask handling JNZ.T being 7 bit long target-tricore: pretty-print register dump and show more status registers target-tricore: add missing 64-bit MOV in RLC format target-tricore: typo in BOL format target-tricore: fix offset masking in BOL format Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-22bootdevice: add Error **errp argument for QEMUBootSetHandlerGonglei7-25/+23
It will be useful for checking when we change traditional boot order dynamically and propagate error message to the monitor. For x86 architecture, we pass &local_err to set_boot_dev() when vm startup in pc_coms_init(). Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: qemu-ppc@nongnu.org Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-12-22bootdevice: add validate check for qemu_boot_set()Gonglei1-0/+8
Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-12-22bootdevice: add Error **errp argument for qemu_boot_set()Gonglei3-13/+17
It will be useful for checking when we change traditional boot order dynamically and propagate error message to the monitor. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-12-22bootdevice: add Error **errp argument for validate_bootdevices()Gonglei3-8/+17
It will be useful for checking when we change traditional boot order dynamically and propagate error message to the monitor. Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-12-22bootdevice: move code about bootorder from vl.c to bootdevice.cGonglei4-68/+70
First, we can downsize vl.c, make it simpler by little and little. Second, I can maintain those code and make some improvement. Cc: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2014-12-21Merge remote-tracking branch 'remotes/kraxel/tags/pull-sdl-20141219-1' into ↵Peter Maydell6-255/+358
staging sdl2: fixes, cleanups and opengl preparation. # gpg: Signature made Fri 19 Dec 2014 09:06:07 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-sdl-20141219-1: sdl2: Work around SDL2 SDL_ShowWindow() bug sdl2: Use correct sdl2_console for window events sdl2: move sdl2_2d_refresh to sdl2-2d.c sdl2: factor out sdl2_poll_events sdl2: add+use sdl2_2d_redraw function. sdl2: move sdl_switch to sdl2-2d.c sdl2: overhaul window size handling sdl2: move sdl_update to new sdl2-2d.c sdl2: turn on keyboard grabs sdl2: move keyboard input code to new sdl2-input.c sdl2: rename sdl2_state to sdl2_console, move to header file sdl: move version logic from source code to makefile Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-21target-tricore: Add instructions of RR1 opcode format, that have 0xb3 as ↵Bastian Koppelmann3-0/+273
first opcode Add instructions of RR1 opcode format, that have 0xb3 as first opcode. Add helper functions mulh, mulmh and mulrh, that compute multiplication, with multiprecision (mulmh) or rounding (mulrh) of 4 halfwords, being either low or high parts of two 32 bit regs. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Fix MFCR/MTCR insn and B format offset.Bastian Koppelmann2-2/+6
Fix gen_mtcr using wrong register. Fix gen_mtcr/mfcr using sign extended offsets. Fix B format insn using not sign extendend offsets. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Add missing 1.6 insn of BOL opcode formatBastian Koppelmann2-1/+54
Some of the 1.6 ISA instructions were still missing. So let's add them. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x4b as the ↵Bastian Koppelmann4-1/+390
first opcode Add instructions of RR opcode format, that have 0x4b as the first opcode. Add helper functions: * parity: Calculates the parity bits for every byte of a 32 int. * bmerge/bsplit: Merges two regs into one bitwise/Splits one reg into two bitwise. * unpack: unpack a IEEE 754 single precision floating point number as exponent and mantissa. * dvinit_b_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 8 bit. * dvinit_h_13/131: (ISA v1.3/v1.31)Prepare operands for a divide operation, where the quotient result is guaranteed to fit into 16 bit. OPCM_32_RR_FLOAT -> OPCM_32_RR_DIVIDE. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0x1 as the ↵Bastian Koppelmann1-0/+97
first opcode Add instructions of RR opcode format, that have 0x1 as the first opcode. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xf as the ↵Bastian Koppelmann3-0/+250
first opcode Add instructions of RR opcode format, that have 0xf as the first opcode. Add helper functions: * clo/z/s: Counts leading ones/zeros/signs. * clo/z/s_h: Count leading ones/zeros/signs in two haflwords. * sh/_h: Shifts one/two word/hwords. * sha/_h: Shifts one/two word/hwords arithmeticly. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Add instructions of RR opcode format, that have 0xb as the ↵Bastian Koppelmann4-2/+942
first opcode Add instructions of RR opcode format, that have 0xb as the first opcode. Add helper functions, for hword and byte arithmetics: * add_h_ssov/suov: Add two halfword and saturate on overflow. * sub_h_ssov/suov: Sub two halfword and saturate on overflow. * absdif_h_ssov: Compute absolute difference for halfwords and saturate on overflow. * abs_h_ssov/suov: Compute absolute value for two halfwords and saturate on overflow. * abs_b/h: Compute absolute value for four/two bytes/halfwords * absdif_b/h: Compute absolute difference for four/two bytes/halfwords * add_b/h: Add four/two bytes/halfwords. * sub_b/h: Sub four/two bytes/halfwords. * eq_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality and set all bits of to either one ore zero. * eqany_b/h: Compare four/two bytes/halfwords with four/two bytes/halfwords on equality. * lt_b/bu/h/hu: Compare four/two bytes/halfwords with four/two bytes/halfwords on less than signed and unsigned. * max_b/bu/h/hu: Calculate max for four/two bytes/halfwords signed and unsigned. * min_b/bu/h/hu: Calculate min for four/two bytes/halfwords signed and unsigned. Add helper function abs_ssov, that computes the absolute value for a 32 bit integer and saturates on overflow. Add microcode generator functions: * gen_sub_CC: Caluclates sub and sets the carry bit. * gen_subc_CC: Caluclates sub and carry and sets the carry bit * gen_abs: Compute absolute value for a 32 bit integer. * gen_cond_w: Compares two 32 bit values on cond and sets result either zero or all bits one. OPC2_32_RR_MIN switched with OPC2_32_RR_MIN_U. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Change SSOV/SUOV makro name to SSOV32/SUOV32Bastian Koppelmann1-76/+58
Those makros are exclusively used for 32 bit arithmetics and won't work for 16 bit with two halfwords. So lets get rid of the len parameter and make them always use 32 bit. Now no token pasting is needed anymore and they can be regular functions. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
2014-12-21target-tricore: Fix mask handling JNZ.T being 7 bit longBastian Koppelmann1-2/+2
The mask is actually 7 bit long, instead of 6, so the expression checking for JNZ.T is always false. Let's make the mask 1 bit wider. Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21target-tricore: pretty-print register dump and show more status registersAlex Zuepke1-6/+15
Now using psw_read() to retrieve the status bits correctly. Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21target-tricore: add missing 64-bit MOV in RLC formatAlex Zuepke2-0/+13
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21target-tricore: typo in BOL formatAlex Zuepke2-3/+3
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-21target-tricore: fix offset masking in BOL formatAlex Zuepke1-1/+1
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
2014-12-20Merge remote-tracking branch 'remotes/stefanha/tags/net-pull-request' into ↵Peter Maydell6-46/+82
staging # gpg: Signature made Fri 19 Dec 2014 13:18:18 GMT using RSA key ID 81AB73C8 # gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" # gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>" * remotes/stefanha/tags/net-pull-request: e1000: defer packets until BM enabled net: Use g_new() & friends where that makes obvious sense net: Fuse g_malloc(); memset() into g_new0() net: don't use set/get_pointer() in set/get_netdev() tap: fix vcpu long time io blocking on tap Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-20Merge remote-tracking branch 'remotes/kraxel/tags/pull-roms-20141217-1' into ↵Peter Maydell7-0/+0
staging update ipxe from 69313ed to 35c5379 # gpg: Signature made Wed 17 Dec 2014 14:45:04 GMT using RSA key ID D3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" * remotes/kraxel/tags/pull-roms-20141217-1: update ipxe from 69313ed to 35c5379 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-20exec: change default exception_index value for migration to -1Paolo Bonzini1-2/+2
In QEMU 2.2 the exception_index value was added to the migration stream through a subsection. The default was set to 0, which is wrong and should have been -1. However, 2.2 does not have commit e511b4d (cpu-exec: reset exception_index correctly, 2014-11-26), hence in 2.2 the exception_index is never used and is set to -1 on the next call to cpu_exec. So we can change the migration stream to make the default -1. The effects are: - 2.2.1 -> 2.2.0: cpu->exception_index set incorrectly to 0 if it were -1 on the source; then reset to -1 in cpu_exec. This is TCG only; KVM does not use exception_index. - 2.2.0 -> 2.2.1: cpu->exception_index set incorrectly to -1 if it were 0 on the source; but it would be reset to -1 in cpu_exec anyway. This is TCG only; KVM does not use exception_index. - 2.2.1 -> 2.1: two bugs fixed: 1) can migrate backwards if cpu->exception_index is set to -1; 2) should not migrate backwards (but 2.2.0 allows it) if cpu->exception_index is set to 0 - 2.2.0 -> 2.3.0: 2.2.0 will send the subsection unnecessarily if exception_index is -1, but that is not a problem. 2.3.0 will set cpu->exception_index to -1 if it is 0 on the source, but this would be anyway a problem for 2.2.0 -> 2.2.x migration (due to lack of commit e511b4d in 2.2.x) so we can ignore it - 2.2.1 -> 2.3.0: everything works. In addition, play it safe and never send the subsection unless TCG is in use. KVM does not use exception_index (PPC KVM stores values in it for use in the subsequent call to ppc_cpu_do_interrupt, but does not need it as soon as kvm_handle_debug returns). Xen and qtest do not run any code for the CPU at all. Reported-by: Igor Mammedov <imammedo@redhat.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1418989994-17244-3-git-send-email-pbonzini@redhat.com Cc: qemu-stable@nongnu.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-20cpu: initialize cpu->exception_index on resetPaolo Bonzini2-3/+1
This unbreaks linux-user (broken by e511b4d, cpu-exec: reset exception_index correctly, 2014-11-26). Reported-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Eduardo Habkost <ehabkost@redhat.com> Message-id: 1418989994-17244-2-git-send-email-pbonzini@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2014-12-19e1000: defer packets until BM enabledMichael S. Tsirkin1-1/+20
Some guests seem to set BM for e1000 after enabling RX. If packets arrive in the window, device is wedged. Probably works by luck on real hardware, work around this by making can_receive depend on BM. Tested-by: Gabriel Somlo <somlo@cmu.edu> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-19net: Use g_new() & friends where that makes obvious senseMarkus Armbruster3-5/+5
g_new(T, n) is neater than g_malloc(sizeof(T) * n). It's also safer, for two reasons. One, it catches multiplication overflowing size_t. Two, it returns T * rather than void *, which lets the compiler catch more type errors. This commit only touches allocations with size arguments of the form sizeof(T). Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-19net: Fuse g_malloc(); memset() into g_new0()Markus Armbruster1-2/+1
Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2014-12-19net: don't use set/get_pointer() in set/get_netdev()Jason Wang1-38/+44
Commit 1ceef9f27359cbe92ef124bf74de6f792e71f6fb (net: multiqueue support) tries to use set_pointer() and get_pointer() to set and get NICPeers which is not a pointer defined in DEFINE_PROP_NETDEV. This trick works but result a unclean and fragile implementation (e.g print_netdev and parse_netdev). This patch solves this issue by not using set/get_pinter() and set and get netdev directly in set_netdev() and get_netdev(). After this the parse_netdev() and print_netdev() were no longer used and dropped from the source. [Renamed 'err' label to 'out' as suggested by Markus Armbruster. --Stefan] Cc: Markus Armbruster <armbru@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jason Wang <jasowang@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
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