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2019-02-24tpm_tis: fix loop that cancels any seizure by a lower localityLiam Merwick1-1/+1
In tpm_tis_mmio_write() if the requesting locality is seizing access, any seizure by a lower locality is cancelled. However the loop doing the seizure had an off-by-one error and the locality immediately preceding the requesting locality was not being cleared. This is fixed by adjusting the test in the for loop to check the localities up to the requesting locality. Signed-off-by: Liam Merwick <Liam.Merwick@oracle.com> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2019-02-22Merge remote-tracking branch 'remotes/awilliam/tags/vfio-updates-20190221.0' ↵Peter Maydell2-45/+90
into staging VFIO updates 2019-02-21 - Workaround kernel overflow bug in vfio type1 DMA unmap (Alex Williamson) - Refactor vfio container initialization (Eric Auger) # gpg: Signature made Fri 22 Feb 2019 05:21:07 GMT # gpg: using RSA key 239B9B6E3BB08B22 # gpg: Good signature from "Alex Williamson <alex.williamson@redhat.com>" [full] # gpg: aka "Alex Williamson <alex@shazbot.org>" [full] # gpg: aka "Alex Williamson <alwillia@redhat.com>" [full] # gpg: aka "Alex Williamson <alex.l.williamson@gmail.com>" [full] # Primary key fingerprint: 42F6 C04E 540B D1A9 9E7B 8A90 239B 9B6E 3BB0 8B22 * remotes/awilliam/tags/vfio-updates-20190221.0: hw/vfio/common: Refactor container initialization vfio/common: Work around kernel overflow bug in DMA unmap Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-22Merge remote-tracking branch 'remotes/rth/tags/pull-hppa-20190221' into stagingPeter Maydell2-3/+24
Fix dino pci config access. # gpg: Signature made Thu 21 Feb 2019 19:03:26 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-hppa-20190221: hw/hppa/dino: mask out lower 2 bits of PCI config addr Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-22Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20190221' into stagingPeter Maydell2-14/+5
Allow const void * as argument to helpers. Remove obsolete TODO file. # gpg: Signature made Thu 21 Feb 2019 18:59:11 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20190221: include/exec/helper-head.h: support "const void *" in helper calls tcg: Remove TODO file Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-22Merge remote-tracking branch ↵Peter Maydell18-63/+120
'remotes/amarkovic/tags/mips-queue-feb-21-2019-v2' into staging MIPS queue for February 21st, 2019, v2 # gpg: Signature made Thu 21 Feb 2019 18:37:04 GMT # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-feb-21-2019-v2: target/mips: fulong2e: Dynamically generate SPD EEPROM data target/mips: fulong2e: Fix bios flash size hw/pci-host/bonito.c: Add PCI mem region mapped at the correct address target/mips: implement QMP query-cpu-definitions command tests/tcg: target/mips: Add wrappers for MSA integer compare instructions tests/tcg: target/mips: Change directory name 'bit-counting' to 'bit-count' tests/tcg: target/mips: Correct path to headers in some test source files hw/misc: mips_itu: Fix 32/64 bit issue in a line involving shift operator Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21hw/vfio/common: Refactor container initializationEric Auger1-44/+70
We introduce the vfio_init_container_type() helper. It computes the highest usable iommu type and then set the container and the iommu type. Its usage in vfio_connect_container() makes the code ready for addition of new iommu types. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2019-02-21vfio/common: Work around kernel overflow bug in DMA unmapAlex Williamson2-1/+20
A kernel bug was introduced in v4.15 via commit 71a7d3d78e3c which adds a test for address space wrap-around in the vfio DMA unmap path. Unfortunately due to overflow, the kernel detects an unmap of the last page in the 64-bit address space as a wrap-around. In QEMU, a Q35 guest with VT-d emulation and guest IOMMU enabled will attempt to make such an unmap request during VM system reset, triggering an error: qemu-kvm: VFIO_UNMAP_DMA: -22 qemu-kvm: vfio_dma_unmap(0x561f059948f0, 0xfef00000, 0xffffffff01100000) = -22 (Invalid argument) Here the IOVA start address (0xfef00000) and the size parameter (0xffffffff01100000) add to exactly 2^64, triggering the bug. A kernel fix is queued for the Linux v5.0 release to address this. This patch implements a workaround to retry the unmap, excluding the final page of the range when we detect an unmap failing which matches the requirements for this issue. This is expected to be a safe and complete workaround as the VT-d address space does not extend to the full 64-bit space and therefore the last page should never be mapped. This workaround can be removed once all kernels with this bug are sufficiently deprecated. Link: https://bugzilla.redhat.com/show_bug.cgi?id=1662291 Reported-by: Pei Zhang <pezhang@redhat.com> Debugged-by: Peter Xu <peterx@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Cornelia Huck <cohuck@redhat.com> Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
2019-02-21Merge remote-tracking branch ↵Peter Maydell22-1328/+2305
'remotes/pmaydell/tags/pull-target-arm-20190221' into staging target-arm queue: * Model the Arm "Musca" development boards: "musca-a" and "musca-b1" * Implement the ARMv8.3-JSConv extension * v8M MPU should use background region as default, not always * Stop unintentional sign extension in pmu_init # gpg: Signature made Thu 21 Feb 2019 18:56:32 GMT # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190221: (21 commits) hw/arm/armsse: Make 0x5... alias region work for per-CPU devices hw/arm/musca: Wire up PL011 UARTs hw/arm/musca: Wire up PL031 RTC hw/arm/musca: Add MPCs hw/arm/musca: Add PPCs hw/arm/musca.c: Implement models of the Musca-A and -B1 boards hw/arm/armsse: Allow boards to specify init-svtor hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header comment hw/char/pl011: Use '0x' prefix when logging hex numbers hw/char/pl011: Support all interrupt lines hw/char/pl011: Allow use as an embedded-struct device hw/timer/pl031: Convert to using trace events hw/timer/pl031: Allow use as an embedded-struct device hw/misc/tz-ppc: Support having unused ports in the middle of the range target/arm: Implement ARMv8.3-JSConv target/arm: Rearrange Floating-point data-processing (2 regs) target/arm: Split out vfp_helper.c target/arm: Restructure disas_fp_int_conv target/arm: Stop unintentional sign extension in pmu_init target/arm: v8M MPU should use background region as default, not always ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/mips: fulong2e: Dynamically generate SPD EEPROM dataBALATON Zoltan1-18/+13
The machine comes with 256M memory module by default but it's upgradable so it could have different memory size. There was a TODO comment to replace static SPD EEPROM data with dynamically generated one to support this. Now that we have a function for that, it's easy to do. Although this would allow larger RAM sizes, the peculiar memory map of the machine may need some special handling to map it as low and high memory. Because I don't know what the correct place would be for highmem, I've left memory size fixed at 256M for now and TODO is moved there instead. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21target/mips: fulong2e: Fix bios flash sizeBALATON Zoltan1-5/+4
According to both the specifications on linux-mips.org referenced in a comment at the beginning of the file and the flash chip part number the bios size should be 512k not 1M. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21hw/pci-host/bonito.c: Add PCI mem region mapped at the correct addressBALATON Zoltan1-1/+6
Stop using system memory as PCI memory otherwise devices such as VGA that have regions mapped to PCI memory clash with RAM. Use a separate memory region for PCI memory and map it to the correct address in system memory which allows PCI mem regions to show at the correct address where clients expect them. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21target/mips: implement QMP query-cpu-definitions commandPavel Dovgalyuk2-2/+35
This patch enables QMP-based querying of the available CPU types for MIPS and MIPS64 platforms. Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com>
2019-02-21tests/tcg: target/mips: Add wrappers for MSA integer compare instructionsAleksandar Markovic1-0/+25
Add wrappers for MSA integer compare instructions. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
2019-02-21tests/tcg: target/mips: Change directory name 'bit-counting' to 'bit-count'Aleksandar Markovic12-0/+0
Change directory name 'bit-counting' to 'bit-count'. This is just for cosmetic and consistency sake. This was the only subdirectory in MSA test directory that uses ending 'ing'. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21tests/tcg: target/mips: Correct path to headers in some test source filesAleksandar Markovic12-36/+36
Correct path to headers in tests/tcg/mips/user/ase/msa/bit-counting/* source files. Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
2019-02-21hw/misc: mips_itu: Fix 32/64 bit issue in a line involving shift operatorAleksandar Markovic1-1/+1
Fix 32/64 bit issue in a line involving shift operator. "1 << ..." calculation of size is done as a 32-bit signed integer which may then be unintentionally sign-extended into the 64-bit result. The problem was discovered by Coverity (CID 1398648). Using "1ULL" instead of "1" on the LHS of the shift fixes this problem. Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2019-02-21include/exec/helper-head.h: support "const void *" in helper callsDavid Hildenbrand1-0/+5
Especially when dealing with out-of-line gvec helpers, it is often helpful to specify some vector pointers as constant. E.g. when we have two inputs and one output, marking the two inputs as consts pointers helps to avoid bugs. Const pointers can be specified via "cptr", however behave in TCG just like ordinary pointers. We can specify helpers like: DEF_HELPER_FLAGS_4(gvec_vbperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32) void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3, uint32_t desc) And make sure that here, only v1 will be written (as long as const is not casted away, of course). Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20190221093459.22547-1-david@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21tcg: Remove TODO fileRichard Henderson1-14/+0
The last update to this file was 9 years ago. In the meantime, 4 of the 6 ideas have actually been completed. The lat two do not actually make sense anymore. Suggested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/armsse: Make 0x5... alias region work for per-CPU devicesPeter Maydell2-11/+17
The region 0x40010000 .. 0x4001ffff and its secure-only alias at 0x50010000... are for per-CPU devices. We implement this by giving each CPU its own container memory region, where the per-CPU devices live. Unfortunately, the alias region which makes devices mapped at 0x4... addresses also appear at 0x5... is only implemented in the overall "all CPUs" container. The effect of this bug is that the CPU_IDENTITY register block appears only at 0x4001f000, but not at the 0x5001f000 alias where it should also appear. Guests (like very recent Arm Trusted Firmware-M) which try to access it at 0x5001f000 will crash. Fix this by moving the handling for this alias from the "all CPUs" container to the per-CPU container. (We leave the aliases for 0x1... and 0x3... in the overall container, because there are no per-CPU devices there.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190215180500.6906-1-peter.maydell@linaro.org Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-02-21hw/arm/musca: Wire up PL011 UARTsPeter Maydell1-5/+29
Wire up the two PL011 UARTs in the Musca board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/musca: Wire up PL031 RTCPeter Maydell1-3/+23
Wire up the PL031 RTC for the Musca board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/musca: Add MPCsPeter Maydell1-8/+147
The Musca board puts its SRAM and flash behind TrustZone Memory Protection Controllers (MPCs). Each MPC sits between the CPU and the RAM/flash, and also has a set of memory mapped control registers. Wire up the MPCs, and the memory behind them. For the moment we implement the flash as simple ROM, which cannot be reprogrammed by the guest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/musca: Add PPCsPeter Maydell1-0/+289
Many of the devices on the Musca board live behind TrustZone Peripheral Protection Controllers (PPCs); add models of the PPCs, using a similar scheme to the MPS2 board models. This commit wires up the PPCs with "unimplemented device" stubs behind them in the correct places in the address map. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/musca.c: Implement models of the Musca-A and -B1 boardsPeter Maydell4-0/+205
The Musca-A and Musca-B1 development boards are based on the SSE-200 subsystem for embedded. Implement an initial skeleton model of these boards, which are similar but not identical. This commit creates the board model with the SSE and the IRQ splitters to wire IRQs up to its two CPUs. As yet there are no devices and no memory: these will be added later. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/armsse: Allow boards to specify init-svtorPeter Maydell2-4/+7
The Musca boards have DAPLink firmware that sets the initial secure VTOR value (the location of the vector table) differently depending on the boot mode (from flash, from RAM, etc). Export the init-svtor as a QOM property of the ARMSSE object so that the board can change it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/arm/armsse: Document SRAM_ADDR_WIDTH property in header commentPeter Maydell1-0/+2
In commit 4b635cf7a95e501211 we added a QOM property to the ARMSSE object, but forgot to add it to the documentation comment in the header. Correct the omission. Fixes: 4b635cf7a95e501211 ("hw/arm/armsse: Make SRAM bank size configurable") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/char/pl011: Use '0x' prefix when logging hex numbersPeter Maydell1-2/+2
The pl011 logs when the guest makes a bad access. It prints the address offset in hex but confusingly omits the '0x' prefix; add it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/char/pl011: Support all interrupt linesPeter Maydell2-3/+45
The PL011 UART has six interrupt lines: * RX (receive data) * TX (transmit data) * RT (receive timeout) * MS (modem status) * E (errors) * combined (logical OR of all the above) So far we have only emulated the combined interrupt line; add support for the others, so that boards that wire them up to different interrupt controller inputs can do so. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/char/pl011: Allow use as an embedded-struct devicePeter Maydell2-29/+36
Create a new include file for the pl011's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/timer/pl031: Convert to using trace eventsPeter Maydell2-25/+36
Convert the debug printing in the PL031 device to use trace events, and augment it to cover the interesting parts of device operation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/timer/pl031: Allow use as an embedded-struct devicePeter Maydell3-24/+46
Create a new include file for the pl031's device struct, type macros, etc, so that it can be instantiated using the "embedded struct" coding style. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21hw/misc/tz-ppc: Support having unused ports in the middle of the rangePeter Maydell2-1/+39
The Peripheral Protection Controller's handling of unused ports is that if there is nothing connected to the port's downstream then it does not create the sysbus MMIO region for the upstream end of the port. This results in odd behaviour when there is an unused port in the middle of the range: since sysbus MMIO regions are implicitly consecutively allocated, any used ports above the unused ones end up with sysbus MMIO region numbers that don't match the port number. Avoid this numbering mismatch by creating dummy MMIO regions for the unused ports. This doesn't change anything for our existing boards, which don't have any gaps in the middle of the port ranges they use; but it will be needed for the Musca board. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21target/arm: Implement ARMv8.3-JSConvRichard Henderson7-0/+140
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> [PMM: fixed a couple of comment typos] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Rearrange Floating-point data-processing (2 regs)Richard Henderson1-116/+111
There are lots of special cases within these insns. Split the major argument decode/loading/saving into no_output (compares), rd_is_dp, and rm_is_dp. We still need to special case argument load for compare (rd as input, rm as zero) and vcvt fixed (rd as input+output), but lots of special cases do disappear. Now that we have a full switch at the beginning, hoist the ISA checks from the code generation. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Split out vfp_helper.cRichard Henderson3-1063/+1089
Move all of the fp helpers out of helper.c into a new file. This is code movement only. Since helper.c has no copyright header, take the one from cpu.h for the new file. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Restructure disas_fp_int_convRichard Henderson1-43/+47
For opcodes 0-5, move some if conditions into the structure of a switch statement. For opcodes 6 & 7, decode everything at once with a second switch. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190215192302.27855-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: Stop unintentional sign extension in pmu_initAaron Lindsay OS1-1/+1
This was introduced by commit bf8d09694ccc07487cd73d7562081fdaec3370c8 target/arm: Don't clear supported PMU events when initializing PMCEID1 and identified by Coverity (CID 1398645). Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com> Reported-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190219144621.450-1-aaron@os.amperecomputing.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21target/arm: v8M MPU should use background region as default, not alwaysPeter Maydell1-3/+5
The "background region" for a v8M MPU is a default which will be used (if enabled, and if the access is privileged) if the access does not match any specific MPU region. We were incorrectly using it always (by putting the condition at the wrong nesting level). This meant that we would always return the default background permissions rather than the correct permissions for a specific region, and also that we would not return the right information in response to a TT instruction. Move the check for the background region to the same place in the logic as the equivalent v8M MPUCheck() pseudocode puts it. This in turn means we must adjust the condition we use to detect matches in multiple regions to avoid false-positives. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20190214113408.10214-1-peter.maydell@linaro.org
2019-02-21hw/arm/armsse: Fix memory leak in error-exit pathPeter Maydell1-4/+6
Coverity points out (CID 1398632, CID 1398650) that we leak a couple of allocated strings in the error-exit code path for setting up the MHUs in the ARMSSE. Fix this bug by moving the allocate-and-free of each string to be closer to the use, so we do the free before doing the error-exit check. Fixes: f8574705f62b38a ("hw/arm/armsse: Add unimplemented-device stubs for MHUs") Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190215113707.24553-1-peter.maydell@linaro.org
2019-02-21hw/hppa/dino: mask out lower 2 bits of PCI config addrSven Schnelle2-3/+24
some versions of HP-UX 10.20 seems to rely on the fact that DINO strips out the lower 2 bits of the PCI configuration address. Also update the binary SeaBIOS distributed to the latest version from Helge's repository, which is required with that change. Signed-off-by: Sven Schnelle <svens@stackframe.org> Message-Id: <20190218183314.20157-1-svens@stackframe.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-02-21Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into ↵Peter Maydell5-22/+79
staging Pull request # gpg: Signature made Wed 20 Feb 2019 18:01:00 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jnsnow/tags/bitmaps-pull-request: blockdev: acquire aio_context for bitmap add/remove block/dirty-bitmap: Documentation and Comment fixups dirty-bitmap: Expose persistent flag to 'query-block' Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-21Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190220-pull-request' ↵Peter Maydell7-16/+30
into staging usb: usb_ep_get() fixes # gpg: Signature made Wed 20 Feb 2019 11:13:32 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20190220-pull-request: usb: remove unnecessary NULL device check from usb_ep_get() usb: add device checks before redirector calls to usb_ep_get() usb: check device is not NULL before calling usb_ep_get() uhci: check device is not NULL before calling usb_ep_get() ohci: check device is not NULL before calling usb_ep_get() ehci: check device is not NULL before calling usb_ep_get() xhci: check device is not NULL before calling usb_ep_get() xhci: add asserts to help with static code analysis usb: rearrange usb_ep_get() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-02-20usb: remove unnecessary NULL device check from usb_ep_get()Liam Merwick1-3/+1
No caller of usb_ep_get() calls it with a NULL device (previous commits have addressed the few remaining cases which didn't explicitly check). Replace check for 'dev == NULL' with an assert instead. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-10-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20usb: add device checks before redirector calls to usb_ep_get()Liam Merwick1-1/+2
Add an assert and an explicit check before the two callers to usb_ep_get() in the USB redirector code to ensure the device passed in is not NULL. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-9-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20usb: check device is not NULL before calling usb_ep_get()Liam Merwick1-4/+4
In musb_packet(), the call to usb_find_device() can return NULL if it doesn't find a device matching 'addr' so explicitly check the return value before passing it to usb_ep_get(). This then allows the subsequent calculation of 'id' to be streamlined. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-8-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20uhci: check device is not NULL before calling usb_ep_get()Liam Merwick1-3/+5
In uhci_handle_td(), the call to ehci_find_device() can return NULL if it doesn't find a device matching 'addr' so explicitly check the return value before passing it to usb_ep_get(). Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-7-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20ohci: check device is not NULL before calling usb_ep_get()Liam Merwick1-0/+8
A call to ohci_find_device() can return NULL if it doesn't find a device matching 'addr' so for the two callers, explicitly check the return value before passing it to usb_ep_get(). Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-6-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20ehci: check device is not NULL before calling usb_ep_get()Liam Merwick1-2/+5
In ehci_process_itd(), the call to ehci_find_device() can return NULL if it doesn't find a device matching 'devaddr' so explicitly check the return value before passing it to usb_ep_get(). Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-5-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20xhci: check device is not NULL before calling usb_ep_get()Liam Merwick1-2/+2
Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-4-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-02-20xhci: add asserts to help with static code analysisLiam Merwick1-0/+2
Most callers of xhci_port_update() and xhci_wakeup() pass in a pointer to an array entry and can never be NULL but add two defensive asserts to protect against future changes (e.g. adding a new port speed, etc.) adding a path through xhci_lookup_port() that could result in the return of a NULL XHCIPort. Signed-off-by: Liam Merwick <liam.merwick@oracle.com> Message-id: 1549460216-25808-3-git-send-email-liam.merwick@oracle.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
generated by cgit v1.1 at 2024-12-27 11:50:44 +0000