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2019-01-03disas: nanoMIPS: Comment the decoder of 'gpr3' gpr encoding typeAleksandar Markovic1-3/+48
Comment the decoder of 'gpr3' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Rename the decoder of 'gpr3' gpr encoding typeAleksandar Markovic2-49/+49
Rename the decoder of 'gpr3' gpr encoding type in nanoMIPS disassembler. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix order of more invocationsAleksandar Markovic1-130/+130
Fix order of extraction function invocations so that extraction goes from MSB side to LSB side of the given instruction coding content. This is desireable because of consistency and easier visual spotting of errors. After this patch, all such invocations should be in the desired order. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Name more functions in a more descriptive wayAleksandar Markovic2-120/+120
Rename more functions that have names that are hard to understand. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix an FP-related misnomer 3Aleksandar Markovic2-130/+130
Rename NMD::extract_ft_20_19_18_17_16(uint64 instruction) to NMD::extract_ft_25_24_23_22_21(uint64 instruction). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix an FP-related misnomer 2Aleksandar Markovic2-122/+122
Rename NMD::extract_fs_15_14_13_12_11(uint64 instruction) to NMD::extract_fs_20_19_18_17_16(uint64 instruction). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix an FP-related misnomer 1Aleksandar Markovic2-72/+72
Rename NMD::extract_fd_10_9_8_7_6(uint64 instruction) to NMD::extract_fd_15_14_13_12_11(uint64 instruction). Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Name some functions in a more descriptive wayAleksandar Markovic2-72/+72
Rename some functions that have names that are hard to understand. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix order of some invocationsAleksandar Markovic1-388/+388
Fix order of extraction function invocations so that extraction goes from MSB side to LSB side of the given instruction coding content. This is desireable because of consistency and easier visual spotting of errors. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix a function misnomerAleksandar Markovic2-133/+133
Fix wrong function name. The convention in these files is that names of extraction functions should reflect bit patterns they are extracting. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Remove functions that are not usedAleksandar Markovic2-233/+0
Some functions were not used at all. Compiler doesn't complain since they are class memebers. Remove them - no future usage is planned. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix preamble text in nanomips.* filesAleksandar Markovic2-6/+8
Fix several mistakes in preambles of nanomips disassembler source files. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03disas: nanoMIPS: Fix types and format stringsStefan Weil2-13/+17
Use POSIX types and format strings. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Stefan Weil <sw@weilnetz.de>
2019-01-03target/mips: Support R5900 three-operand MADD1 and MADDU1 instructionsFredrik Noring1-3/+9
The three-operand MADD and MADDU are specific to R5900 cores. Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Fredrik Noring <noring@nocrew.org>
2019-01-03target/mips: Support R5900 three-operand MADD and MADDU instructionsPhilippe Mathieu-Daudé1-5/+53
The three-operand MADD and MADDU are specific to Sony R5900 core, and Toshiba TX19/TX39/TX79 cores as well. The "32-Bit TX System RISC TX39 Family Architecture manual" is available at https://wiki.qemu.org/File:DSAE0022432.pdf Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org> Signed-off-by: Fredrik Noring <noring@nocrew.org> Tested-by: Fredrik Noring <noring@nocrew.org>
2019-01-03target/mips: MXU: Add handler for an align instructionAleksandar Markovic1-3/+194
Add translation handler for S32ALNI MXU instruction. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03target/mips: MXU: Add handlers for max/min instructionsAleksandar Markovic1-21/+279
Add translation handlers for six max/min MXU instructions. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03target/mips: MXU: Add handlers for logic instructionsAleksandar Markovic1-34/+205
Add translation handlers for four logic MXU instructions. It should be noted that there is an error in MXU documentation (dated June 2017) regarding opcodes for this group of instructions. This was confirmed by running tests on hardware, and also by looking up other related public source trees (binutils, Android NDK). In initial MXU patches to QEMU, opcodes for MXU logic instructions were created to be in accordance with the MXU documentation, therefore the error from was propagated. This patch corrects that, changing the involved code. Besides that, as MXU was designed and implemented only for 32-bit CPUs, corresponding preprosessor conditions were added around MXU code, which allows more flexible implementation of MXU handlers. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03target/mips: MXU: Improve the comment containing MXU overviewAleksandar Markovic1-30/+44
Improve textual description of MXU extension. These are mostly comment formatting changes. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03target/mips: MXU: Add generic naming for optn2 constantsAleksandar Markovic1-0/+5
Add generic naming involving generig suffixes OPTN0, OPTN1, OPTN2, OPTN3 for four optn2 constants. Existing suffixes WW, LW, HW, XW are not quite appropriate for some instructions using optn2. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03target/mips: MXU: Add missing opcodes/decoding for LX* instructionsAleksandar Markovic1-38/+102
Add missing opcodes and decoding engine for LXB, LXH, LXW, LXBU, and LXHU instructions. They were for some reason forgotten in previous commits. The MXU opcode list and decoding engine should be now complete. Reviewed-by: Stefan Markovic <smarkovic@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03atomics: Set ATOMIC_REG_SIZE=8 for MIPS n32Paul Burton1-2/+3
ATOMIC_REG_SIZE is currently defined as the default sizeof(void *) for all MIPS host builds, including those using the n32 ABI. n32 is the MIPS64 ILP32 ABI and as such tcg/mips/tcg-target.h defines TCG_TARGET_REG_BITS as 64 for n32 builds. If we attempt to build QEMU for an n32 host with support for a 64b target architecture then TCG_OVERSIZED_GUEST is 0 and accel/tcg/cputlb.c attempts to use atomic_* functions. This fails because ATOMIC_REG_SIZE is 4, causing the calls to QEMU_BUILD_BUG_ON(sizeof(*ptr) > ATOMIC_REG_SIZE) in the various atomic_* functions to generate errors. Fix this by defining ATOMIC_REG_SIZE as 8 for all MIPS64 builds, which will cover both n32 (ILP32) & n64 (LP64) ABIs in much the same was as we already do for x86_64/x32. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Signed-off-by: Paul Burton <pburton@wavecomp.com>
2019-01-03MAINTAINERS: Add Aleksandar Rikalo as a reviewer for MIPS contentAleksandar Markovic1-0/+9
Add Aleksandar Rikalo as a reviewer for MIPS content. Aleksandar brings to us more than six years of experience in working on a variety of development tools for MIPS architectures, and will greatly help QEMU community understand and support intricacies of MIPS better. Acked-by: Aleksandar Rikalo <arikalo@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03MAINTAINERS: target/mips: Reorder items alphabeticallyAleksandar Markovic1-5/+5
Reorder items alphabetically for better visibility. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03MAINTAINERS: target/mips: Add filter for mips in email subjectsAleksandar Markovic1-0/+1
Add ability to redirect mails (sent to qemu-devel) containing "mips" in the subject line to MIPS maintainers and reviewers. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03MAINTAINERS: target/mips: Add MIPS files under default-configs directoryAleksandar Markovic1-0/+1
Add following files as maintained within the main MIPS target section in MAINTAINERS: default-configs/mips64el-linux-user.mak default-configs/mips64-linux-user.mak default-configs/mipsn32el-linux-user.mak default-configs/mipsn32-linux-user.mak default-configs/mipsel-linux-user.mak default-configs/mips-linux-user.mak default-configs/mips64el-softmmu.mak default-configs/mips64-softmmu.mak default-configs/mipsel-softmmu.mak default-configs/mips-softmmu.mak default-configs/mips-softmmu-common.mak Future nanoMIPS user mode will also have its .mak file, and because of that "*mips*" was used instead of "mips*" as a shorthand in the new item in MAINTAINERS. Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2019-01-03Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20181226' into stagingPeter Maydell19-164/+2945
Host support for riscv64. Dead code elimination pass. Register allocation improvements. # gpg: Signature made Tue 25 Dec 2018 20:52:34 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-tcg-20181226: (42 commits) tcg: Improve call argument loading tcg: Record register preferences during liveness tcg: Add TCG_OPF_BB_EXIT tcg: Split out more subroutines from liveness_pass_1 tcg: Rename and adjust liveness_pass_1 helpers tcg: Reindent parts of liveness_pass_1 tcg: Dump register preference info with liveness tcg: Improve register allocation for matching constraints tcg: Add output_pref to TCGOp tcg: Add preferred_reg argument to tcg_reg_alloc_do_movi tcg: Add preferred_reg argument to temp_sync tcg: Add preferred_reg argument to temp_load tcg: Add preferred_reg argument to tcg_reg_alloc tcg: Add reachable_code_pass tcg: Reference count labels tcg: Add TCG_CALL_NO_RETURN tcg: Renumber TCG_CALL_* flags linux-user: Add safe_syscall for riscv64 host disas/microblaze: Remove unused REG_SP macro configure: Add support for building RISC-V host ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-12-26tcg: Improve call argument loadingRichard Henderson1-1/+2
Free the argument register only after we have verified that the temporary is not already in that register. This case is likely now that we are back propagating the preferred register. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Record register preferences during livenessRichard Henderson1-32/+165
With these preferences, we can arrange for function call arguments to be computed into the proper registers instead of requiring extra moves. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add TCG_OPF_BB_EXITRichard Henderson3-10/+16
Use this to notice the opcodes that exit the TB, which implies that local temps are really dead and need not be synced. Previously we so marked the true end of the TB, but that was immediately overwritten by the la_bb_end invoked by any TCG_OPF_BB_END opcode, like exit_tb. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Split out more subroutines from liveness_pass_1Richard Henderson1-12/+23
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Rename and adjust liveness_pass_1 helpersRichard Henderson1-8/+5
No need for a "tcg_" prefix for a static function; we already have another "la_" prefix for indicating liveness analysis. Pass in nb_globals and nb_temps, as we will already have them in registers for other loops within the parent function. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Reindent parts of liveness_pass_1Richard Henderson1-67/+70
There are two blocks of the form if (foo) { stuff1; goto bar; } else { baz: stuff2; } which have unnecessary and confusing indentation. Remove the else and unindent stuff2. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Dump register preference info with livenessRichard Henderson2-10/+37
Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Improve register allocation for matching constraintsRichard Henderson1-12/+24
Try harder to honor the output_pref. When we're forced to allocate a second register for the input, it does not need to use the input constraint; that will be honored by the register we allocate for the output and a move is already required. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add output_pref to TCGOpRichard Henderson2-7/+14
Allocate storage for, but do not yet fill in, per-opcode preferences for the output operands. Pass it in to the register allocation routines for output operands. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add preferred_reg argument to tcg_reg_alloc_do_moviRichard Henderson1-4/+5
Pass this through to temp_sync. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add preferred_reg argument to temp_syncRichard Henderson1-8/+8
Pass this through to tcg_reg_alloc. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add preferred_reg argument to temp_loadRichard Henderson1-9/+9
Pass this through to tcg_reg_alloc. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add preferred_reg argument to tcg_reg_allocRichard Henderson1-22/+81
This new argument will aid register allocation by indicating how the temporary will be used in future. If the preference cannot be satisfied, fall back to the constraints of the current insn. Short circuit the preference when it cannot be satisfied or if it does not further constrain the operation. With an eye toward optimizing function call sequences, optimize for the preferred_reg set containing a single register. For the moment, all users pass 0 for preference. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add reachable_code_passRichard Henderson1-0/+76
Delete trivially dead code that follows unconditional branches and noreturn helpers. These can occur either via optimization or via the structure of a target's translator following an exception. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Reference count labelsRichard Henderson4-1/+25
Increment when adding branches, and decrement when removing them. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add TCG_CALL_NO_RETURNRichard Henderson3-7/+29
Remember which helpers have been marked noreturn. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Renumber TCG_CALL_* flagsRichard Henderson1-3/+3
Previously, the low 4 bits were used for TCG_CALL_TYPE_MASK, which was removed in 6a18ae2d2947532d5c26439548afa0481c4529f9. Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26linux-user: Add safe_syscall for riscv64 hostRichard Henderson2-0/+100
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26disas/microblaze: Remove unused REG_SP macroRichard Henderson1-1/+0
This causes a build error with debian sid, riscv64 host: disas/microblaze.c:179: error: "REG_SP" redefined [-Werror] #define REG_SP 1 /* stack pointer */ In file included from /usr/include/signal.h:306, from include/qemu/osdep.h:101, from disas/microblaze.c:36: /usr/include/riscv64-linux-gnu/sys/ucontext.h:36: note: this is the location of the previous definition # define REG_SP 2 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26configure: Add support for building RISC-V hostAlistair Francis1-2/+10
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <52160afacecc5b109dc43a412fa3e74ddd6277fb.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26disas: Add RISC-V supportAlistair Francis1-2/+8
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <caa478c8987d6042434bb9582017cdf0ea192208.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg: Add RISC-V cpu signal handlerAlistair Francis1-0/+75
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <c445175310fa836b61fd862a55628907f0093194.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-12-26tcg/riscv: Add the target init codeAlistair Francis1-0/+31
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Michael Clark <mjc@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <dd6e439ab81883974b8fd91f904f6de26ab5d697.1545246859.git.alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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