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5 hoursMerge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into stagingstagingRichard Henderson36-249/+269
* configure: detect --cpu=mipsisa64r6 * target/i386: decode address before going back to translate.c * meson: allow configuring the x86-64 baseline * meson: remove dead optimization option * exec: small changes to allow compilation with C++ in Android emulator * fix SEV compilation on 32-bit systems # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCAAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmZ+8mEUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroMVmAf+PjJBpMYNFb2qxJDw5jI7hITsrtm4 # v5TKo9x7E3pna5guae5ODFencYhBITQznHFa3gO9w09QN7Gq/rKjuBBST9VISslU # dW3HtxY9A1eHQtNqHuD7jBWWo9N0hhNiLRa6xz/VDTjEJSxhjSdK2bRW9Yz9hZAe # 8bbEEC9us21RdFTS+eijOMo9SPyASUlqIq4RbQpbAVuzzOMeXnfOuX9VSTcBy9o2 # 7cKMg7zjL8WQugJKynyl5lny7m1Ji55LD2UrYMF6Mik3Wz5kwgHcUITJ+ZHd/9hR # a+MI7o/jyCPdmX9pBvJCxyerCVYBu0ugLqYKpAcsqU6111FLrnGgDvHf/g== # =LdYd # -----END PGP SIGNATURE----- # gpg: Signature made Fri 28 Jun 2024 10:26:57 AM PDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (23 commits) target/i386/sev: Fix printf formats target/i386/sev: Use size_t for object sizes target/i386: SEV: store pointer to decoded id_auth in SevSnpGuest target/i386: SEV: rename sev_snp_guest->id_auth target/i386: SEV: store pointer to decoded id_block in SevSnpGuest target/i386: SEV: rename sev_snp_guest->id_block target/i386: remove unused enum target/i386: give CC_OP_POPCNT low bits corresponding to MO_TL target/i386: use cpu_cc_dst for CC_OP_POPCNT target/i386: fix CC_OP dump include: move typeof_strip_qual to compiler.h, use it in QAPI_LIST_LENGTH() exec: don't use void* in pointer arithmetic in headers exec: avoid using C++ keywords in function parameters block: rename former bdrv_file_open callbacks block: remove separate bdrv_file_open callback block: do not check bdrv_file_open block: make assertion more generic meson: remove dead optimization option meson: allow configuring the x86-64 baseline Revert "host/i386: assume presence of SSE2" ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10 hourstarget/i386/sev: Fix printf formatsRichard Henderson1-6/+11
hwaddr uses HWADDR_PRIx, sizeof yields size_t so uses %zu, and gsize uses G_GSIZE_FORMAT. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240626194950.1725800-4-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10 hourstarget/i386/sev: Use size_t for object sizesRichard Henderson2-9/+9
This code was using both uint32_t and uint64_t for len. Consistently use size_t instead. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/r/20240626194950.1725800-3-richard.henderson@linaro.org Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10 hourstarget/i386: SEV: store pointer to decoded id_auth in SevSnpGuestPaolo Bonzini1-5/+8
Do not rely on finish->id_auth_uaddr, so that there are no casts from pointer to uint64_t. They break on 32-bit hosts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10 hourstarget/i386: SEV: rename sev_snp_guest->id_authPaolo Bonzini1-6/+6
Free the "id_auth" name for the binary version of the data. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10 hourstarget/i386: SEV: store pointer to decoded id_block in SevSnpGuestPaolo Bonzini1-5/+6
Do not rely on finish->id_block_uaddr, so that there are no casts from pointer to uint64_t. They break on 32-bit hosts. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10 hourstarget/i386: SEV: rename sev_snp_guest->id_blockPaolo Bonzini1-6/+6
Free the "id_block" name for the binary version of the data. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
10 hourstarget/i386: remove unused enumPaolo Bonzini1-16/+0
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hourstarget/i386: give CC_OP_POPCNT low bits corresponding to MO_TLPaolo Bonzini2-4/+12
Handle it like the other arithmetic cc_ops. This simplifies a bit the implementation of bit test instructions. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hourstarget/i386: use cpu_cc_dst for CC_OP_POPCNTPaolo Bonzini4-6/+6
It is the only CCOp, among those that compute ZF from one of the cc_op_* registers, that uses cpu_cc_src. Do not make it the odd one off, instead use cpu_cc_dst like the others. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hourstarget/i386: fix CC_OP dumpPaolo Bonzini1-63/+64
POPCNT was missing, and the entries were all out of order after ADCX/ADOX/ADCOX were moved close to EFLAGS. Just use designated initializers. Fixes: 4885c3c4953 ("target-i386: Use ctpop helper", 2017-01-10) Fixes: cc155f19717 ("target/i386: rewrite flags writeback for ADCX/ADOX", 2024-06-11) Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursinclude: move typeof_strip_qual to compiler.h, use it in QAPI_LIST_LENGTH()Paolo Bonzini3-43/+47
The typeof_strip_qual() is most useful for the atomic fetch-and-modify operations in atomic.h, but it can be used elsewhere as well. For example, QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a requirement. Move the macro to compiler.h and, while at it, move it under #ifndef __cplusplus to emphasize that it uses C-only constructs. A C++ version of typeof_strip_qual() using type traits is possible[1], but beyond the scope of this patch because the little C++ code that is in QEMU does not use QAPI. The patch was tested by changing the declaration of strv_from_str_list() in qapi/qapi-type-helpers.c to: char **strv_from_str_list(const strList *const list) This is valid C code, and it fails to compile without this change. [1] https://lore.kernel.org/qemu-devel/20240624205647.112034-1-flwu@google.com/ Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Tested-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursexec: don't use void* in pointer arithmetic in headersRoman Kiryanov1-1/+1
void* pointer arithmetic is a GCC extentension which could not be available in other build tools (e.g. C++). This changes removes this assumption. Signed-off-by: Roman Kiryanov <rkir@google.com> Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Link: https://lore.kernel.org/r/20240620201654.598024-1-rkir@google.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursexec: avoid using C++ keywords in function parametersRoman Kiryanov1-2/+2
to use the QEMU headers with a C++ compiler. Signed-off-by: Roman Kiryanov <rkir@google.com> Link: https://lore.kernel.org/r/20240618224553.878869-1-rkir@google.com Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursblock: rename former bdrv_file_open callbacksPaolo Bonzini4-15/+15
Since there is no bdrv_file_open callback anymore, rename the implementations so that they end with "_open" instead of "_file_open". NFS is the exception because all the functions are named nfs_file_*. Suggested-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursblock: remove separate bdrv_file_open callbackPaolo Bonzini17-34/+30
bdrv_file_open and bdrv_open are completely equivalent, they are never checked except to see which one to invoke. So merge them into a single one. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursblock: do not check bdrv_file_openPaolo Bonzini1-6/+5
The set of BlockDrivers that have .bdrv_file_open coincides with those that have .protocol_name and guess what---checking drv->bdrv_file_open is done to see if the driver is a protocol. So check drv->protocol_name instead. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursblock: make assertion more genericPaolo Bonzini1-1/+1
.bdrv_needs_filename is only set for drivers that also set bdrv_file_open, i.e. protocol drivers. So we can make the assertion always, it will always pass for those drivers that use bdrv_open. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursmeson: remove dead optimization optionPaolo Bonzini3-18/+0
Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursmeson: allow configuring the x86-64 baselinePaolo Bonzini3-8/+39
Add a Meson option to configure which x86-64 instruction set to use. QEMU will now default to x86-64-v1 + cmpxchg16b for 64-bit builds (that corresponds to a Pentium 4 for 32-bit builds). The baseline can be tuned down to Pentium Pro for 32-bit builds (with -Dx86_version=0), or up as desired. Acked-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursRevert "host/i386: assume presence of SSE2"Paolo Bonzini3-2/+5
This reverts commit b18236897ca15c3db1506d8edb9a191dfe51429c. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursRevert "host/i386: assume presence of SSSE3"Paolo Bonzini1-2/+2
This reverts commit 433cd6d94a8256af70a5200f236dc8047c3c1468. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursRevert "host/i386: assume presence of POPCNT"Paolo Bonzini3-2/+5
This reverts commit 45ccdbcb24baf99667997fac5cf60318e5e7db51. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 hoursconfigure: detect --cpu=mipsisa64r6Paolo Bonzini1-1/+1
Treat it as a MIPS64 machine. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
37 hoursMerge tag 'pull-riscv-to-apply-20240627-1' of ↵HEADmasterRichard Henderson12-203/+877
https://github.com/alistair23/qemu into staging RISC-V PR for 9.1 * Extend virtual irq csrs masks to be 64 bit wide * Move Guest irqs out of the core local irqs range * zvbb implies zvkb * virt: add address-cells in create_fdt_one_aplic() * virt: add aplic nodename helper * virt: rename aplic nodename to 'interrupt-controller' * virt: aplic DT: add 'qemu, aplic' to 'compatible' * virt: aplic DT: rename prop to 'riscv, delegation' * virt: change imsic nodename to 'interrupt-controller' * virt: imsics DT: add 'qemu, imsics' to 'compatible' * virt: imsics DT: add '#msi-cells' * QEMU support for KVM Guest Debug on RISC-V * Support RISC-V privilege 1.13 spec * Add support for RISC-V ACPI tests * Modularize common match conditions for trigger # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmZ9OCEACgkQr3yVEwxT # gBM6aRAApE7Cjo6U1MrcXywh897DnMV9TT9a0jWxhw659eOSk8Uo8mXNNmGSudcl # +//jIQr/JB5YVDcnFAGWFDaMMev2hkbXG68IaLsfqA32CWZzrOgFpFP+sgicDKmP # A+P/z0CL332hDRxlhglbIYukCN1bEjWbUDgZaXPVc7ieMM0mwDyFZt7jH65dNmNg # HpmVcUSooUx8weHOKp0vCKCBcQ6neahjvweTYszsWjXgu51+VrpoSAAds98HHY9H # vilbTGtJzGEmnfTCmm1GmRn5/g5iQzDKDge+Kg+OzINEfoOBByJerK27sGNRkzxt # ZNUd0RM2q1wkfZ3XfLU3qEnxHson8SQp2+VYTqnEv3TdR0AjrnsxL7IUuFm+iTv4 # wG3IqBwt+efdAzc9k+K2smCyp3036HNrJHQSyhtxu+yU36K+jBKVq++pRzgOFTvl # 87VvNI/dYL4hSJ4yS00ti2axl6GNEAEePHwQ0fRXvEdSGc4vOw3ayDqyqF0Gcy9+ # MJq+nV7BX9pEyTRZEKqTi2nB7xh3kq0e+mev2ByQlracBqHIayXC3DsDvPcUbiwJ # 8bzX28kl5C28vYUVJjzYQgZy2XXGbbsnv3ifah4hi2NJESmYHN0uxs9raW9i+lhR # 2FAm+eO6mxuJTIH/NTou+msxZJw2jTPLkYdG2e5UkTjUN7JKGnk= # =bag2 # -----END PGP SIGNATURE----- # gpg: Signature made Thu 27 Jun 2024 03:00:01 AM PDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20240627-1' of https://github.com/alistair23/qemu: (32 commits) target/riscv: Apply modularized matching conditions for icount trigger target/riscv: Apply modularized matching conditions for watchpoint target/riscv: Add functions for common matching conditions of trigger target/riscv: Remove extension auto-update check statements target/riscv: Add Zc extension implied rule target/riscv: Add multi extension implied rules target/riscv: Add MISA extension implied rules target/riscv: Introduce extension implied rule helpers target/riscv: Introduce extension implied rules definition target/riscv: fix instructions count handling in icount mode target/riscv: Fix froundnx.h nanbox check hw/riscv/virt.c: Make block devices default to virtio target/riscv: Support the version for ss1p13 target/riscv: Reserve exception codes for sw-check and hw-err target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32 target/riscv: Add 'P1P13' bit in SMSTATEEN0 target/riscv: Define macros and variables for ss1p13 target/riscv: Reuse the conversion function of priv_spec target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUG target/riscv/kvm: handle the exit with debug reason ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2 daystarget/riscv: Apply modularized matching conditions for icount triggerAlvin Chang1-1/+1
We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. We can invoke trigger_common_match() to check the privilege levels of the type 3 triggers. Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-4-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2 daystarget/riscv: Apply modularized matching conditions for watchpointAlvin Chang1-20/+6
We have implemented trigger_common_match(), which checks if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_watchpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6 triggers for the watchpoints. This commit also changes the behavior of looping the triggers. In previous implementation, if we have a type 2 trigger and env->virt_enabled is true, we directly return false to stop the loop. Now we keep looping all the triggers until we find a matched trigger. Only load/store bits and loaded/stored address should be further checked in riscv_cpu_debug_check_watchpoint(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-3-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2 daystarget/riscv: Add functions for common matching conditions of triggerAlvin Chang1-23/+78
According to RISC-V Debug specification version 0.13 [1] (also applied to version 1.0 [2] but it has not been ratified yet), there are several common matching conditions before firing a trigger, including the enabled privilege levels of the trigger. This commit adds trigger_common_match() to prepare the common matching conditions for the type 2/3/6 triggers. For now, we just implement trigger_priv_match() to check if the enabled privilege levels of the trigger match CPU's current privilege level. Remove the related code in riscv_cpu_debug_check_breakpoint() and invoke trigger_common_match() to check the privilege levels of the type 2 and type 6 triggers for the breakpoints. This commit also changes the behavior of looping the triggers. In previous implementation, if we have a type 2 trigger and env->virt_enabled is true, we directly return false to stop the loop. Now we keep looping all the triggers until we find a matched trigger. Only the execution bit and the executed PC should be futher checked in riscv_cpu_debug_check_breakpoint(). [1]: https://github.com/riscv/riscv-debug-spec/releases/tag/task_group_vote [2]: https://github.com/riscv/riscv-debug-spec/releases/tag/1.0.0-rc1-asciidoc Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240626132247.2761286-2-alvinga@andestech.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Remove extension auto-update check statementsFrank Chang1-119/+0
Remove the old-fashioned extension auto-update check statements as they are replaced by the extension implied rules. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-7-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Add Zc extension implied ruleFrank Chang1-0/+34
Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Add multi extension implied rulesFrank Chang1-0/+340
Add multi extension implied rules to enable the implied extensions of the multi extension recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Add MISA extension implied rulesFrank Chang1-1/+49
Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Introduce extension implied rule helpersFrank Chang1-0/+121
Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Introduce extension implied rules definitionFrank Chang2-0/+31
RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCPUConfig. 'ext' will also serve as the key of the hash tables to look up the rule in the following commit. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240625114629.27793-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: fix instructions count handling in icount modeClément Léger1-13/+17
When icount is enabled, rather than returning the virtual CPU time, we should return the instruction count itself. Add an instructions bool parameter to get_ticks() to correctly return icount_get_raw() when icount_enabled() == 1 and instruction count is queried. This will modify the existing behavior which was returning an instructions count close to the number of cycles (CPI ~= 1). Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20240618112649.76683-1-cleger@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Fix froundnx.h nanbox checkBranislav Brzak1-1/+1
helper_froundnx_h function mistakenly uses single percision nanbox check instead of the half percision one. This patch fixes the issue. Signed-off-by: Branislav Brzak <brzakbranislav@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240608214546.226963-1-brzakbranislav@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 dayshw/riscv/virt.c: Make block devices default to virtioSunil V L1-0/+2
RISC-V virt is currently missing default type for block devices. Without this being set, proper backend is not created when option like -cdrom is used. So, make the virt board's default block device type be IF_VIRTIO similar to other architectures. We also need to set no_cdrom to avoid getting a default cdrom device. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240620064718.275427-1-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Support the version for ss1p13Fea.Wang2-1/+9
Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20240606135454.119186-7-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Reserve exception codes for sw-check and hw-errFea.Wang1-0/+2
Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-6-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang2-0/+33
Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-5-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang2-0/+9
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-4-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Define macros and variables for ss1p13Fea.Wang2-1/+4
Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-3-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv: Reuse the conversion function of priv_specJim Shu3-10/+6
Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu <jim.shu@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-2-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUGChao Du1-0/+1
To enable the KVM GUEST DEBUG for RISC-V at QEMU side. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-4-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv/kvm: handle the exit with debug reasonChao Du1-0/+20
If the breakpoint belongs to the userspace then set the ret value. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-3-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 daystarget/riscv/kvm: add software breakpoints supportChao Du1-0/+69
This patch implements insert/remove software breakpoint process. For RISC-V, GDB treats single-step similarly to breakpoint: add a breakpoint at the next step address, then continue. So this also works for single-step debugging. Implement kvm_arch_update_guest_debug(): Set the control flag when there are active breakpoints. This will help KVM to know the status in the userspace. Add some stubs which are necessary for building, and will be implemented later. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-2-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 dayshw/riscv/virt.c: imsics DT: add '#msi-cells'Daniel Henrique Barboza1-0/+1
The DT docs for riscv,imsics [1] requires a 'msi-cell' property. Add one and set it zero. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240531202759.911601-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 dayshw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'Daniel Henrique Barboza1-1/+7
The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the 'compatible' property. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 dayshw/riscv/virt.c: change imsic nodename to 'interrupt-controller'Daniel Henrique Barboza1-1/+2
The Linux DT docs for imsic [1] predicts an 'interrupt-controller@addr' node, not 'imsic@addr', given this node inherits the 'interrupt-controller' node. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
3 dayshw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'Daniel Henrique Barboza1-1/+1
The DT docs for riscv,aplic [1] predicts a 'riscv,delegation' property. Not 'riscv,delegate'. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2024-06-29 03:41:12 +0000