aboutsummaryrefslogtreecommitdiff
AgeCommit message (Expand)AuthorFilesLines
2019-12-17Merge remote-tracking branch 'remotes/cleber/tags/python-next-pull-request' i...Peter Maydell17-197/+284
2019-12-17Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20191217' into...Peter Maydell65-955/+2454
2019-12-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' in...Peter Maydell2-28/+76
2019-12-17pseries: Update SLOF firmware imageAlexey Kardashevskiy3-1/+1
2019-12-17ppc/pnv: Drop PnvChipClass::typeGreg Kurz2-14/+0
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_pcba() methodGreg Kurz3-13/+25
2019-12-17ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpersGreg Kurz1-10/+0
2019-12-17ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()Greg Kurz3-21/+14
2019-12-17ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()Greg Kurz3-17/+14
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz2-7/+25
2019-12-17ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz2-5/+26
2019-12-17ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpersGreg Kurz1-10/+0
2019-12-17ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz2-6/+12
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz2-14/+31
2019-12-16python/qemu: Remove unneeded imports in __init__Wainer dos Santos Moschetta1-6/+0
2019-12-17ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz2-4/+0
2019-12-17ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz2-14/+13
2019-12-17ppc: Drop useless extern annotation for functionsGreg Kurz2-14/+14
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater4-11/+16
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater6-44/+134
2019-12-17ppc/pnv: Make PnvXScomInterface an incomplete typeGreg Kurz1-4/+2
2019-12-17ppc/pnv: populate the DT with realized XSCOM devicesCédric Le Goater1-1/+4
2019-12-17ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodesCédric Le Goater1-1/+6
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh5-0/+39
2019-12-17target/ppc: Add SPR ASDRSuraj Jitindar Singh2-0/+7
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh6-20/+30
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh7-4/+51
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater4-12/+53
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater5-8/+58
2019-12-17ppc/psi: cleanup definitionsCédric Le Goater1-2/+5
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater5-11/+232
2019-12-17target/ppc: Add POWER10 DD1.0 model informationCédric Le Goater5-6/+237
2019-12-17ppc: Make PPCVirtualHypervisor an incomplete typeGreg Kurz1-4/+0
2019-12-17ppc: Ignore the CPU_INTERRUPT_EXITTB interrupt with KVMGreg Kurz1-0/+5
2019-12-17ppc: Don't use CPUPPCState::irq_input_state with modern Book3s CPU modelsGreg Kurz2-15/+5
2019-12-17xics: Don't deassert outputsGreg Kurz1-3/+0
2019-12-17ppc: Deassert the external interrupt pin in KVM on resetGreg Kurz3-0/+11
2019-12-17spapr: Simplify ovec diffDavid Gibson4-40/+16
2019-12-17spapr: Fold h_cas_compose_response() into h_client_architecture_support()David Gibson3-66/+54
2019-12-17spapr: Improve handling of fdt buffer sizeDavid Gibson1-22/+11
2019-12-17spapr: Don't trigger a CAS reboot for XICS/XIVE mode changeoverDavid Gibson1-20/+13
2019-12-17ppc: well form kvmppc_hint_smt_possible error hint helperVladimir Sementsov-Ogievskiy3-6/+6
2019-12-17ppc/pnv: Dump the XIVE NVT tableCédric Le Goater2-0/+67
2019-12-17ppc/pnv: Extend XiveRouter with a get_block_id() handlerCédric Le Goater4-6/+29
2019-12-17ppc/pnv: Introduce a pnv_xive_block_id() helperCédric Le Goater2-34/+33
2019-12-17ppc/xive: Synthesize interrupt from the saved IPB in the NVTCédric Le Goater1-0/+52
2019-12-17ppc/xive: Introduce a xive_tctx_ipb_update() helperCédric Le Goater2-10/+12
2019-12-17ppc/xive: Remove the get_tctx() XiveRouter handlerCédric Le Goater4-30/+0
2019-12-17ppc/xive: Move the TIMA operations to the controller modelCédric Le Goater4-33/+65
2019-12-17ppc/pnv: Clarify how the TIMA is accessed on a multichip systemCédric Le Goater3-17/+40
generated by cgit v1.1 at 2024-09-03 19:10:03 +0000