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2022-11-10block/mirror: Do not wait for active writesHanna Reitz1-7/+30
Waiting for all active writes to settle before daring to create a background copying operation means that we will never do background operations while the guest does anything (in write-blocking mode), and therefore cannot converge. Yes, we also will not diverge, but actually converging would be even nicer. It is unclear why we did decide to wait for all active writes to settle before creating a background operation, but it just does not seem necessary. Active writes will put themselves into the in_flight bitmap and thus properly block actually conflicting background requests. It is important for active requests to wait on overlapping background requests, which we do in active_write_prepare(). However, so far it was not documented why it is important. Add such documentation now, and also to the other call of mirror_wait_on_conflicts(), so that it becomes more clear why and when requests need to actively wait for other requests to settle. Another thing to note is that of course we need to ensure that there are no active requests when the job completes, but that is done by virtue of the BDS being drained anyway, so there cannot be any active requests at that point. With this change, we will need to explicitly keep track of how many bytes are in flight in active requests so that job_progress_set_remaining() in mirror_run() can set the correct number of remaining bytes. Buglink: https://bugzilla.redhat.com/show_bug.cgi?id=2123297 Signed-off-by: Hanna Reitz <hreitz@redhat.com> Message-Id: <20221109165452.67927-2-hreitz@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2022-11-09Merge tag 'pull-tcg-20221109' of https://gitlab.com/rth7680/qemu into stagingStefan Hajnoczi2-35/+45
Fix -Werror=clobbered issue with tb_gen_code # -----BEGIN PGP SIGNATURE----- # # iQFRBAABCgA7FiEEekgeeIaLTbaoWgXAZN846K9+IV8FAmNrBscdHHJpY2hhcmQu # aGVuZGVyc29uQGxpbmFyby5vcmcACgkQZN846K9+IV9Fpwf/Rfj6jdVXlHX4mlWe # snuTeLYDMxZkcCEobPlM6MTG3bVetmulQD09bf6rppOSfiG4LjcLwQtIYafXNG98 # EJiIZJNOsQen6MXtFlv9ZeqWi8PBe+4YQbIT3fOn5BC9p0BxS0aiIrTM36PpvKE9 # PV7I+KpwoNUeMSaJHf/jH+Q272Tk1jlW3GYzygbX/XHxsoLz9byRO9A0AMwClAOF # XuNx+0+3w8xGfapsMU/oBkSMVFj03jsm07PMgvipMfT9s8qcTgzCyK8VeJPp9WHz # 9gn4mvVnEBQU1W3K2SCx1o3pyFaqmyMwnE0BixWKVEM9zAaJEBN5iYCn4QX0TH3y # Hmzc8g== # =YF54 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 08 Nov 2022 20:47:51 EST # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * tag 'pull-tcg-20221109' of https://gitlab.com/rth7680/qemu: accel/tcg: Split out setjmp_gen_code tcg: Move TCG_TARGET_HAS_direct_jump init to tb_gen_code Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-09accel/tcg: Split out setjmp_gen_codeRichard Henderson1-25/+33
Isolate the code protected by setjmp. Fixes: translate-all.c: In function ‘tb_gen_code’: translate-all.c:748:51: error: argument ‘cflags’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-11-09tcg: Move TCG_TARGET_HAS_direct_jump init to tb_gen_codeRichard Henderson2-10/+12
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-11-08Update VERSION for v7.2.0-rc0v7.2.0-rc0Stefan Hajnoczi1-1/+1
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-08Revert "hw/block/pflash_cfi: Error out if dev length isn't power of 2"Daniel Henrique Barboza2-11/+2
Commit 334c388f25 ("pflash_cfi: Error out if device length isn't a power of two") aimed to finish the effort started by commit 06f1521795 ("pflash: Require backend size to match device, improve errors"), but unfortunately we are not quite there since various machines are still ready to accept incomplete / oversized pflash backend images, and now fail, i.e. on Debian bullseye: $ qemu-system-x86_64 \ -drive \ if=pflash,format=raw,unit=0,readonly=on,file=/usr/share/OVMF/OVMF_CODE.fd qemu-system-x86_64: Device size must be a power of two. where OVMF_CODE.fd comes from the ovmf package, which doesn't pad the firmware images to the flash size: $ ls -lh /usr/share/OVMF/ -rw-r--r-- 1 root root 3.5M Aug 19 2021 OVMF_CODE_4M.fd -rw-r--r-- 1 root root 1.9M Aug 19 2021 OVMF_CODE.fd -rw-r--r-- 1 root root 128K Aug 19 2021 OVMF_VARS.fd Since we entered the freeze period to prepare the v7.2.0 release, the safest is to revert commit 334c388f25707a234c4a0dea05b9df08d. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1294 Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221108175755.95141-1-philmd@linaro.org> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Message-Id: <20221108172633.860700-1-danielhb413@gmail.com>
2022-11-08memory: Fix wrong end address dumpZhenzhong Duan1-1/+1
The end address of memory region section isn't correctly calculated which leads to overflowed mtree dump: Dispatch Physical sections ...... #70 @0000000000002000..0000000000011fff io [ROOT] #71 @0000000000005000..0000000000005fff (noname) #72 @0000000000005000..0000000000014fff io [ROOT] #73 @0000000000005658..0000000000005658 vmport #74 @0000000000005659..0000000000015658 io [ROOT] #75 @0000000000006000..0000000000015fff io [ROOT] After fix: #70 @0000000000002000..0000000000004fff io [ROOT] #71 @0000000000005000..0000000000005fff (noname) #72 @0000000000005000..0000000000005657 io [ROOT] #73 @0000000000005658..0000000000005658 vmport #74 @0000000000005659..0000000000005fff io [ROOT] #75 @0000000000006000..000000000000ffff io [ROOT] Fixes: 5e8fd947e2670 ("memory: Rework "info mtree" to print flat views and dispatch trees") Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20220622095912.3430583-1-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08vhost-vdpa: fix assert !virtio_net_get_subqueue(nc)->async_tx.elem in ↵Si-Wei Liu1-1/+1
virtio_net_reset The citing commit has incorrect code in vhost_vdpa_receive() that returns zero instead of full packet size to the caller. This renders pending packets unable to be freed so then get clogged in the tx queue forever. When device is being reset later on, below assertion failure ensues: 0 0x00007f86d53bb387 in raise () from /lib64/libc.so.6 1 0x00007f86d53bca78 in abort () from /lib64/libc.so.6 2 0x00007f86d53b41a6 in __assert_fail_base () from /lib64/libc.so.6 3 0x00007f86d53b4252 in __assert_fail () from /lib64/libc.so.6 4 0x000055b8f6ff6fcc in virtio_net_reset (vdev=<optimized out>) at /usr/src/debug/qemu/hw/net/virtio-net.c:563 5 0x000055b8f7012fcf in virtio_reset (opaque=0x55b8faf881f0) at /usr/src/debug/qemu/hw/virtio/virtio.c:1993 6 0x000055b8f71f0086 in virtio_bus_reset (bus=bus@entry=0x55b8faf88178) at /usr/src/debug/qemu/hw/virtio/virtio-bus.c:102 7 0x000055b8f71f1620 in virtio_pci_reset (qdev=<optimized out>) at /usr/src/debug/qemu/hw/virtio/virtio-pci.c:1845 8 0x000055b8f6fafc6c in memory_region_write_accessor (mr=<optimized out>, addr=<optimized out>, value=<optimized out>, size=<optimized out>, shift=<optimized out>, mask=<optimized out>, attrs=...) at /usr/src/debug/qemu/memory.c:483 9 0x000055b8f6fadce9 in access_with_adjusted_size (addr=addr@entry=20, value=value@entry=0x7f867e7fb7e8, size=size@entry=1, access_size_min=<optimized out>, access_size_max=<optimized out>, access_fn=0x55b8f6fafc20 <memory_region_write_accessor>, mr=0x55b8faf80a50, attrs=...) at /usr/src/debug/qemu/memory.c:544 10 0x000055b8f6fb1d0b in memory_region_dispatch_write (mr=mr@entry=0x55b8faf80a50, addr=addr@entry=20, data=0, op=<optimized out>, attrs=attrs@entry=...) at /usr/src/debug/qemu/memory.c:1470 11 0x000055b8f6f62ada in flatview_write_continue (fv=fv@entry=0x7f86ac04cd20, addr=addr@entry=549755813908, attrs=..., attrs@entry=..., buf=buf@entry=0x7f86d0223028 <Address 0x7f86d0223028 out of bounds>, len=len@entry=1, addr1=20, l=1, mr=0x55b8faf80a50) at /usr/src/debug/qemu/exec.c:3266 12 0x000055b8f6f62c8f in flatview_write (fv=0x7f86ac04cd20, addr=549755813908, attrs=..., buf=0x7f86d0223028 <Address 0x7f86d0223028 out of bounds>, len=1) at /usr/src/debug/qemu/exec.c:3306 13 0x000055b8f6f674cb in address_space_write (as=<optimized out>, addr=<optimized out>, attrs=..., buf=<optimized out>, len=<optimized out>) at /usr/src/debug/qemu/exec.c:3396 14 0x000055b8f6f67575 in address_space_rw (as=<optimized out>, addr=<optimized out>, attrs=..., attrs@entry=..., buf=buf@entry=0x7f86d0223028 <Address 0x7f86d0223028 out of bounds>, len=<optimized out>, is_write=<optimized out>) at /usr/src/debug/qemu/exec.c:3406 15 0x000055b8f6fc1cc8 in kvm_cpu_exec (cpu=cpu@entry=0x55b8f9aa0e10) at /usr/src/debug/qemu/accel/kvm/kvm-all.c:2410 16 0x000055b8f6fa5f5e in qemu_kvm_cpu_thread_fn (arg=0x55b8f9aa0e10) at /usr/src/debug/qemu/cpus.c:1318 17 0x000055b8f7336e16 in qemu_thread_start (args=0x55b8f9ac8480) at /usr/src/debug/qemu/util/qemu-thread-posix.c:519 18 0x00007f86d575aea5 in start_thread () from /lib64/libpthread.so.0 19 0x00007f86d5483b2d in clone () from /lib64/libc.so.6 Make vhost_vdpa_receive() return the size passed in as is, so that the caller qemu_deliver_packet_iov() would eventually propagate it back to virtio_net_flush_tx() to release pending packets from the async_tx queue. Which corresponds to the drop path where qemu_sendv_packet_async() returns non-zero in virtio_net_flush_tx(). Fixes: 846a1e85da64 ("vdpa: Add dummy receive callback") Cc: Eugenio Perez Martin <eperezma@redhat.com> Signed-off-by: Si-Wei Liu <si-wei.liu@oracle.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-Id: <20221108041929.18417-2-jasowang@redhat.com>
2022-11-08Merge tag 'pull-request-2022-11-08' of https://gitlab.com/thuth/qemu into ↵Stefan Hajnoczi22-7468/+7436
staging * Last minute s390x fixes before the hard freeze * Whiste space clean-up in ui/, display/ and hw/usb/ # -----BEGIN PGP SIGNATURE----- # # iQJFBAABCAAvFiEEJ7iIR+7gJQEY8+q5LtnXdP5wLbUFAmNqPZ0RHHRodXRoQHJl # ZGhhdC5jb20ACgkQLtnXdP5wLbVbwxAArAxJewpow+QBj7dMd6qLrpC7mjxgiiQD # F8XNYh6bPpPo3+4exmMKMS+DGSLC5TJnp61F4IHyH+yOx8DVWmrjo97q+nWYYD4y # jOdC5a2kzkMzVjrxy26uvPhoUGkiM5w8H5bF9hcWukuEwqpoJPU7u5RXd1yn48Ju # O1RrASw+rHZSnCGFFXldG2HoS+bUOaZRHQs5kV9EwpqEn42eQtq38CQ7YEMloOkD # FpPl75KEQ9/doqSbGLdFP1HzaG/emtFnioIXlGM3Y7RzDxCgvKTdAvPCOBO7LxHA # oOY/nFcRYIEUslvyZLUXahKE2qBv2nenmWAQ9lwGd/iU78nWzR19BZdpItSP3Sjj # HFLOKztqI8qLbx966uOU8O5FaYqfGPV6QZVOSzAl7u8GZbqpN5lp+uArEoGtawMo # 9fRDAgSoser9AAIWr1TOoFGRff3VT4hlZeale3VOmfxAOBc2r70pzvk3ou5mo8NU # VXb6Uz5nNIm8RV9fr6/jgllfQDMiCHSwaAnC1hABqAwatcU/SJ4dKfXbdwjsPN8V # jgC5GqAHaC9mwQu0rfZSzuGZkosh0MZVik/xcWO3hspT/CyIafpi42POyQEjOMYf # 5SgJ8ydV32xEGQw66cl9yLAuhN4F8eTavLwQBV7pmCeySm8HCFGuZrmQkeOTBTD2 # HEbJJjz9zgI= # =P8Mt # -----END PGP SIGNATURE----- # gpg: Signature made Tue 08 Nov 2022 06:29:33 EST # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * tag 'pull-request-2022-11-08' of https://gitlab.com/thuth/qemu: hw/usb: fix tab indentation hw/display: fix tab indentation ui: fix tab indentation s390x/s390-virtio-ccw: Switch off zPCI enhancements on older machines Revert "s390x/s390-virtio-ccw: add zpcii-disable machine property" Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-08Merge tag 'mips-20221108' of https://github.com/philmd/qemu into stagingStefan Hajnoczi6-98/+84
MIPS patches queue - Remove -Wclobbered in nanoMIPS disassembler (Richard Henderson) - Fix invalid string formats in nanoMIPS disassembler (myself) - Allow Loongson-2F to access XKPHYS in kernel mode (Jiaxun Yang) - Octeon opcode fixes (Jiaxun Yang, Pavel Dovgalyuk) - MAINTAINERS nanoMIPS update # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmNpnTYACgkQ4+MsLN6t # wN4t2A//XLIH7uL+u6kqGm45fVyy58R1NDoj2afNv5rRqIcXSrP9zRH00woLmGzs # pYLbu3yOynY2/OSU3iooAaXjQz8ub3YIpceAQdD26OgnpTrwVzKO9jvQz2UlDrzs # gETnHfqwZDBzxbqkUXxT7Pe3NRQzRmMgrMYNJm+e7UokCVy3c2PZ6vBdC5zvwS6K # LwnuEBvG74fV70D42dYay0wTB37z7m5Cf7uMp7TrEA+2HLgIZl+J9AuCmZxZZxdU # sh0AvNiVaKbHT55lazWAMvmVuUEl5zLTEUa1B0sOv081ZaY3ACBuh6Q8VpNgkgSx # qxKQbye+LtnDDYckeIRa3jI5Fs5AagC6lPPJJpiiFnMqpQaPYhNDFFjR5LNdwfQ6 # cN1lU4toi2B5LuUmiCEJrAsMgocLaNVnhwas391vtIFZh+onN/wZ1sE1Ur1kZkL7 # and2QDr2C8Y7qnpP3q8QRSz1yz+pyvTRcRIwjrnRGIgOfQUOiYeLB1RO01VOFn8u # 0Oa5gKrtClnQxMfZqoRIGucrnbZdrP/oHwsVOKUdDDNpAceVEJ0dvBiUv6WhQQ/4 # G6Ih2GJ/gJU3Ld8UliA9MCzISbvNoQ6EHYk0YqrH8B/MCzvOLbbmaZban3+xFTma # c2YGQ16ZIQsZMm00sB1Du8l9H9ms/N0VJcSx9txD2YbQWOA/bMs= # =gQ7f # -----END PGP SIGNATURE----- # gpg: Signature made Mon 07 Nov 2022 19:05:10 EST # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] # Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE * tag 'mips-20221108' of https://github.com/philmd/qemu: MAINTAINERS: Inherit from nanoMIPS disas/nanomips: Tidy read for 48-bit opcodes disas/nanomips: Split out read_u16 disas/nanomips: Merge insn{1,2,3} into words[3] disas/nanomips: Move setjmp into nanomips_dis disas/nanomips: Remove headers already included by "qemu/osdep.h" disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formats disas/nanomips: Fix invalid PRIx64 format calling img_format() disas/nanomips: Fix invalid PRId64 format calling img_format() target/mips: Don't check COP1X for 64 bit FP mode target/mips: Disable DSP ASE for Octeon68XX target/mips: Enable LBX/LWX/* instructions for Octeon target/mips: Cast offset field of Octeon BBIT to int16_t target/mips: Set CP0St_{KX, SX, UX} for Loongson-2F Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-08hw/usb: fix tab indentationAmarjargal Gundjalam7-1294/+1294
The TABs should be replaced with spaces, to make sure that we have a consistent coding style with an indentation of 4 spaces everywhere. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370 Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com> Message-Id: <6c993f57800f8fef7a910074620f6e80e077a3d1.1666707782.git.amarjargal16@gmail.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-11-08hw/display: fix tab indentationAmarjargal Gundjalam6-1509/+1509
The TABs should be replaced with spaces, to make sure that we have a consistent coding style with an indentation of 4 spaces everywhere. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370 Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com> Message-Id: <5cefd05b4d3721d416e48e6df19df18cb6338933.1666707782.git.amarjargal16@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-11-08ui: fix tab indentationAmarjargal Gundjalam4-4626/+4626
The TABs should be replaced with spaces, to make sure that we have a consistent coding style with an indentation of 4 spaces everywhere. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/370 Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Amarjargal Gundjalam <amarjargal16@gmail.com> Message-Id: <9a0d0718aafaa52029fad76a149f3200b6bba0dd.1666707782.git.amarjargal16@gmail.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-11-08s390x/s390-virtio-ccw: Switch off zPCI enhancements on older machinesCédric Le Goater1-0/+5
zPCI enhancement features (interpretation and forward assist) were recently introduced to improve performance on PCI passthrough devices. To maintain the same behaviour on older Z machines, deactivate the features with the associated properties. Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20221107161349.1032730-3-clg@kaod.org> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-11-08Revert "s390x/s390-virtio-ccw: add zpcii-disable machine property"Cédric Le Goater5-39/+2
This reverts commit 59d1ce44396e3ad2330dc3261ff3da7ad3a16184. The "zpcii-disable" machine property is redundant with the "interpret" zPCI device property. Remove it for clarification. Signed-off-by: Cédric Le Goater <clg@redhat.com> Message-Id: <20221107161349.1032730-2-clg@kaod.org> Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2022-11-08MAINTAINERS: Inherit from nanoMIPSPhilippe Mathieu-Daudé1-7/+1
6 months ago Stefan Pejic stepped in as nanoMIPS maintainer (see commit a 8e0e23445a "target/mips: Undeprecate nanoMIPS ISA support in QEMU"), however today his email is bouncing: ** Message blocked ** Your message to stefan.pejic@syrmia.com has been blocked. See technical details below for more information. The response from the remote server was: 550 5.4.1 Recipient address rejected: Access denied. AS(201806281) [DBAEUR03FT030.eop-EUR03.prod.protection.outlook.com] To avoid unmaintained code, I feel forced to merge this code back with the generic MIPS section. Historical references: - https://lore.kernel.org/qemu-devel/TY0PR03MB679726901BD6C6BE40114A2FE2A79@TY0PR03MB6797.apcprd03.prod.outlook.com/ - https://lore.kernel.org/qemu-devel/b858a20e97b74e7b90a94948314d0008@MTKMBS62N2.mediatek.inc/ Cc: Vince Del Vecchio <Vince.DelVecchio@mediatek.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <49f41916-687f-b9e5-2de7-9c658fe0d4c7@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221101114458.25756-6-philmd@linaro.org>
2022-11-08disas/nanomips: Tidy read for 48-bit opcodesRichard Henderson1-6/+6
There is no point in looking for a 48-bit opcode if we've not read the second word for a 32-bit opcode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221106023735.5277-5-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Split out read_u16Richard Henderson1-29/+19
Split out a helper function for reading a uint16_t with the correct endianness. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221106023735.5277-4-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Merge insn{1,2,3} into words[3]Richard Henderson1-23/+21
Since Disassemble wants the data in this format, collect it that way. This allows using a loop to print the bytes. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221106212852.152384-3-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Move setjmp into nanomips_disRichard Henderson1-25/+17
Reduce the number of local variables within the scope of the setjmp by moving it to the existing helper. The actual length returned from Disassemble is not used, because we have already determined the length while reading bytes. Fixes: nanomips.c: In function ‘print_insn_nanomips’: nanomips.c:21925:14: error: variable ‘insn1’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21925:25: error: variable ‘insn2’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21925:36: error: variable ‘insn3’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] nanomips.c:21926:22: error: variable ‘buf’ might be clobbered by ‘longjmp’ or ‘vfork’ [-Werror=clobbered] Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221106212852.152384-2-richard.henderson@linaro.org>
2022-11-08disas/nanomips: Remove headers already included by "qemu/osdep.h"Philippe Mathieu-Daudé1-4/+0
Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221101114458.25756-5-philmd@linaro.org>
2022-11-08disas/nanomips: Use G_GNUC_PRINTF to avoid invalid string formatsPhilippe Mathieu-Daudé1-1/+1
Suggested-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221101114458.25756-4-philmd@linaro.org>
2022-11-08disas/nanomips: Fix invalid PRIx64 format calling img_format()Philippe Mathieu-Daudé1-1/+2
Fix: disas/nanomips.c:12231:62: warning: format specifies type 'char *' but the argument has type 'uint64' (aka 'unsigned long long') [-Wformat] return img_format("RESTOREF 0x%" PRIx64 ", %s", u_value, count_value); ~~ ^~~~~~~~~~~ %llu Fixes: 4066c152b3 ("disas/nanomips: Remove IMMEDIATE functions") Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221101114458.25756-3-philmd@linaro.org>
2022-11-08disas/nanomips: Fix invalid PRId64 format calling img_format()Philippe Mathieu-Daudé1-15/+20
Fix warnings such: disas/nanomips.c:3251:64: warning: format specifies type 'char *' but the argument has type 'int64' (aka 'long long') [-Wformat] return img_format("CACHE 0x%" PRIx64 ", %s(%s)", op_value, s_value, rs); ~~ ^~~~~~~ %lld To avoid crashes such (kernel from commit f375ad6a0d): $ qemu-system-mipsel -cpu I7200 -d in_asm -kernel generic_nano32r6el_page4k ... ---------------- IN: __bzero 0x805c6084: 20c4 6950 ADDU r13, a0, a2 0x805c6088: 9089 ADDIU a0, 1 Process 70261 stopped * thread #6, stop reason = EXC_BAD_ACCESS (code=1, address=0xfffffffffffffff0) frame #0: 0x00000001bfe38864 libsystem_platform.dylib`_platform_strlen + 4 libsystem_platform.dylib`: -> 0x1bfe38864 <+4>: ldr q0, [x1] 0x1bfe38868 <+8>: adr x3, #-0xc8 ; ___lldb_unnamed_symbol314 0x1bfe3886c <+12>: ldr q2, [x3], #0x10 0x1bfe38870 <+16>: and x2, x0, #0xf Target 0: (qemu-system-mipsel) stopped. (lldb) bt * thread #6, stop reason = EXC_BAD_ACCESS (code=1, address=0xfffffffffffffff0) * frame #0: 0x00000001bfe38864 libsystem_platform.dylib`_platform_strlen + 4 frame #1: 0x00000001bfce76a0 libsystem_c.dylib`__vfprintf + 4544 frame #2: 0x00000001bfd158b4 libsystem_c.dylib`_vasprintf + 280 frame #3: 0x0000000101c22fb0 libglib-2.0.0.dylib`g_vasprintf + 28 frame #4: 0x0000000101bfb7d8 libglib-2.0.0.dylib`g_strdup_vprintf + 32 frame #5: 0x000000010000fb70 qemu-system-mipsel`img_format(format=<unavailable>) at nanomips.c:103:14 [opt] frame #6: 0x0000000100018868 qemu-system-mipsel`SB_S9_(instruction=<unavailable>, info=<unavailable>) at nanomips.c:12616:12 [opt] frame #7: 0x000000010000f90c qemu-system-mipsel`print_insn_nanomips at nanomips.c:589:28 [opt] Fixes: 4066c152b3 ("disas/nanomips: Remove IMMEDIATE functions") Reported-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221101114458.25756-2-philmd@linaro.org>
2022-11-08target/mips: Don't check COP1X for 64 bit FP modeJiaxun Yang1-1/+1
Some implementations (i.e. Loongson-2F) may decide to implement a 64 bit FPU without implementing COP1X instructions. As the eligibility of 64 bit FP instructions is already determined by CP0St_FR, there is no need to check for COP1X again. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221102165719.190378-1-jiaxun.yang@flygoat.com> [PMD: Add missing trailing parenthesis (buildfix)] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Disable DSP ASE for Octeon68XXJiaxun Yang1-2/+2
I don't have access to Octeon68XX hardware but according to my investigation Octeon never had DSP ASE support. As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual" CP0C3_DSPP is reserved bit and read as 0. Also I do have access to a Ubiquiti Edgerouter 4 which has Octeon CN7130 processor and I can confirm CP0C3_DSPP is read as 0 on that processor. Further more, in linux kernel: arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h cpu_has_dsp is overridden as 0. So I believe we shouldn't emulate DSP in QEMU as well. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <20221031132531.18122-4-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Enable LBX/LWX/* instructions for OcteonPavel Dovgalyuk1-4/+8
This patch changes condition and function name for enabling indexed load instructions for Octeon vCPUs. Octeons do not have DSP extension, but implement LBX-and-others. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <166728058455.229236.13834649461181619195.stgit@pasha-ThinkPad-X280> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Cast offset field of Octeon BBIT to int16_tJiaxun Yang1-1/+1
As per "Cavium Networks OCTEON Plus CN50XX Hardware Reference Manual" offset field is signed 16 bit value. However arg_BBIT.offset is unsigned. We need to cast it as signed to do address calculation. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20221031132531.18122-3-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-08target/mips: Set CP0St_{KX, SX, UX} for Loongson-2FJiaxun Yang1-0/+6
As per an unpublished document, in later reversion of chips CP0St_{KX, SX, UX} is not writeable and hardcoded to 1. Without those bits set, kernel is unable to access XKPHYS address segment. So just set them up on CPU reset. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221031132531.18122-2-jiaxun.yang@flygoat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2022-11-07Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu ↵Stefan Hajnoczi155-1015/+7991
into staging pci,pc,virtio: features, tests, fixes, cleanups lots of acpi rework first version of biosbits infrastructure ASID support in vhost-vdpa core_count2 support in smbios PCIe DOE emulation virtio vq reset HMAT support part of infrastructure for viommu support in vhost-vdpa VTD PASID support fixes, tests all over the place Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # -----BEGIN PGP SIGNATURE----- # # iQFDBAABCAAtFiEEXQn9CHHI+FuUyooNKB8NuNKNVGkFAmNpXDkPHG1zdEByZWRo # YXQuY29tAAoJECgfDbjSjVRpD0AH/2G8ZPrgrxJC9y3uD5/5J6QRzO+TsDYbg5ut # uBf4rKSHHzcu6zdyAfsrhbAKKzyD4HrEGNXZrBjnKM1xCiB/SGBcDIWntwrca2+s # 5Dpbi4xvd4tg6tVD4b47XNDCcn2uUbeI0e2M5QIbtCmzdi/xKbFAfl5G8DQp431X # Kmz79G4CdKWyjVlM0HoYmdCw/4FxkdjD02tE/Uc5YMrePNaEg5Bw4hjCHbx1b6ur # 6gjeXAtncm9s4sO0l+sIdyiqlxiTry9FSr35WaQ0qPU+Og5zaf1EiWfdl8TRo4qU # EAATw5A4hyw11GfOGp7oOVkTGvcNB/H7aIxD7emdWZV8+BMRPKo= # =zTCn # -----END PGP SIGNATURE----- # gpg: Signature made Mon 07 Nov 2022 14:27:53 EST # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (83 commits) checkpatch: better pattern for inline comments hw/virtio: introduce virtio_device_should_start tests/acpi: update tables for new core count test bios-tables-test: add test for number of cores > 255 tests/acpi: allow changes for core_count2 test bios-tables-test: teach test to use smbios 3.0 tables hw/smbios: add core_count2 to smbios table type 4 vhost-user: Support vhost_dev_start vhost: Change the sequence of device start intel-iommu: PASID support intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a function intel-iommu: drop VTDBus intel-iommu: don't warn guest errors when getting rid2pasid entry vfio: move implement of vfio_get_xlat_addr() to memory.c tests: virt: Update expected *.acpihmatvirt tables tests: acpi: aarch64/virt: add a test for hmat nodes with no initiators hw/arm/virt: Enable HMAT on arm virt machine tests: Add HMAT AArch64/virt empty table files tests: acpi: q35: update expected blobs *.hmat-noinitiators expected HMAT: tests: acpi: q35: add test for hmat nodes without initiators ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-07util/log: Ignore per-thread flag if global file already thereGreg Kurz1-0/+4
If QEMU is started with `-D qemu.log.%d` without any `-d` option, doing `log all` in the monitor fails with: Filename template with '%d' required for 'tid' It is confusing since '%d' was actually passed. This happens because QEMU caches the log file name with %d converted to getpid() since `tid` wasn't required. This name isn't suitable for a subsequent enablement of per-thread logs. There's little cause to change the behavior as `-d tid` is mostly used at user-only startup. Drop the per-thread from the requested flags in this case : `log all` will thus enable everything except `tid` instead of failing. This is preferable over forcing the user to enable each log item individually. With this patch, `tid` is now truely immutable : it can only be set or unset from the command line and never changed afterwards. Fixes: 4e51069d6793 ("util/log: Support per-thread log files") Cc: richard.henderson@linaro.org Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221104120059.678470-3-groug@kaod.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-07util/log: Make the per-thread flag immutableGreg Kurz1-0/+5
Per-thread logging was implemented under the assumption that once enabled, it is not possible to switch back to single file logging. This isn't enforced though and it is possible to go through the global file opening sequence in per-thread mode. The code isn't ready for this and produces unexpected results as detailed below. Start QEMU in system emulation mode with `-D ./qemu.log.%d -d tid` and then change the log level from the monitor to something that doesn't have tid, e.g. `log cpu_reset`. The value of log_flags is zero and per_thread is set to false : the rest of the code then assumes it is running in the global log case and opens a file named `qemu.log.%d`, which is obviously not an expected behavior. Enforce the immutability of the flag early in qemu_set_log_internal() so that its value is correct for all subsequent users. Fixes: 4e51069d6793 ("util/log: Support per-thread log files") Cc: richard.henderson@linaro.org Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20221104120059.678470-2-groug@kaod.org Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-07Merge tag 'pull-loongarch-20221107' of https://gitlab.com/gaosong/qemu into ↵Stefan Hajnoczi6-17/+19
staging pull-loongarch-20221107 # -----BEGIN PGP SIGNATURE----- # # iLMEAAEIAB0WIQS4/x2g0v3LLaCcbCxAov/yOSY+3wUCY2hz5gAKCRBAov/yOSY+ # 31ESA/9ppQVu70y8AnA/aYCzC6koQxxAsaD/lvwc7M1xzeZnjwOsVnsFLpZITTJj # 2+2O/BlEO3uRvAtV6E7Vtu9D/+Cc+HQ7yOFnwbY0jZmePThp3YYtTg6o+2T7/9ya # RMicgny1SYjsOjG8/Uam9+dRbH5QheNFwid0BWFhMts9MDB3Mg== # =zZ8m # -----END PGP SIGNATURE----- # gpg: Signature made Sun 06 Nov 2022 21:56:38 EST # gpg: using RSA key B8FF1DA0D2FDCB2DA09C6C2C40A2FFF239263EDF # gpg: Good signature from "Song Gao <m17746591750@163.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF * tag 'pull-loongarch-20221107' of https://gitlab.com/gaosong/qemu: target/loongarch: Fix return value of CHECK_FPE target/loongarch: Separate the hardware flags into MMU index and PLV Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-11-07checkpatch: better pattern for inline commentsMichael S. Tsirkin1-2/+4
checkpatch is unhappy about this line: WARNING: Block comments use a leading /* on a separate line #50: FILE: hw/acpi/nvdimm.c:1074: + aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? */)); but there's nothing wrong with it - the check is just too simplistic. It will also miss lines which mix inline and block comments. Instead, let's strip all inline comments from a line and then check for block comments. Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07hw/virtio: introduce virtio_device_should_startAlex Bennée8-11/+25
The previous fix to virtio_device_started revealed a problem in its use by both the core and the device code. The core code should be able to handle the device "starting" while the VM isn't running to handle the restoration of migration state. To solve this duel use introduce a new helper for use by the vhost-user backends who all use it to feed a should_start variable. We can also pick up a change vhost_user_blk_set_status while we are at it which follows the same pattern. Fixes: 9f6bcfd99f (hw/virtio: move vm_running check to virtio_device_started) Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: "Michael S. Tsirkin" <mst@redhat.com> Message-Id: <20221107121407.1010913-1-alex.bennee@linaro.org>
2022-11-07tests/acpi: update tables for new core count testJulia Suvorova4-3/+0
Changes in the tables (for 275 cores): FACP: + Use APIC Cluster Model (V4) : 1 APIC: +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 ... + +[81Ch 2076 1] Subtable Type : 00 [Processor Local APIC] +[81Dh 2077 1] Length : 08 +[81Eh 2078 1] Processor ID : FE +[81Fh 2079 1] Local Apic ID : FE +[820h 2080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[824h 2084 1] Subtable Type : 09 [Processor Local x2APIC] +[825h 2085 1] Length : 10 +[826h 2086 2] Reserved : 0000 +[828h 2088 4] Processor x2Apic ID : 000000FF +[82Ch 2092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[830h 2096 4] Processor UID : 000000FF ... DSDT: + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + } ... + Processor (C0FE, 0xFE, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0xFE)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0xFE, 0xFE, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0xFE) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0xFE, Arg0, Arg1, Arg2) + } + } + + Device (C0FF) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, 0xFF) // _UID: Unique ID + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0xFF)) + } + + Name (_MAT, Buffer (0x10) // _MAT: Multiple APIC Table Entry + { + /* 0000 */ 0x09, 0x10, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x01, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0xFF) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0xFF, Arg0, Arg1, Arg2) + } + } + ... Signed-off-by: Julia Suvorova <jusual@redhat.com> Message-Id: <20220731162141.178443-6-jusual@redhat.com> Message-Id: <20221011111731.101412-6-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07bios-tables-test: add test for number of cores > 255Julia Suvorova1-13/+45
The new test is run with a large number of cpus and checks if the core_count field in smbios_cpu_test (structure type 4) is correct. Choose q35 as it allows to run with -smp > 255. Signed-off-by: Julia Suvorova <jusual@redhat.com> Message-Id: <20220731162141.178443-5-jusual@redhat.com> Message-Id: <20221011111731.101412-5-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com>
2022-11-07tests/acpi: allow changes for core_count2 testJulia Suvorova4-0/+3
Signed-off-by: Julia Suvorova <jusual@redhat.com> Message-Id: <20220731162141.178443-4-jusual@redhat.com> Message-Id: <20221011111731.101412-4-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Acked-by: Igor Mammedov <imammedo@redhat.com>
2022-11-07bios-tables-test: teach test to use smbios 3.0 tablesJulia Suvorova1-24/+76
Introduce the 64-bit entry point. Since we no longer have a total number of structures, stop checking for the new ones at the EOF structure (type 127). Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220731162141.178443-3-jusual@redhat.com> Message-Id: <20221011111731.101412-3-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07hw/smbios: add core_count2 to smbios table type 4Julia Suvorova3-5/+35
In order to use the increased number of cpus, we need to bring smbios tables in line with the SMBIOS 3.0 specification. This allows us to introduce core_count2 which acts as a duplicate of core_count if we have fewer cores than 256, and contains the actual core number per socket if we have more. core_enabled2 and thread_count2 fields work the same way. Signed-off-by: Julia Suvorova <jusual@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220731162141.178443-2-jusual@redhat.com> Message-Id: <20221011111731.101412-2-jusual@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07vhost-user: Support vhost_dev_startYajun Wu1-1/+73
The motivation of adding vhost-user vhost_dev_start support is to improve backend configuration speed and reduce live migration VM downtime. Today VQ configuration is issued one by one. For virtio net with multi-queue support, backend needs to update RSS (Receive side scaling) on every rx queue enable. Updating RSS is time-consuming (typical time like 7ms). Implement already defined vhost status and message in the vhost specification [1]. (a) VHOST_USER_PROTOCOL_F_STATUS (b) VHOST_USER_SET_STATUS (c) VHOST_USER_GET_STATUS Send message VHOST_USER_SET_STATUS with VIRTIO_CONFIG_S_DRIVER_OK for device start and reset(0) for device stop. On reception of the DRIVER_OK message, backend can apply the needed setting only once (instead of incremental) and also utilize parallelism on enabling queues. This improves QEMU's live migration downtime with vhost user backend implementation by great margin, specially for the large number of VQs of 64 from 800 msec to 250 msec. [1] https://qemu-project.gitlab.io/qemu/interop/vhost-user.html Signed-off-by: Yajun Wu <yajunw@nvidia.com> Acked-by: Parav Pandit <parav@nvidia.com> Message-Id: <20221017064452.1226514-3-yajunw@nvidia.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07vhost: Change the sequence of device startYajun Wu2-13/+16
This patch is part of adding vhost-user vhost_dev_start support. The motivation is to improve backend configuration speed and reduce live migration VM downtime. Moving the device start routines after finishing all the necessary device and VQ configuration, further aligning to the virtio specification for "device initialization sequence". Following patch will add vhost-user vhost_dev_start support. Signed-off-by: Yajun Wu <yajunw@nvidia.com> Acked-by: Parav Pandit <parav@nvidia.com> Message-Id: <20221017064452.1226514-2-yajunw@nvidia.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07intel-iommu: PASID supportJason Wang5-104/+341
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the existing support for scalable mode, we need to implement the following missing parts: 1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation with PASID 2) tag IOTLB with PASID 3) PASID cache and its flush 4) PASID based IOTLB invalidation For simplicity PASID cache is not implemented so we can simply implement the PASID cache flush as a no and leave it to be implemented in the future. For PASID based IOTLB invalidation, since we haven't had L1 stage support, the PASID based IOTLB invalidation is not implemented yet. For PASID based device IOTLB invalidation, it requires the support for vhost so we forbid enabling device IOTLB when PASID is enabled now. Those work could be done in the future. Note that though PASID based IOMMU translation is ready but no device can issue PASID DMA right now. In this case, PCI_NO_PASID is used as PASID to identify the address without PASID. vtd_find_add_as() has been extended to provision address space with PASID which could be utilized by the future extension of PCI core to allow device model to use PASID based DMA translation. This feature would be useful for: 1) prototyping PASID support for devices like virtio 2) future vPASID work 3) future PRS and vSVA work Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221028061436.30093-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07intel-iommu: convert VTD_PE_GET_FPD_ERR() to be a functionJason Wang1-14/+28
We used to have a macro for VTD_PE_GET_FPD_ERR() but it has an internal goto which prevents it from being reused. This patch convert that macro to a dedicated function and let the caller to decide what to do (e.g using goto or not). This makes sure it can be re-used for other function that requires fault reporting. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221028061436.30093-4-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
2022-11-07intel-iommu: drop VTDBusJason Wang2-127/+118
We introduce VTDBus structure as an intermediate step for searching the address space. This works well with SID based matching/lookup. But when we want to support SID plus PASID based address space lookup, this intermediate steps turns out to be a burden. So the patch simply drops the VTDBus structure and use the PCIBus and devfn as the key for the g_hash_table(). This simplifies the codes and the future PASID extension. To prevent being slower for past vtd_find_as_from_bus_num() callers, a vtd_as cache indexed by the bus number is introduced to store the last recent search result of a vtd_as belongs to a specific bus. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221028061436.30093-3-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
2022-11-07intel-iommu: don't warn guest errors when getting rid2pasid entryJason Wang1-6/+6
We use to warn on wrong rid2pasid entry. But this error could be triggered by the guest and could happens during initialization. So let's don't warn in this case. Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221028061436.30093-2-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Yi Liu <yi.l.liu@intel.com>
2022-11-07vfio: move implement of vfio_get_xlat_addr() to memory.cCindy Lu3-61/+81
- Move the implement vfio_get_xlat_addr to softmmu/memory.c, and change the name to memory_get_xlat_addr(). So we can use this function on other devices, such as vDPA device. - Add a new function vfio_get_xlat_addr in vfio/common.c, and it will check whether the memory is backed by a discard manager. then device can have its own warning. Signed-off-by: Cindy Lu <lulu@redhat.com> Message-Id: <20221031031020.1405111-2-lulu@redhat.com> Acked-by: Alex Williamson <alex.williamson@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07tests: virt: Update expected *.acpihmatvirt tablesHesham Almatary6-5/+0
* Expected ACPI Data Table [HMAT] [000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] [004h 0004 4] Table Length : 00000120 [008h 0008 1] Revision : 02 [009h 0009 1] Checksum : 4F [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Reserved : 00000000 [028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [02Ah 0042 2] Reserved : 0000 [02Ch 0044 4] Length : 00000028 [030h 0048 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [032h 0050 2] Reserved1 : 0000 [034h 0052 4] Processor Proximity Domain : 00000000 [038h 0056 4] Memory Proximity Domain : 00000000 [03Ch 0060 4] Reserved2 : 00000000 [040h 0064 8] Reserved3 : 0000000000000000 [048h 0072 8] Reserved4 : 0000000000000000 [050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [052h 0082 2] Reserved : 0000 [054h 0084 4] Length : 00000028 [058h 0088 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [05Ah 0090 2] Reserved1 : 0000 [05Ch 0092 4] Processor Proximity Domain : 00000001 [060h 0096 4] Memory Proximity Domain : 00000001 [064h 0100 4] Reserved2 : 00000000 [068h 0104 8] Reserved3 : 0000000000000000 [070h 0112 8] Reserved4 : 0000000000000000 [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 [080h 0128 2] Flags (decoded below) : 0000 Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 [084h 0132 4] Processor Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [040h 0064 8] Reserved3 : 0000000000000000 [048h 0072 8] Reserved4 : 0000000000000000 [050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [052h 0082 2] Reserved : 0000 [054h 0084 4] Length : 00000028 [058h 0088 2] Flags (decoded below) : 0001 Processor Proximity Domain Valid : 1 [05Ah 0090 2] Reserved1 : 0000 [05Ch 0092 4] Processor Proximity Domain : 00000001 [060h 0096 4] Memory Proximity Domain : 00000001 [064h 0100 4] Reserved2 : 00000000 [068h 0104 8] Reserved3 : 0000000000000000 [070h 0112 8] Reserved4 : 0000000000000000 [078h 0120 2] Structure Type : 0000 [Memory Proximity Domain Attributes] [07Ah 0122 2] Reserved : 0000 [07Ch 0124 4] Length : 00000028 [080h 0128 2] Flags (decoded below) : 0000 Processor Proximity Domain Valid : 0 [082h 0130 2] Reserved1 : 0000 [084h 0132 4] Processor Proximity Domain : 00000080 [088h 0136 4] Memory Proximity Domain : 00000002 [08Ch 0140 4] Reserved2 : 00000000 [090h 0144 8] Reserved3 : 0000000000000000 [098h 0152 8] Reserved4 : 0000000000000000 [0A0h 0160 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] [0A2h 0162 2] Reserved : 0000 [0A4h 0164 4] Length : 00000040 [0A8h 0168 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0A9h 0169 1] Data Type : 00 [0AAh 0170 2] Reserved1 : 0000 [0ACh 0172 4] Initiator Proximity Domains # : 00000002 [0B0h 0176 4] Target Proximity Domains # : 00000003 [0B4h 0180 4] Reserved2 : 00000000 [0B8h 0184 8] Entry Base Unit : 0000000000002710 [0C0h 0192 4] Initiator Proximity Domain List : 00000000 [0C4h 0196 4] Initiator Proximity Domain List : 00000001 [0C8h 0200 4] Target Proximity Domain List : 00000000 [0CCh 0204 4] Target Proximity Domain List : 00000001 [0D0h 0208 4] Target Proximity Domain List : 00000002 [0D4h 0212 2] Entry : 0001 [0D6h 0214 2] Entry : 0002 [0D8h 0216 2] Entry : 0003 [0DAh 0218 2] Entry : 0002 [0DCh 0220 2] Entry : 0001 [0DEh 0222 2] Entry : 0003 [0E0h 0224 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] [0E2h 0226 2] Reserved : 0000 [0E4h 0228 4] Length : 00000040 [0E8h 0232 1] Flags (decoded below) : 00 Memory Hierarchy : 0 [0E9h 0233 1] Data Type : 03 [0EAh 0234 2] Reserved1 : 0000 [0ECh 0236 4] Initiator Proximity Domains # : 00000002 [0F0h 0240 4] Target Proximity Domains # : 00000003 [0F4h 0244 4] Reserved2 : 00000000 [0F8h 0248 8] Entry Base Unit : 0000000000000001 [100h 0256 4] Initiator Proximity Domain List : 00000000 [104h 0260 4] Initiator Proximity Domain List : 00000001 [108h 0264 4] Target Proximity Domain List : 00000000 [10Ch 0268 4] Target Proximity Domain List : 00000001 [110h 0272 4] Target Proximity Domain List : 00000002 [114h 0276 2] Entry : 000A [116h 0278 2] Entry : 0005 [118h 0280 2] Entry : 0001 [11Ah 0282 2] Entry : 0005 [11Ch 0284 2] Entry : 000A [11Eh 0286 2] Entry : 0001 Raw Table Data: Length 288 (0x120) 0000: 48 4D 41 54 20 01 00 00 02 4F 42 4F 43 48 53 20 // HMAT ....OBOCHS 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0050: 00 00 00 00 28 00 00 00 01 00 00 00 01 00 00 00 // ....(........... 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 0070: 00 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... 0080: 00 00 00 00 80 00 00 00 02 00 00 00 00 00 00 00 // ................ 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ 00A0: 01 00 00 00 40 00 00 00 00 00 00 00 02 00 00 00 // ....@........... 00B0: 03 00 00 00 00 00 00 00 10 27 00 00 00 00 00 00 // .........'...... 00C0: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................ 00D0: 02 00 00 00 01 00 02 00 03 00 02 00 01 00 03 00 // ................ 00E0: 01 00 00 00 40 00 00 00 00 03 00 00 02 00 00 00 // ....@........... 00F0: 03 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 // ................ 0100: 00 00 00 00 01 00 00 00 00 00 00 00 01 00 00 00 // ................ 0110: 02 00 00 00 0A 00 05 00 01 00 05 00 0A 00 01 00 // ................ Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com> Message-Id: <20221027100037.251-9-hesham.almatary@huawei.com> Tested-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07tests: acpi: aarch64/virt: add a test for hmat nodes with no initiatorsHesham Almatary1-0/+59
This patch imitates the "tests: acpi: q35: add test for hmat nodes without initiators" commit to test numa nodes with different HMAT attributes, but on AArch64/virt. Tested with: qemu-system-aarch64 -accel tcg \ -machine virt,hmat=on,gic-version=3 -cpu cortex-a57 \ -bios qemu-efi-aarch64/QEMU_EFI.fd \ -kernel Image -append "root=/dev/vda2 console=ttyAMA0" \ -drive if=virtio,file=aarch64.qcow2,format=qcow2,id=hd \ -device virtio-rng-pci \ -net user,hostfwd=tcp::10022-:22 -net nic \ -device intel-hda -device hda-duplex -nographic \ -smp 4 \ -m 3G \ -object memory-backend-ram,size=1G,id=ram0 \ -object memory-backend-ram,size=1G,id=ram1 \ -object memory-backend-ram,size=1G,id=ram2 \ -numa node,nodeid=0,memdev=ram0,cpus=0-1 \ -numa node,nodeid=1,memdev=ram1,cpus=2-3 \ -numa node,nodeid=2,memdev=ram2 \ -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-latency,latency=10 \ -numa hmat-lb,initiator=0,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \ -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-latency,latency=20 \ -numa hmat-lb,initiator=0,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \ -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-latency,latency=30 \ -numa hmat-lb,initiator=0,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 \ -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-latency,latency=20 \ -numa hmat-lb,initiator=1,target=0,hierarchy=memory,data-type=access-bandwidth,bandwidth=5242880 \ -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-latency,latency=10 \ -numa hmat-lb,initiator=1,target=1,hierarchy=memory,data-type=access-bandwidth,bandwidth=10485760 \ -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-latency,latency=30 \ -numa hmat-lb,initiator=1,target=2,hierarchy=memory,data-type=access-bandwidth,bandwidth=1048576 Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com> Message-Id: <20221027100037.251-8-hesham.almatary@huawei.com> Tested-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-11-07hw/arm/virt: Enable HMAT on arm virt machineXiang Chen2-0/+8
Since the patchset ("Build ACPI Heterogeneous Memory Attribute Table (HMAT)"), HMAT is supported, but only x86 is enabled. Enable HMAT on arm virt machine. Signed-off-by: Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by: Hesham Almatary <hesham.almatary@huawei.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20221027100037.251-7-hesham.almatary@huawei.com> Tested-by: Yicong Yang <yangyicong@hisilicon.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.1 at 2024-09-01 09:39:33 +0000