| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2021-05-25 | target/arm: Implement SVE2 SPLICE, EXT | Stephen Long | 2 | -7/+39 |
| 2021-05-25 | target/arm: Implement SVE2 FMMLA | Stephen Long | 5 | -0/+125 |
| 2021-05-25 | target/arm: Implement SVE2 gather load insns | Stephen Long | 2 | -0/+19 |
| 2021-05-25 | target/arm: Implement SVE2 scatter store insns | Stephen Long | 2 | -0/+18 |
| 2021-05-25 | target/arm: Implement SVE2 XAR | Richard Henderson | 8 | -21/+172 |
| 2021-05-25 | target/arm: Implement SVE2 HISTCNT, HISTSEG | Stephen Long | 4 | -0/+163 |
| 2021-05-25 | target/arm: Implement SVE2 RSUBHNB, RSUBHNT | Stephen Long | 4 | -0/+22 |
| 2021-05-25 | target/arm: Implement SVE2 SUBHNB, SUBHNT | Stephen Long | 4 | -0/+23 |
| 2021-05-25 | target/arm: Implement SVE2 RADDHNB, RADDHNT | Stephen Long | 4 | -0/+22 |
| 2021-05-25 | target/arm: Implement SVE2 ADDHNB, ADDHNT | Stephen Long | 4 | -0/+62 |
| 2021-05-25 | target/arm: Implement SVE2 complex integer multiply-add | Richard Henderson | 6 | -8/+113 |
| 2021-05-25 | target/arm: Implement SVE2 integer multiply-add long | Richard Henderson | 4 | -0/+133 |
| 2021-05-25 | target/arm: Implement SVE2 saturating multiply-add high | Richard Henderson | 4 | -6/+195 |
| 2021-05-25 | target/arm: Implement SVE2 saturating multiply-add long | Richard Henderson | 4 | -0/+112 |
| 2021-05-25 | target/arm: Implement SVE2 MATCH, NMATCH | Stephen Long | 4 | -0/+101 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise ternary operations | Richard Henderson | 4 | -0/+281 |
| 2021-05-25 | target/arm: Implement SVE2 WHILERW, WHILEWR | Richard Henderson | 2 | -0/+70 |
| 2021-05-25 | target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS | Richard Henderson | 4 | -17/+82 |
| 2021-05-25 | target/arm: Implement SVE2 SQSHRN, SQRSHRN | Richard Henderson | 4 | -0/+149 |
| 2021-05-25 | target/arm: Implement SVE2 UQSHRN, UQRSHRN | Richard Henderson | 4 | -0/+137 |
| 2021-05-25 | target/arm: Implement SVE2 SQSHRUN, SQRSHRUN | Richard Henderson | 4 | -0/+153 |
| 2021-05-25 | target/arm: Implement SVE2 SHRN, RSHRN | Richard Henderson | 4 | -2/+236 |
| 2021-05-25 | target/arm: Implement SVE2 floating-point pairwise | Stephen Long | 4 | -0/+114 |
| 2021-05-25 | target/arm: Implement SVE2 saturating extract narrow | Richard Henderson | 4 | -0/+330 |
| 2021-05-25 | target/arm: Implement SVE2 integer absolute difference and accumulate | Richard Henderson | 2 | -0/+27 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift and insert | Richard Henderson | 2 | -0/+15 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift right and accumulate | Richard Henderson | 2 | -0/+42 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract long with carry | Richard Henderson | 4 | -0/+66 |
| 2021-05-25 | target/arm: Implement SVE2 integer absolute difference and accumulate long | Richard Henderson | 4 | -0/+104 |
| 2021-05-25 | target/arm: Implement SVE2 complex integer add | Richard Henderson | 4 | -0/+92 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise permute | Richard Henderson | 5 | -0/+135 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise exclusive-or interleaved | Richard Henderson | 4 | -0/+49 |
| 2021-05-25 | target/arm: Implement SVE2 bitwise shift left long | Richard Henderson | 4 | -0/+197 |
| 2021-05-25 | target/arm: Implement SVE2 PMULLB, PMULLT | Richard Henderson | 5 | -0/+59 |
| 2021-05-25 | target/arm: Implement SVE2 integer multiply long | Richard Henderson | 4 | -0/+64 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract wide | Richard Henderson | 4 | -0/+78 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract interleaved long | Richard Henderson | 2 | -0/+10 |
| 2021-05-25 | target/arm: Implement SVE2 integer add/subtract long | Richard Henderson | 4 | -0/+132 |
| 2021-05-25 | target/arm: Implement SVE2 saturating add/subtract (predicated) | Richard Henderson | 4 | -56/+210 |
| 2021-05-25 | target/arm: Implement SVE2 integer pairwise arithmetic | Richard Henderson | 4 | -0/+135 |
| 2021-05-25 | target/arm: Implement SVE2 integer halving add/subtract (predicated) | Richard Henderson | 4 | -0/+112 |
| 2021-05-25 | target/arm: Implement SVE2 saturating/rounding bitwise shift left (predicated) | Richard Henderson | 4 | -0/+176 |
| 2021-05-25 | target/arm: Split out saturating/rounding shifts from neon | Richard Henderson | 2 | -430/+227 |
| 2021-05-25 | target/arm: Implement SVE2 integer unary operations (predicated) | Richard Henderson | 4 | -0/+88 |
| 2021-05-25 | target/arm: Implement SVE2 integer pairwise add and accumulate long | Richard Henderson | 4 | -0/+102 |
| 2021-05-25 | target/arm: Implement SVE2 Integer Multiply - Unpredicated | Richard Henderson | 4 | -0/+166 |
| 2021-05-25 | target/arm: Add ID_AA64ZFR0 fields and isar_feature_aa64_sve2 | Richard Henderson | 3 | -8/+32 |
| 2021-05-25 | disas/libvixl: Protect C system header for C++ compiler | Philippe Mathieu-Daudé | 6 | -11/+15 |
| 2021-05-25 | target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type | Rebecca Cran | 1 | -0/+1 |
| 2021-05-25 | target/arm: Add support for FEAT_TLBIOS | Rebecca Cran | 2 | -0/+48 |
