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2024-06-26target/riscv: Add Zc extension implied ruleFrank Chang1-0/+34
Zc extension has special implied rules that need to be handled separately. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-6-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add multi extension implied rulesFrank Chang1-0/+340
Add multi extension implied rules to enable the implied extensions of the multi extension recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add MISA extension implied rulesFrank Chang1-1/+49
Add MISA extension implied rules to enable the implied extensions of MISA recursively. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Introduce extension implied rule helpersFrank Chang1-0/+121
Introduce helpers to enable the extensions based on the implied rules. The implied extensions are enabled recursively, so we don't have to expand all of them manually. This also eliminates the old-fashioned ordering requirement. For example, Zvksg implies Zvks, Zvks implies Zvksed, etc., removing the need to check the implied rules of Zvksg before Zvks. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240625114629.27793-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Introduce extension implied rules definitionFrank Chang2-0/+31
RISCVCPUImpliedExtsRule is created to store the implied rules. 'is_misa' flag is used to distinguish whether the rule is derived from the MISA or other extensions. 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it stores the offset of the extension defined in RISCVCPUConfig. 'ext' will also serve as the key of the hash tables to look up the rule in the following commit. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Tested-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240625114629.27793-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: fix instructions count handling in icount modeClément Léger1-13/+17
When icount is enabled, rather than returning the virtual CPU time, we should return the instruction count itself. Add an instructions bool parameter to get_ticks() to correctly return icount_get_raw() when icount_enabled() == 1 and instruction count is queried. This will modify the existing behavior which was returning an instructions count close to the number of cycles (CPI ~= 1). Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Message-ID: <20240618112649.76683-1-cleger@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Fix froundnx.h nanbox checkBranislav Brzak1-1/+1
helper_froundnx_h function mistakenly uses single percision nanbox check instead of the half percision one. This patch fixes the issue. Signed-off-by: Branislav Brzak <brzakbranislav@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20240608214546.226963-1-brzakbranislav@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: Make block devices default to virtioSunil V L1-0/+2
RISC-V virt is currently missing default type for block devices. Without this being set, proper backend is not created when option like -cdrom is used. So, make the virt board's default block device type be IF_VIRTIO similar to other architectures. We also need to set no_cdrom to avoid getting a default cdrom device. Signed-off-by: Sunil V L <sunilvl@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240620064718.275427-1-sunilvl@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Support the version for ss1p13Fea.Wang2-1/+9
Add RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Message-ID: <20240606135454.119186-7-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Reserve exception codes for sw-check and hw-errFea.Wang1-0/+2
Based on the priv-1.13.0, add the exception codes for Software-check and Hardware-error. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-6-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add MEDELEGH, HEDELEGH csrs for RV32Fea.Wang2-0/+33
Based on privileged spec 1.13, the RV32 needs to implement MEDELEGH and HEDELEGH for exception codes 32-47 for reserving and exception codes 48-63 for custom use. Add the CSR number though the implementation is just reading zero and writing ignore. Besides, for accessing HEDELEGH, it should be controlled by mstateen0 'P1P13' bit. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-5-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Add 'P1P13' bit in SMSTATEEN0Fea.Wang2-0/+9
Based on privilege 1.13 spec, there should be a bit56 for 'P1P13' in mstateen0 that controls access to the hedeleg. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-4-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Define macros and variables for ss1p13Fea.Wang2-1/+4
Add macros and variables for RISC-V privilege 1.13 support. Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liwei1518@gmail.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-3-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Reuse the conversion function of priv_specJim Shu3-10/+6
Public the conversion function of priv_spec in cpu.h, so that tcg-cpu.c could also use it. Signed-off-by: Jim Shu <jim.shu@sifive.com> Signed-off-by: Fea.Wang <fea.wang@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606135454.119186-2-fea.wang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv/kvm: define TARGET_KVM_HAVE_GUEST_DEBUGChao Du1-0/+1
To enable the KVM GUEST DEBUG for RISC-V at QEMU side. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-4-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv/kvm: handle the exit with debug reasonChao Du1-0/+20
If the breakpoint belongs to the userspace then set the ret value. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-3-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv/kvm: add software breakpoints supportChao Du1-0/+69
This patch implements insert/remove software breakpoint process. For RISC-V, GDB treats single-step similarly to breakpoint: add a breakpoint at the next step address, then continue. So this also works for single-step debugging. Implement kvm_arch_update_guest_debug(): Set the control flag when there are active breakpoints. This will help KVM to know the status in the userspace. Add some stubs which are necessary for building, and will be implemented later. Signed-off-by: Chao Du <duchao@eswincomputing.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240606014501.20763-2-duchao@eswincomputing.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: imsics DT: add '#msi-cells'Daniel Henrique Barboza1-0/+1
The DT docs for riscv,imsics [1] requires a 'msi-cell' property. Add one and set it zero. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240531202759.911601-9-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: imsics DT: add 'qemu, imsics' to 'compatible'Daniel Henrique Barboza1-1/+7
The DT docs for riscv,imsics [1] predicts a 'qemu,imsics' enum in the 'compatible' property. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-8-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: change imsic nodename to 'interrupt-controller'Daniel Henrique Barboza1-1/+2
The Linux DT docs for imsic [1] predicts an 'interrupt-controller@addr' node, not 'imsic@addr', given this node inherits the 'interrupt-controller' node. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: 28d8c281200f ("hw/riscv: virt: Add optional AIA IMSIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-7-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: aplic DT: rename prop to 'riscv, delegation'Daniel Henrique Barboza1-1/+1
The DT docs for riscv,aplic [1] predicts a 'riscv,delegation' property. Not 'riscv,delegate'. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-6-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: aplic DT: add 'qemu, aplic' to 'compatible'Daniel Henrique Barboza1-1/+6
The DT docs for riscv,aplic [1] predicts a 'qemu,aplic' enum in the 'compatible' property. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-5-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: rename aplic nodename to 'interrupt-controller'Daniel Henrique Barboza1-1/+1
The correct name of the aplic controller node, as per Linux kernel DT docs [1], is 'interrupt-controller@addr'. [1] Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml Reported-by: Conor Dooley <conor@kernel.org> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-4-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: add aplic nodename helperDaniel Henrique Barboza1-5/+8
We'll change the aplic DT nodename in the next patch and the name is hardcoded in 2 different functions. Create a helper to change a single place later. While we're at it, in create_fdt_socket_aplic(), move 'aplic_name' inside the conditional to avoid allocating a string that won't be used when socket == NULL. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-3-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26hw/riscv/virt.c: add address-cells in create_fdt_one_aplic()Daniel Henrique Barboza2-0/+3
We need #address-cells properties in all interrupt controllers that are referred by an interrupt-map [1]. For the RISC-V machine, both PLIC and APLIC controllers must have this property. PLIC already sets it in create_fdt_socket_plic(). Set the property for APLIC in create_fdt_one_aplic(). [1] https://lore.kernel.org/linux-arm-kernel/CAL_JsqJE15D-xXxmELsmuD+JQHZzxGzdXvikChn6KFWqk6NzPw@mail.gmail.com/ Suggested-by: Anup Patel <apatel@ventanamicro.com> Fixes: e6faee65855b ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240531202759.911601-2-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: zvbb implies zvkbJerry Zhang Jian1-0/+4
According to RISC-V crypto spec, Zvkb extension is a subset of the Zvbb extension [1]. 1: https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10 Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240528130349.20193-1-jerry.zhangjian@sifive.com> [ Changes by AF: - Tidy up commit message - Rebase ] Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Move Guest irqs out of the core local irqs range.Rajnesh Kanwal2-2/+10
Qemu maps IRQs 0:15 for core interrupts and 16 onward for guest interrupts which are later translated to hgiep in `riscv_cpu_set_irq()` function. With virtual IRQ support added, software now can fully use the whole local interrupt range without any actual hardware attached. This change moves the guest interrupt range after the core local interrupt range to avoid clash. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240520125157.311503-3-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-26target/riscv: Extend virtual irq csrs masks to be 64 bit wide.Rajnesh Kanwal1-7/+7
AIA extends the width of all IRQ CSRs to 64bit even in 32bit systems by adding missing half CSRs. This seems to be missed while adding support for virtual IRQs. The whole logic seems to be correct except the width of the masks. Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240520125157.311503-2-rkanwal@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2024-06-24Merge tag 'pull-vfio-20240624' of https://github.com/legoater/qemu into stagingRichard Henderson24-378/+1066
vfio queue: * Add a host IOMMU device abstraction * VIRTIO-IOMMU/VFIO: Fix host iommu geometry handling * QOMify VFIOContainer # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmZ541QACgkQUaNDx8/7 # 7KFdnQ/8Dih3HI2qtY93bTxg0lmJ+ZMibojTkEkTu3kSvwoI12wkiSMFKzzTWpZE # UtGyIqQQij8IfQtIz87uQskv7oFiZKG6JWMTAX4uJ8ZIgZiih29/e/38VGEbogBh # yO+1Pqr3ETlyLnQcu9ruBTJ293LXovmD4d9feoaVdURBNZ1EqIh7sv/y7YdUsR+i # tXa6kW1ZIlKBI54o/uuODHWQYyOHs39VtZ6JZvgxVVEQsNikcJsosK9ts9A1EByi # 0roQVXm2QAK/nPXlmMGLvJWzQcdeXQ6W6hzYkO2HqGnCLURnpW+y/ZVbNcxGOOiU # 2G6L0TASlqA3yqCJeLuZZqjM6S2VbnvrA8omyg4QnygIHppYjp2CdcCmUpg6wfze # rkgbVLNasX+le4ss2emuHPh55dLDP20yW83DeGeqSgE//foaJWhtOK/cnvs04zV2 # D6oSAVsOsZ6ozYlQckYnaxIBANDKLRnzCXVZLUCmHxCUhxHuiNJUsHfZYIv/Zxen # C5ZjD/JPgx3onkoKbNfTRTgwOCdXhVPjWnnp7Su49jymsekqdk1ntln4ixDT3Vol # ghQPQLjICBc8qXiOJAcFDwqLf/telPlzUUzvlDeC4BYMnpBAP6rQ3JJ8i0vCCiWv # zKCtmbcDqDRMDpWyJWM3XA/kVKP9i2tNa1R/ej2SleCFLgRapBw= # =3koe # -----END PGP SIGNATURE----- # gpg: Signature made Mon 24 Jun 2024 02:21:24 PM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [undefined] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * tag 'pull-vfio-20240624' of https://github.com/legoater/qemu: (42 commits) vfio/container: Move vfio_container_destroy() to an instance_finalize() handler vfio/container: Introduce vfio_iommu_legacy_instance_init() vfio/container: Remove vfio_container_init() vfio/container: Remove VFIOContainerBase::ops vfio/container: Introduce an instance_init() handler vfio/container: Switch to QOM vfio/container: Change VFIOContainerBase to use QOM vfio/container: Discover IOMMU type before creating the container vfio/container: Introduce vfio_create_container() vfio/container: Introduce vfio_get_iommu_class_name() vfio/container: Modify vfio_get_iommu_type() to use a container fd vfio/container: Simplify vfio_container_init() vfio/container: Introduce vfio_address_space_insert() vfio/common: Extract vIOMMU code from vfio_sync_dirty_bitmap() vfio/common: Move dirty tracking ranges update to helper vfio: Remove unused declarations from vfio-common.h vfio: Make vfio_devices_dma_logging_start() return bool memory: Remove IOMMU MR iommu_set_iova_range API hw/vfio: Remove memory_region_iommu_set_iova_ranges() call virtio-iommu: Remove the implementation of iommu_set_iova_range ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-24Merge tag 'sdmmc-20240624' of https://github.com/philmd/qemu into stagingRichard Henderson4-105/+150
SD/MMC patches queue One fix and various cleanups for the SD card model. # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEE+qvnXhKRciHc/Wuy4+MsLN6twN4FAmZ5cRUACgkQ4+MsLN6t # wN59Qw//cUdjD287pB5Ml5aQqr9sOTyVnHUceZtz7AOZ5w8RM2tlPDgOImeLOvU6 # OV7qfWvNaUxtQxhfh5jpe8Pj4eHBtRQzA6a1AWToEvnN4189QWHZpqf5TUa4AlFS # uAk7k2TkoNv9zbNKca0bP3L1x6sT9l0VPZBLaLbgdXDIX2ycD0r3NVQxXb/bJRgM # 6pFRcLCF/isKzLQDwqnTa11hB/JDTvOU7xnY0kazGRvyWjbSvE2sOJzLNJXHkW0I # /FNfRbOKJo2t+47Z5qSXUFFLeIEBTy7VqNBsOQ6sMIgrWzbOSrtBcuxKp0p9NCGH # fdZHlDVRnNGXewUya4RjbmXiCNuGL4zJ82b2BaQZVd5ZwU2opIr8xO96WCojQ4dZ # +Dq3uv7su3PUVOh95i38Eo93OG9jXFx642XD4q2uKu5j70IoGXAkIoLUcFkZZdGS # 9rCsaNUHyHJrN6nXf3Cekvkqxz36p6QXaUF9I1vB0JF6CrexMD35sBUK+RE9k4uW # LnqL7ZwQDGDGVl3kPS/VCXv1mMim4aRLSEIveq7Ui6dKzaaJMIIodZ8CFMuyTTsD # cGE+Cd053nf6SzX3+kEZftNdjtJ906O8xIAw+RNdARYx003l4kUxgsPDk7ELyzIP # Tb+VlZl2P+ROJmeWvRMTW7ZQ49M9IEMrg8zlGF4hLCxB1JndeOA= # =O5er # -----END PGP SIGNATURE----- # gpg: Signature made Mon 24 Jun 2024 06:13:57 AM PDT # gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE # gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full] * tag 'sdmmc-20240624' of https://github.com/philmd/qemu: hw/sd/sdcard: Add comments around registers and commands hw/sd/sdcard: Inline BLK_READ_BLOCK / BLK_WRITE_BLOCK macros hw/sd/sdcard: Add sd_invalid_mode_for_cmd to report invalid mode switch hw/sd/sdcard: Only call sd_req_get_address() where address is used hw/sd/sdcard: Factor sd_req_get_address() method out hw/sd/sdcard: Only call sd_req_get_rca() where RCA is used hw/sd/sdcard: Factor sd_req_get_rca() method out hw/sd/sdcard: Have cmd_valid_while_locked() return a boolean value hw/sd/sdcard: Trace update of block count (CMD23) hw/sd/sdcard: Remove explicit entries for illegal commands hw/sd/sdcard: Remove ACMD6 handler for SPI mode hw/sd/sdcard: Use Load/Store API to fill some CID/CSD registers hw/sd/sdcard: Use registerfield CSR::CURRENT_STATE definition hw/sd/sdcard: Use HWBLOCK_SHIFT definition instead of magic values hw/sd/sdcard: Fix typo in SEND_OP_COND command name hw/sd/sdcard: Rewrite sd_cmd_ALL_SEND_CID using switch case (CMD2) hw/sd/sdcard: Correct code indentation hw/sd/sdcard: Avoid OOB in sd_read_byte() during unexpected CMD switch bswap: Add st24_be_p() to store 24 bits in big-endian order Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2024-06-24vfio/container: Move vfio_container_destroy() to an instance_finalize() handlerCédric Le Goater4-7/+3
vfio_container_destroy() clears the resources allocated VFIOContainerBase object. Now that VFIOContainerBase is a QOM object, add an instance_finalize() handler to do the cleanup. It will be called through object_unref(). Suggested-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Introduce vfio_iommu_legacy_instance_init()Cédric Le Goater1-1/+8
Just as we did for the VFIOContainerBase object, introduce an instance_init() handler for the legacy VFIOContainer object and do the specific initialization there. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Remove vfio_container_init()Cédric Le Goater4-11/+0
It's now empty. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Remove VFIOContainerBase::opsCédric Le Goater6-25/+38
Instead, use VFIO_IOMMU_GET_CLASS() to get the class pointer. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Introduce an instance_init() handlerCédric Le Goater1-6/+13
This allows us to move the initialization code from vfio_container_init(), which we will soon remove. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Switch to QOMCédric Le Goater2-5/+5
Instead of allocating the container struct, create a QOM object of the appropriate type. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Change VFIOContainerBase to use QOMCédric Le Goater6-10/+15
VFIOContainerBase was made a QOM interface because we believed that a QOM object would expose all the IOMMU backends to the QEMU machine and human interface. This only applies to user creatable devices or objects. Change the VFIOContainerBase nature from interface to object and make the necessary adjustments in the VFIO_IOMMU hierarchy. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Discover IOMMU type before creating the containerCédric Le Goater1-24/+23
Since the QEMU struct type representing the VFIO container is deduced from the IOMMU type exposed by the host, this type should be well defined *before* creating the container struct. This will be necessary to instantiate a QOM object of the correct type in future changes. Rework vfio_set_iommu() to extract the part doing the container initialization and move it under vfio_create_container(). Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Introduce vfio_create_container()Cédric Le Goater1-4/+15
This routine allocates the QEMU struct type representing the VFIO container. It is minimal currently and future changes will do more initialization. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Introduce vfio_get_iommu_class_name()Cédric Le Goater1-12/+6
Rework vfio_get_iommu_class() to return a literal class name instead of a class object. We will need this name to instantiate the object later on. Since the default case asserts, remove the error report as QEMU will simply abort before. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Modify vfio_get_iommu_type() to use a container fdCédric Le Goater1-3/+3
The 'container' pointer has no other use than its 'fd' attribute. Simplify the prototype to ease future changes. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Simplify vfio_container_init()Cédric Le Goater5-7/+6
Assign the base container VFIOAddressSpace 'space' pointer in vfio_address_space_insert(). The ultimate goal is to remove vfio_container_init() and instead rely on an .instance_init() handler to perfom the initialization of VFIOContainerBase. To be noted that vfio_connect_container() will assign the 'space' pointer later in the execution flow. This should not have any consequence. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/container: Introduce vfio_address_space_insert()Cédric Le Goater4-2/+10
It prepares ground for a future change initializing the 'space' pointer of VFIOContainerBase. The goal is to replace vfio_container_init() by an .instance_init() handler when VFIOContainerBase is QOMified. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/common: Extract vIOMMU code from vfio_sync_dirty_bitmap()Avihai Horon1-25/+38
Extract vIOMMU code from vfio_sync_dirty_bitmap() to a new function and restructure the code. This is done in preparation for optimizing vIOMMU device dirty page tracking. No functional changes intended. Signed-off-by: Avihai Horon <avihaih@nvidia.com> Signed-off-by: Joao Martins <joao.m.martins@oracle.com> [ clg: - Rebased on upstream - Fixed typo in commit log ] Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio/common: Move dirty tracking ranges update to helperJoao Martins1-16/+22
Separate the changes that update the ranges from the listener, to make it reusable in preparation to expand its use to vIOMMU support. Signed-off-by: Joao Martins <joao.m.martins@oracle.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> [ clg: - Rebased on upstream - Introduced vfio_dirty_tracking_update_range() - Fixed typ in commit log ] Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio: Remove unused declarations from vfio-common.hCédric Le Goater1-4/+0
These were forgotten in the recent cleanups. Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24vfio: Make vfio_devices_dma_logging_start() return boolCédric Le Goater1-7/+7
Since vfio_devices_dma_logging_start() takes an 'Error **' argument, best practices suggest to return a bool. See the api/error.h Rules section. It will simplify potential changes coming after. vfio_container_set_dirty_page_tracking() could be modified in the same way but the errno value can be saved in the migration stream when called from vfio_listener_log_global_stop(). Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Eric Auger <eric.auger@redhat.com> Tested-by: Eric Auger <eric.auger@redhat.com> Signed-off-by: Cédric Le Goater <clg@redhat.com>
2024-06-24memory: Remove IOMMU MR iommu_set_iova_range APIEric Auger2-45/+0
Since the host IOVA ranges are now passed through the PCIIOMMUOps set_host_resv_regions and we have removed the only implementation of iommu_set_iova_range() in the virtio-iommu and the only call site in vfio/common, let's retire the IOMMU MR API and its memory wrapper. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2024-06-24hw/vfio: Remove memory_region_iommu_set_iova_ranges() callEric Auger1-10/+0
As we have just removed the only implementation of iommu_set_iova_ranges IOMMU MR callback in the virtio-iommu, let's remove the call to the memory wrapper. Usable IOVA ranges are now conveyed through the PCIIOMMUOps in VFIO-PCI. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
2024-06-24virtio-iommu: Remove the implementation of iommu_set_iova_rangeEric Auger1-67/+0
Now that we use PCIIOMMUOps to convey information about usable IOVA ranges we do not to implement the iommu_set_iova_ranges IOMMU MR callback. Signed-off-by: Eric Auger <eric.auger@redhat.com> Reviewed-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
generated by cgit v1.1 at 2024-09-18 16:00:30 +0000