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2019-01-09spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.hGreg Kurz2-4/+4
PHB hotplug will bring more users for it. Let's define it along with the PHB defines from which it is derived for simplicity. While here fix a misleading comment about manual placement, which was abandoned with 30b3bc5aa9f4. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09pci: allow cleanup/unregistration of PCI root busesMichael Roth2-0/+36
This adds cleanup counterparts to pci_register_root_bus(), pci_root_bus_new(), and pci_bus_irqs(). These cleanup routines are needed in the case of hotpluggable PCIHostBridge implementations. Currently we can rely on the object_unparent()'ing of the PCIHostState recursively unparenting and cleaning up it's child buses, but we need explicit calls to also: 1) remove the PCIHostState from pci_host_bridges global list. otherwise, we risk accessing freed memory when we access the list later 2) clean up memory allocated in pci_bus_irqs() Both are handled outside the context of any particular bus or host bridge's init/realize functions, making it difficult to avoid the need for explicit cleanup functions without remodeling how PCIHostBridges are created. So keep it simple and just add them for now. Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09spapr: move spapr_create_phb() to core machine codeGreg Kurz3-14/+12
This function is only used when creating the default PHB. Let's rename it and move it to the core machine code for clarity. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09MAINTAINERS: add qemu_vga.ndrv file entry for Mac machinesMark Cave-Ayland1-0/+2
The VGA driver built from Ben's QemuMacDrivers repository is used exclusively by the Mac machines. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09MAINTAINERS: Add some missing ppc-related filesThomas Huth1-2/+7
hw/gpio/mpc8xxx.c is only used by the e500 machine, so add it there. And the hw/input/adb* files are specific to the Mac machines, so they should be assigned to these categories. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: replace AVR* macros with Vsr* macrosMark Cave-Ayland1-17/+13
Now that the VMX and VSR register sets have been combined, the same macros can be used to access both AVR and VSR field members. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: move FP and VMX registers into aligned vsr register arrayMark Cave-Ayland13-82/+165
The VSX register array is a block of 64 128-bit registers where the first 32 registers consist of the existing 64-bit FP registers extended to 128-bit using new VSR registers, and the last 32 registers are the VMX 128-bit registers as show below: 64-bit 64-bit +--------------------+--------------------+ | FP0 | | VSR0 +--------------------+--------------------+ | FP1 | | VSR1 +--------------------+--------------------+ | ... | ... | ... +--------------------+--------------------+ | FP30 | | VSR30 +--------------------+--------------------+ | FP31 | | VSR31 +--------------------+--------------------+ | VMX0 | VSR32 +-----------------------------------------+ | VMX1 | VSR33 +-----------------------------------------+ | ... | ... +-----------------------------------------+ | VMX30 | VSR62 +-----------------------------------------+ | VMX31 | VSR63 +-----------------------------------------+ In order to allow for future conversion of VSX instructions to use TCG vector operations, recreate the same layout using an aligned version of the existing vsr register array. Since the old fpr and avr register arrays are removed, the existing callers must also be updated to use the correct offset in the vsr register array. This also includes switching the relevant VMState fields over to using subarrays to make sure that migration is preserved. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: merge ppc_vsr_t and ppc_avr_t union typesMark Cave-Ayland3-45/+39
Since the VSX registers are actually a superset of the VMX registers then they can be represented by the same type. Merge ppc_avr_t into ppc_vsr_t and change ppc_avr_t to be a simple typedef alias. Note that due to a difference in the naming of the float32 member between ppc_avr_t and ppc_vsr_t, references to the ppc_avr_t f member must be replaced with f32 instead. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_envMark Cave-Ayland2-45/+18
Instead of accessing the FPR, VMX and VSX registers through static arrays of TCGv_i64 globals, remove them and change the helpers to load/store data directly within cpu_env. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for ↵Mark Cave-Ayland1-224/+638
VSR register access These helpers allow us to move VSR register values to/from the specified TCGv_i64 argument. To prevent VSX helpers accessing the cpu_vsr array directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: introduce get_avr64() and set_avr64() helpers for VMX register ↵Mark Cave-Ayland2-33/+124
access These helpers allow us to move AVR register values to/from the specified TCGv_i64 argument. To prevent VMX helpers accessing the cpu_avr{l,h} arrays directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: introduce get_fpr() and set_fpr() helpers for FP register accessMark Cave-Ayland2-110/+386
These helpers allow us to move FP register values to/from the specified TCGv_i64 argument in the VSR helpers to be introduced shortly. To prevent FP helpers accessing the cpu_fpr array directly, add extra TCG temporaries as required. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: switch EXTRACT_HELPER macros over to use sextract32/extract32Mark Cave-Ayland1-4/+4
These ensure that we consistently handle signed and unsigned extensions correctly when decoding immediates from instruction opcodes. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09target/ppc: fix typo in SIMM5 extraction helperMark Cave-Ayland1-1/+1
As the macro name suggests, the argument should be signed and not unsigned. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09MAINTAINERS: Add more files to sam460exBALATON Zoltan1-0/+6
The sm501 model belonged to SH before but that seems to be inactive now and latest changes were for sam460ex which is the more active user of this device at the moment so let's adopt sm501 for sam460ex. Also add device tree and firmware sources and binaries. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09ppc4xx: Disable debug logging by defaultBALATON Zoltan1-2/+1
Debug logs were left enabled in ppc4xx_devs.c whereas in other files these are normally not enabled. Disable it here as well. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09ppc/spapr: Receive and store device tree blob from SLOFAlexey Kardashevskiy5-3/+94
SLOF receives a device tree and updates it with various properties before switching to the guest kernel and QEMU is not aware of any changes made by SLOF. Since there is no real RTAS (QEMU implements it), it makes sense to pass the SLOF final device tree to QEMU to let it implement RTAS related tasks better, such as PCI host bus adapter hotplug. Specifially, now QEMU can find out the actual XICS phandle (for PHB hotplug) and the RTAS linux,rtas-entry/base properties (for firmware assisted NMI - FWNMI). This stores the initial DT blob in the sPAPR machine and replaces it in the KVMPPC_H_UPDATE_DT (new private hypercall) handler. This adds an @update_dt_enabled machine property to allow backward migration. SLOF already has a hypercall since https://github.com/aik/SLOF/commit/e6fc84652c9c0073f9183 This makes use of the new fdt_check_full() helper. In order to allow the configure script to pick the correct DTC version, this adjusts the DTC presense test. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-09spapr: Add H-Call H_HOME_NODE_ASSOCIATIVITYLaurent Vivier3-0/+42
H_HOME_NODE_ASSOCIATIVITY H-Call returns the associativity domain designation associated with the identifier input parameter This fixes a crash when we try to hotplug a CPU in memory-less and CPU-less numa node. In this case, the kernel tries to online the node, but without the information provided by this h-call, the node id, it cannot and the CPU is started while the node is not onlined. It also removes the warning message from the kernel: VPHN is not supported. Disabling polling.. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-01-08Merge remote-tracking branch 'remotes/kraxel/tags/usb-20190108-pull-request' ↵Peter Maydell8-61/+74
into staging usb: generic sysbus ehci, bugfixes. # gpg: Signature made Tue 08 Jan 2019 15:53:37 GMT # gpg: using RSA key 4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20190108-pull-request: usb: move ehci_create_ich9_with_companions to hw/i386 hw/usb: Add generic sys-bus EHCI controller usb: dev-mtp: fix memory leak in error path usb: drop unnecessary usb_device_post_load checks hw/usb: fix mistaken de-initialization of CCID state Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-08qemu-thread: Don't block SEGV, ILL and FPERoman Bolshakov1-0/+5
If any of these signals happen on macOS, they are not delivered to other threads and signalfd_compat receives nothing. Indeed, POSIX reference and sigprocmask(2) note that an attempt to block the signals results in undefined behaviour. SEGV and FPE can't also be received by signalfd(2) on Linux. An ability to retrieve SIGBUS via signalfd(2) is used by QEMU for memory preallocation therefore we can't unblock it without consequences. But it's important to leave a remark that the signal is lost on macOS. Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-08util: Implement debug-threads for macOSRoman Bolshakov3-9/+33
macOS provides pthread_setname_np that doesn't have thread id argument. Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-08ui/cocoa: Include less of the generated modular QAPI headersMarkus Armbruster1-1/+2
Avoids pointless recompilation. Missed in commit 112ed241f5d. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Roman Bolshakov <r.bolshakov@yadro.com> Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> Tested-by: Roman Bolshakov <r.bolshakov@yadro.com> Message-id: 20181220084559.13880-1-armbru@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-08usb: move ehci_create_ich9_with_companions to hw/i386Paolo Bonzini3-55/+53
This function is only needed when Q35 is in use. Moving it to the same file that uses it lets you disable the entire USB subsystem in x86_64-softmmu.mak; of course doing that will cause -usb to break horribly, but one thing at a time. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-id: 1545064358-4601-1-git-send-email-pbonzini@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-08hw/usb: Add generic sys-bus EHCI controllerHongbo Zhang2-0/+18
This patch introduces a new system bus generic EHCI controller. For the system bus EHCI controller, we've already had "xlnx", "exynos4210", "tegra2", "ppc4xx" and "fusbh200", they are specific and only suitable for their own platforms, platforms such as an Arm server, may need a generic system bus EHCI controller, this patch creates it, and the kernel driver ehci_platform.c works well on it. Signed-off-by: Hongbo Zhang <hongbo.zhang@linaro.org> Message-id: 1546077657-22637-1-git-send-email-hongbo.zhang@linaro.org Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-08usb: dev-mtp: fix memory leak in error pathLi Qiang1-0/+1
Spotted by Coverity: CID 1397074 Fixes: c52d46e041b Signed-off-by: Li Qiang <liq3ea@163.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190103132605.49476-1-liq3ea@163.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-08usb: drop unnecessary usb_device_post_load checksJonathan Davies1-6/+0
In usb_device_post_load, certain values of dev->setup_len or dev->setup_index can cause -EINVAL to be returned. One example is when setup_len exceeds 4096, the hard-coded value of sizeof(dev->data_buf). This can happen through legitimate guest activity and will cause all subsequent attempts to migrate the guest to fail in vmstate_load_state. The values of these variables can be set by USB packets originating in the guest. There are two ways in which they can be set: in do_token_setup and in do_parameter in hw/usb/core.c. It is easy to craft a USB packet in a guest that causes do_token_setup to set setup_len to a value larger than 4096. When this has been done once, all subsequent attempts to migrate the VM will fail in usb_device_post_load until the VM is next power-cycled or a smaller-sized USB packet is sent to the device. Sample code for achieving this in a VM started with "-device usb-tablet" running Linux with CONFIG_HIDRAW=y and HID_MAX_BUFFER_SIZE > 4096: #include <sys/types.h> #include <sys/stat.h> #include <fcntl.h> #include <unistd.h> int main() { char buf[4097]; int fd = open("/dev/hidraw0", O_RDWR|O_NONBLOCK); buf[0] = 0x1; write(fd, buf, 4097); return 0; } When this code is run in the VM, qemu will output: usb_generic_handle_packet: ctrl buffer too small (4097 > 4096) A subsequent attempt to migrate the VM will fail and output the following on the destination host: qemu-kvm: error while loading state for instance 0x0 of device '0000:00:06.7/1/usb-ptr' qemu-kvm: load of migration failed: Invalid argument The idea behind checking the values of setup_len and setup_index before they are used is correct, but doing it in usb_device_post_load feels arbitrary, and will cause unnecessary migration failures. Indeed, none of the commit messages for c60174e8, 9f8e9895 and 719ffe1f justify why post_load is the right place to do these checks. They correctly point out that the important thing to protect is the usb_packet_copy. Instead, the right place to do the checks is in do_token_setup and do_parameter. Indeed, there are already some checks here. We can examine each of the disjuncts currently tested in usb_device_post_load to see whether any need adding to do_token_setup or do_parameter to improve safety there: * dev->setup_index < 0 - This test is not needed because setup_index is explicitly set to 0 in do_token_setup and do_parameter. * dev->setup_len < 0 - In both do_token_setup and do_parameter, the value of setup_len is computed by (s->setup_buf[7] << 8) | s->setup_buf[6]. Since s->setup_buf is a byte array and setup_len is an int32_t, it's impossible for this arithmetic to set setup_len's top bit, so it can never be negative. * dev->setup_index > dev->setup_len - Since setup_index is 0, this is equivalent to the previous test, so is redundant. * dev->setup_len > sizeof(dev->data_buf) - This condition is already explicitly checked in both do_token_setup and do_parameter. Hence there is no need to bolster the existing checks in do_token_setup or do_parameter, and we can safely remove these checks from usb_device_post_load without reducing safety but allowing migrations to proceed regardless of what USB packets have been generated by the guest. Signed-off-by: Jonathan Davies <jonathan.davies@nutanix.com> Message-Id: <20190107175117.23769-1-jonathan.davies@nutanix.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2019-01-08Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20190108' into stagingPeter Maydell4-23/+30
Queued target/alpha patches # gpg: Signature made Tue 08 Jan 2019 02:14:18 GMT # gpg: using RSA key 64DF38E8AF7E215F # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth/tags/pull-axp-20190108: pc-bios: Update palcode-clipper target/alpha: Fix user-only initialization of fpcr hw/alpha/typhoon: Stop calling cpu_unassigned_access() Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-08pc-bios: Update palcode-clipperRichard Henderson2-0/+0
Do not double-update the PC after OPCDEC. Fixes: https://bugs.launchpad.net/bugs/1810545 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-08target/alpha: Fix user-only initialization of fpcrRichard Henderson1-3/+3
When the representation of fpcr was changed, the user-only initialization was not updated to match. Oops. Fixes: f3d3aad4a92 Fixes: https://bugs.launchpad.net/bugs/1701835 Reported-by: Bruno Haible <bruno@clisp.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-08hw/alpha/typhoon: Stop calling cpu_unassigned_access()Peter Maydell1-20/+27
The typhoon MemoryRegionOps callbacks directly call cpu_unassigned_access(), presumably as the old-fashioned way to provoke a CPU exception. This won't work since commit 6ad4d7eed05a1e235 when we switched Alpha over to the transaction_failed hook API, because now cpu_unassigned_access() is a no-op for Alpha. Make the MemoryRegionOps callbacks use the read_with_attrs and write_with_attrs hooks, so they can signal a failure that should cause a CPU exception by returning MEMTX_ERROR. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20181210173350.13073-1-peter.maydell@linaro.org> Tested-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2019-01-07Merge remote-tracking branch ↵Peter Maydell48-267/+2563
'remotes/pmaydell/tags/pull-target-arm-20190107' into staging target-arm queue: * Support u-boot 'noload' images for Arm (as used by NetBSD/evbarm GENERIC kernel) * hw/misc/tz-mpc: Fix value of BLK_MAX register * target/arm: Emit barriers for A32/T32 load-acquire/store-release insns * nRF51 SoC: add timer, GPIO, RNG peripherals * hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller * cpus.c: Fix race condition in cpu_stop_current() * hw/arm: versal: Plug memory leaks * Allow M profile boards to run even if -kernel not specified * gdbstub: Add multiprocess extension support for use when the board has multiple CPUs of different types (like the Xilinx Zynq boards) * target/arm: Don't decode S bit in SVE brk[ab] merging insns * target/arm: Convert ARM_TBFLAG_* to FIELDs # gpg: Signature made Mon 07 Jan 2019 16:29:52 GMT # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20190107: (37 commits) Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel. hw/misc/tz-mpc: Fix value of BLK_MAX register target/arm: Emit barriers for A32/T32 load-acquire/store-release insns arm: Add Clock peripheral stub to NRF51 SOC tests/microbit-test: Add Tests for nRF51 Timer arm: Instantiate NRF51 Timers hw/timer/nrf51_timer: Add nRF51 Timer peripheral tests/microbit-test: Add Tests for nRF51 GPIO arm: Instantiate NRF51 general purpose I/O hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheral arm: Instantiate NRF51 random number generator hw/misc/nrf51_rng: Add NRF51 random number generator peripheral arm: Add header to host common definition for nRF51 SOC peripherals qtest: Add set_irq_in command to set IRQ/GPIO level hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controller cpus.c: Fix race condition in cpu_stop_current() MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/ hw/arm: versal: Plug memory leaks Revert "armv7m: Guard against no -kernel argument" arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07Support u-boot noload images for arm as used by, NetBSD/evbarm GENERIC kernel.Nick Hudson9-11/+33
noload kernels are loaded with the u-boot image header and as a result the header size needs adding to the entry point. Fake up a hdr so the kernel image is loaded at the right address and the entry point is adjusted appropriately. The default location for the uboot file is 32MiB above bottom of DRAM. This matches the recommendation in Documentation/arm/Booting. Clarify the load_uimage API to state the passing of a load address when an image doesn't specify one, or when loading a ramdisk is expected. Adjust callers of load_uimage, etc. Signed-off-by: Nick Hudson <skrll@netbsd.org> Message-id: 11488a08-1fe0-a278-2210-deb64731107f@gmx.co.uk Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07Merge remote-tracking branch ↵Peter Maydell32-1638/+1786
'remotes/elmarco/tags/machine-props-pull-request' into staging Generalize machine compatibility properties During "[PATCH v2 05/10] qom/globals: generalize object_property_set_globals()" review, Eduardo suggested to rework the GlobalProperty handling, so that -global is limited to QDev only and we avoid mixing the machine compats and the user-provided -global properties (instead of generalizing -global to various object kinds, like I proposed in v2). "qdev: do not mix compat props with global props" patch decouples a bit user-provided -global from machine compat properties. This allows to get rid of "user_provided" and "errp" fields in following patches. A new compat property "x-use-canonical-path-for-ramblock-id" is added to hostmem for legacy canonical path names, set to true for -file and -memfd with qemu < 4.0. (this series was initially titled "[PATCH v2 00/10] hostmem: use object "id" for memory region name with >= 3.1", but its focus is more in refactoring the global and compatilibity properties handling now) # gpg: Signature made Mon 07 Jan 2019 12:22:43 GMT # gpg: using RSA key DAE8E10975969CE5 # gpg: Good signature from "Marc-André Lureau <marcandre.lureau@redhat.com>" # gpg: aka "Marc-André Lureau <marcandre.lureau@gmail.com>" # Primary key fingerprint: 87A9 BD93 3F87 C606 D276 F62D DAE8 E109 7596 9CE5 * remotes/elmarco/tags/machine-props-pull-request: (28 commits) hostmem: use object id for memory region name with >= 4.0 arm: replace instance_post_init() qdev-props: call object_apply_global_props() qdev-props: remove errp from GlobalProperty qdev-props: convert global_props to GPtrArray qdev: all globals are now user-provided qdev: make a separate helper function to apply compat properties compat: remove remaining PC_COMPAT macros include: remove compat.h compat: replace PC_COMPAT_2_1 & HW_COMPAT_2_1 macros compat: replace PC_COMPAT_2_2 & HW_COMPAT_2_2 macros compat: replace PC_COMPAT_2_3 & HW_COMPAT_2_3 macros compat: replace PC_COMPAT_2_4 & HW_COMPAT_2_4 macros compat: replace PC_COMPAT_2_5 & HW_COMPAT_2_5 macros compat: replace PC_COMPAT_2_6 & HW_COMPAT_2_6 macros compat: replace PC_COMPAT_2_7 & HW_COMPAT_2_7 macros compat: replace PC_COMPAT_2_8 & HW_COMPAT_2_8 macros compat: replace PC_COMPAT_2_9 & HW_COMPAT_2_9 macros compat: replace PC_COMPAT_2_10 & HW_COMPAT_2_10 macros compat: replace PC_COMPAT_2_11 & HW_COMPAT_2_11 macros ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/misc/tz-mpc: Fix value of BLK_MAX registerPeter Maydell1-1/+1
In the TZ Memory Protection Controller, the BLK_MAX register is supposed to return the maximum permitted value of the BLK_IDX register. Our implementation incorrectly returned max+1 (ie the total number of valid index values, since BLK_IDX is zero-based). Correct this off-by-one error. Since we consistently initialize and use s->blk_max throughout the implementation as the 'size' of the LUT, just adjust the value we return when the guest reads the BLK_MAX register, rather than trying to change the semantics of the s->blk_max internal struct field. Fixes: https://bugs.launchpad.net/qemu/+bug/1806824 Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181213183249.3468-1-peter.maydell@linaro.org
2019-01-07target/arm: Emit barriers for A32/T32 load-acquire/store-release insnsPeter Maydell1-7/+26
Now that MTTCG is here, the comment in the 32-bit Arm decoder that "Since the emulation does not have barriers, the acquire/release semantics need no special handling" is no longer true. Emit the correct barriers for the load-acquire/store-release insns, as we already do in the A64 decoder. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
2019-01-07arm: Add Clock peripheral stub to NRF51 SOCSteffen Görtz2-0/+27
This stubs enables the microbit-micropython firmware to run on the microbit machine. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-12-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07tests/microbit-test: Add Tests for nRF51 TimerSteffen Görtz1-0/+95
Basic tests for nRF51 Timer Peripheral. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-11-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Instantiate NRF51 TimersSteffen Görtz2-0/+30
Instantiates TIMER0 - TIMER2 Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-10-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/timer/nrf51_timer: Add nRF51 Timer peripheralSteffen Görtz4-0/+479
This patch adds the model for the nRF51 timer peripheral. Currently, only the TIMER mode is implemented. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-9-stefanha@redhat.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07tests/microbit-test: Add Tests for nRF51 GPIOSteffen Görtz2-0/+162
The test suite for the nRF51 GPIO peripheral for now only tests initial state. Additionally a set of tests testing an implementation detail of the model are included. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-8-stefanha@redhat.com [PMM: fixed stray space at start of file] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Instantiate NRF51 general purpose I/OSteffen Görtz2-0/+18
Instantiates GPIO peripheral model Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-7-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/gpio/nrf51_gpio: Add nRF51 GPIO peripheralSteffen Görtz5-0/+378
This adds a model of the nRF51 GPIO peripheral. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf The nRF51 series microcontrollers support up to 32 GPIO pins in various configurations. The pins can be used as input pins with pull-ups or pull-down. Furthermore, three different output driver modes per level are available (disconnected, standard, high-current). The GPIO-Peripheral has a mechanism for detecting level changes which is not featured in this model. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-6-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Instantiate NRF51 random number generatorSteffen Görtz2-0/+18
Use RNG in SOC. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-5-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/misc/nrf51_rng: Add NRF51 random number generator peripheralSteffen Görtz3-0/+346
Add a model of the NRF51 random number generator peripheral. This is a simple random generator that continuously generates new random values after startup. Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-4-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07arm: Add header to host common definition for nRF51 SOC peripheralsSteffen Görtz3-22/+57
Adds a header that provides definitions that are used across nRF51 peripherals Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-3-stefanha@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07qtest: Add set_irq_in command to set IRQ/GPIO levelSteffen Görtz3-0/+66
Adds a new qtest command "set_irq_in" which allows to set qemu gpio lines to a given level. Based on https://lists.gnu.org/archive/html/qemu-devel/2012-12/msg02363.html which never got merged. Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 20190103091119.9367-2-stefanha@redhat.com Originally-by: Matthew Ogilvie <mmogilvi_qemu@miniinfo.net> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/arm/allwinner-a10: Add the 'A' SRAM and the SRAM controllerPhilippe Mathieu-Daudé2-0/+7
From the "A10 User Manual V1.20" p.29: "3.2. Memory Mapping" and: 7. System Control 7.1. Overview A10 embeds a high-speed SRAM which has been split into five segments. See detailed memory mapping in following table: Area Address Size (Bytes) A1 0x00000000-0x00003FFF 16K A2 0x00004000-0x00007FFF 16K A3 0x00008000-0x0000B3FF 13K A4 0x0000B400-0x0000BFFF 3K Since for emulation purpose we don't need the segmentations, we simply define the 'A' area as a single 48KB SRAM. We don't implement the following others areas: - 'B': 'Secure RAM' (64K), - 'C': Debug/ISP SRAM - 'D': USB SRAM (qemu) info mtree address-space: memory 0000000000000000-ffffffffffffffff (prio 0, i/o): system 0000000000000000-000000000000bfff (prio 0, ram): sram A 0000000001c00000-0000000001c00fff (prio -1000, i/o): a10-sram-ctrl 0000000001c0b000-0000000001c0bfff (prio 0, i/o): aw_emac 0000000001c18000-0000000001c18fff (prio 0, i/o): ahci 0000000001c18080-0000000001c180ff (prio 0, i/o): allwinner-ahci 0000000001c20400-0000000001c207ff (prio 0, i/o): allwinner-a10-pic 0000000001c20c00-0000000001c20fff (prio 0, i/o): allwinner-A10-timer 0000000001c28000-0000000001c2801f (prio 0, i/o): serial 0000000040000000-0000000047ffffff (prio 0, ram): cubieboard.ram Reported-by: Charlie Smurthwaite <charlie@atech.media> Tested-by: Charlie Smurthwaite <charlie@atech.media> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20190104142921.878-1-f4bug@amsat.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07cpus.c: Fix race condition in cpu_stop_current()Peter Maydell1-1/+2
We use cpu_stop_current() to ensure the current CPU has stopped from places like qemu_system_reset_request(). Unfortunately its current implementation has a race. It calls qemu_cpu_stop(), which sets cpu->stopped to true even though the CPU hasn't actually stopped yet. The main thread will look at the flags set by qemu_system_reset_request() and call pause_all_vcpus(). pause_all_vcpus() waits for every cpu to have cpu->stopped true, so it can continue (and we will start the system reset operation) before the vcpu thread has got back to its top level loop. Instead, just set cpu->stop and call cpu_exit(). This will cause the vcpu to exit back to the top level loop, and there (as part of the wait_io_event code) it will call qemu_cpu_stop(). This fixes bugs where the reset request appeared to be ignored or the CPU misbehaved because the reset operation started to change vcpu state while the vcpu thread was still using it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Tested-by: Jaap Crezee <jaap@jcz.nl> Message-id: 20181207155911.12710-1-peter.maydell@linaro.org
2019-01-07MAINTAINERS: Add ARM-related files for hw/[misc|input|timer]/Thomas Huth1-2/+14
Some of the files in hw/input/, hw/misc/ and hw/timer/ are only used by one of the ARM machines, so we can assign these files to the corresponding boards. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 1546433583-18397-1-git-send-email-thuth@redhat.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07hw/arm: versal: Plug memory leaksEdgar E. Iglesias1-0/+2
Plug a couple of "board creation time" memory leaks. Fixes: 6f16da53ffe4567 ("hw/arm: versal: Add a virtual Xilinx Versal board") Reported-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190104104749.5314-2-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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