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2011-09-10Gdbstub: Fix back-trace on SPARC32Fabien Chouteau3-3/+104
Gdb expects all registers windows to be flushed in ram, which is not the case in Qemu. Therefore the back-trace generation doesn't work. This patch adds a function to handle reads (and only read) in stack frames as if windows were flushed. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add regression testsuiteMax Filippov28-0/+3087
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10MAINTAINERS: add xtensa maintainerMax Filippov1-0/+13
Add myself as target-xtensa and DC232B maintainer. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add dc232b core and boardMax Filippov4-0/+546
This is Diamond 232L Standard Core Rev.B (LE). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement boolean optionMax Filippov2-24/+86
See ISA, 4.3.9 Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement memory protection optionsMax Filippov5-13/+782
- TLB opcode group; - region protection option (ISA, 4.6.3); - region translation option (ISA, 4.6.4); - MMU option (ISA, 4.6.5). Cache control attribute bits are not used by this implementation. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add gdb supportMax Filippov4-0/+496
Specific xtensa processor overlay for GDB contains register map in the gdb/xtensa-config.c. This description is used by the GDB to e.g. parse 'g' response packets and it may be reused in the qemu's gdbstub (only XTREG definitions for non-pseudoregisters are needed). Currently mainline GDB does not support operations with privileged SRs (see http://sourceware.org/ml/gdb/2011-07/msg00075.html). This support may be enabled, see NUM_CORE_REGS comment in the gdbstub.c Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement relocatable vectorsMax Filippov3-2/+19
See ISA, 4.4.3 for details. Vector addresses recorded in core configuration are absolute values that correspond to default VECBASE value. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement CPENABLE and PRID SRsMax Filippov3-0/+10
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement accurate window checkMax Filippov1-0/+110
See ISA, 4.7.1.3 for details. Window check is inserted before commands that push "used register watermark" beyond its current level. Used register watermark is reset on instructions that change WINDOW_BASE/WINDOW_START SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement interrupt optionMax Filippov6-12/+431
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt option) and 4.4.8 (timer interrupt option) for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement SIMCALLMax Filippov5-3/+236
Tensilica iss provides support for applications running in freestanding environment through SIMCALL command. It is used by Tensilica libc to access argc/argv, for file I/O, etc. Note that simcalls that accept buffer addresses expect virtual addresses. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement unaligned exception optionMax Filippov3-4/+73
See ISA, 4.4.4 for details. Correct (aligned as per ISA) address for unaligned access is generated in case this option is not enabled. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement extended L32RMax Filippov3-4/+40
See ISA, 4.3.3 for details. TB flag XTENSA_TBFLAG_LITBASE is used to track enable bit of LITBASE SR. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement loop optionMax Filippov4-9/+93
See ISA, 4.3.2 for details. Operations that change LEND SR value invalidate TBs at the old and at the new LEND. LEND value at TB compilation time is considered constant and loop instruction is generated based on this value. Invalidation may be avoided for the TB at the old LEND address, since looping code verifies actual LEND value. Invalidation may be avoided for the TB at the new LEND address if there's a way to associate LEND address with TB at compilation time and later verify that it doesn't change. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement windowed registersMax Filippov5-9/+345
See ISA, 4.7.1 for details. Physical registers and currently visible window are separate fields in CPUEnv. Only current window is accessible to TCG. On operations that change window base helpers copy current window to and from physical registers. Window overflow check described in 4.7.1.3 is in separate patch. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement RST2 group (32 bit mul/div/rem)Max Filippov1-1/+76
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement exceptionsMax Filippov6-6/+242
- mark privileged opcodes with ring check; - make debug exception on exception handler entry. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add PS register and access controlMax Filippov3-6/+77
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement CACHE groupMax Filippov1-1/+94
All operations in this group are no-ops, because cache ought to be transparent to applications. However cache may be abused, then we'll need to actually implement these opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement SYNC groupMax Filippov1-1/+30
All operations in this group are no-ops, because there are no delayed side effects. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: mark reserved and TBD opcodesMax Filippov1-1/+109
Reserved opcodes must generate illegal instruction exception. Usually they signal emulation quality problems. Not implemented opcodes are good to see. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement LSAI groupMax Filippov2-0/+90
- base + offset load/store operations for 1/2/4 byte values; - cache operations (not implemented); - multiprocessor synchronization operations. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement shifts (ST1 and RST1 groups)Max Filippov4-0/+262
- ST1: SAR (shift amount special register) manipulation, NSA(U); - RST1: shifts, 16-bit multiplication. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement RST3 groupMax Filippov1-0/+161
- access to Special Registers (wsr, rsr); - access to User Registers (wur, rur); - misc. operations option (value clamp, sign extension, min, max); - conditional moves. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add special and user registersMax Filippov2-2/+54
Special Registers hold the majority of the state added to the processor by the options. See ISA, 5.3 for details. User Registers hold state added in support of designer's TIE and in some cases of options that Tensilica provides. See ISA, 5.4 for details. Only registers mapped in sregnames or uregnames are considered valid. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement JX/RET0/CALLXMax Filippov1-0/+43
Group SNM0 (indirect jumps and calls). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement conditional jumpsMax Filippov1-0/+164
- BZ (comparison to zero); - BI0 (comparison to signed immediate); - BI1 (comparison to unsigned immediate); - B (two registers comparison, bit sets comparison); - BEQZ.N/BNEZ.N (narrow comparison to zero). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add sample boardMax Filippov2-0/+107
Sample board and sample CPU core are used for debug and may be used for development of custom SoC emulators. This board has two fixed size memory regions for DTCM and ITCM and variable length SRAM region. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement RT0 groupMax Filippov1-0/+19
NEG and ABS are the only members of RT0 group. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement narrow instructionsMax Filippov1-0/+54
Instructions with op0 >= 8 are 2 bytes long, others are 3 bytes long. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: implement disas_xtensa_insnMax Filippov5-2/+556
Set up disas_xtensa_insn switch structure, mark required options on high level groups. Implement arithmetic/bit logic/jump/call0. Implement code generation loop with single step/breakpoint checking. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add target to the configure scriptMax Filippov3-1/+13
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10target-xtensa: add target stubsMax Filippov11-0/+373
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10mipsnet: use trace frameworkHervé Poussineau2-20/+13
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10mipsnet: convert to qdevHervé Poussineau3-36/+65
Move mipsnet_init() function to mipssim machine Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10PCI: delete unused mem_base and pci_to_cpu_addrBlue Swirl2-15/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10Sparc64: remove useless variableBlue Swirl1-4/+2
Remove a useless variable, spotted by clang analyzer: /src/qemu/target-sparc/op_helper.c:3904:18: warning: unused variable 'tmp' [-Wunused-variable] target_ulong tmp = val; The error message is actually incorrect since the variable is used. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10lsi53c895a: avoid a warning from clang analyzerBlue Swirl1-4/+1
Avoid this warning from clang analyzer by deleting the variable: /src/qemu/hw/lsi53c895a.c:895:5: warning: Value stored to 'id' is never read id = (current_tag >> 8) & 0xf; Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10cpu-exec: remove unnecessary assignmentBlue Swirl1-2/+3
Avoid this warning from clang analyzer: /src/qemu/cpu-exec.c:97:5: warning: Value stored to 'phys_page2' is never read phys_page2 = -1; Adjust the scope of the variable while at it. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10kvm: remove unnecessary assignmentsBlue Swirl1-1/+1
Avoid these warnings from clang analyzer: /src/qemu/target-i386/kvm.c:772:5: warning: Value stored to 'cwd' is never read cwd = swd = twd = 0; /src/qemu/target-i386/kvm.c:772:11: warning: Although the value stored to 'swd' is used in the enclosing expression, the value is never actually read from 'swd' cwd = swd = twd = 0; Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10hid: fix misassignmentBlue Swirl1-1/+1
The code does not have any effect as is, fix it. Spotted by clang analyzer: /src/qemu/hw/hid.c:99:13: warning: Value stored to 'x1' is never read x1 = 1; Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10scsi-bus: remove duplicate table entriesBlue Swirl1-3/+1
Remove duplicate entries from SCSI command table, spotted by clang analyzer: /src/qemu/hw/scsi-bus.c:979:40: warning: initializer overrides prior initialization of this subobject [ ERASE_16 ] = "ERASE_16", /src/qemu/hw/scsi-bus.c:978:40: note: previous initialization is here [ WRITE_SAME_16 ] = "WRITE_SAME_16", /src/qemu/hw/scsi-bus.c:984:40: warning: initializer overrides prior initialization of this subobject [ MAINTENANCE_IN ] = "MAINTENANCE_IN", /src/qemu/hw/scsi-bus.c:917:40: note: previous initialization is here [ MAINTENANCE_IN ] = "MAINTENANCE_IN", /src/qemu/hw/scsi-bus.c:985:40: warning: initializer overrides prior initialization of this subobject [ MAINTENANCE_OUT ] = "MAINTENANCE_OUT", /src/qemu/hw/scsi-bus.c:918:40: note: previous initialization is here [ MAINTENANCE_OUT ] = "MAINTENANCE_OUT", Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10qemu-io: remove unnecessary assignmentBlue Swirl1-1/+0
Remove an unnecessary assignment, spotted by clang analyzer: /src/qemu/qemu-io.c:995:9: warning: Value stored to 'offset' is never read offset += reqs[i].qiov->size; Acked-by: Kevin Wolf <kwolf@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10win32: improve version.o dependencyBlue Swirl1-1/+1
Actually, version.rc doesn't need config-host.mak but config-host.h, fix it. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-10g364fb: compile in hwlibBlue Swirl7-8/+15
Compile g364fb in hwlib. Two compilations less for the full build. Acked-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2011-09-09Merge remote-tracking branch 'sstabellini/xen-next' into stagingAnthony Liguori8-26/+85
2011-09-09Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori11-17/+15
2011-09-09build: fix missing trace dep on GENERATED_HEADERSMichael Roth1-0/+2
fc764105 added an include for qemu-common.h to trace/control.h, which made all users of this header file dependent on GENERATED_HEADERS. Since it's used by pretty much all the trace backends now, make trace-obj-y dependent on GENERATED_HEADERS. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com> Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2011-09-09vns/tls: don't use depricated gnutls functionsGerd Hoffmann1-19/+49
Avoid using deprecated gnutls functions with recent gnutls versions. Fixes build failure on Fedora 16. Keep the old way for compatibility with old installations such as RHEL-5 (gnutls 1.4.x). Based on a patch from Raghavendra D Prabhu <raghu.prabhu13@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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