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2009-10-24escc: add chipset docsBlue Swirl1-0/+4
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-24escc: convert to VMState, vmsd and resetBlue Swirl1-62/+38
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-24sparc32: add chipset docs for eccmemctlBlue Swirl1-0/+4
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-24sparc32: convert slavio_misc to reset + vmsdBlue Swirl1-6/+6
Also remove unused include directive. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-24sparc32: convert eccmemctl to reset + vmsdBlue Swirl1-6/+6
Also remove unused include directive. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-24sparc64: remove unused variablesBlue Swirl1-3/+0
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-23target-arm: optimize thumb 32-bit multiplyJuha.Riihimaki@nokia.com1-17/+1
Current implementation of thumb mul instruction is implemented as a 32x32->64 multiply which then uses only 32 least significant bits of the result. Replace that with a simple 32x32->32 multiply. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: cleanup internal resource leaksJuha Riihimäki1-27/+89
Revised patch for getting rid of tcg temporary variable leaks in target-arm/translate.c. This version also includes the leak patch for gen_set_cpsr macro, now converted as a static inline function, which I sent earlier as a separate patch on top of this patch. Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-i386: implement lzcnt emulationAndre Przywara3-14/+38
lzcnt is a AMD Phenom/Barcelona added instruction returning the number of leading zero bits in a word. As this is similar to the "bsr" instruction, reuse the existing code. There need to be some more changes, though, as lzcnt always returns a valid value (in opposite to bsr, which has a special case when the operand is 0). lzcnt is guarded by the ABM CPUID bit (Fn8000_0001:ECX_5). Signed-off-by: Andre Przywara <andre.przywara@amd.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-ppc: move often used CPU fields at the top of the structureAurelien Jarno1-4/+4
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-23target-arm: fix sdiv helperAurelien Jarno1-0/+2
(INT32_MIN / -1) triggers an overflow, and the result depends on the host architecture (INT32_MIN on arm, -1 on ppc, SIGFPE on x86). Use a test to output the correct value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-23target-arm: use clz32() instead of a for loopAurelien Jarno1-4/+2
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
2009-10-21Merge commit 'linux-user/linux-user-for-upstream' into stagingAnthony Liguori7-6/+145
2009-10-21qdev: add string property.Gerd Hoffmann2-0/+32
Patchworks-ID: 35755 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-21char: emit the OPENED event only when a new char connection is openedAmit Shah2-1/+8
The OPENED event gets sent also when qemu resets its state initially. The consumers of the event aren't interested in receiving this event on reset. Patchworks-ID: 35288 Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-21char: rename CHR_EVENT_RESET to CHR_EVENT_OPENEDAmit Shah6-6/+6
The char event RESET is emitted when a char device is opened. Give it a better name. Patchworks-ID: 35287 Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-21char: check for initial_reset_issued unnecessaryAmit Shah1-4/+1
At init, qemu_chr_reset is always called with initial_reset_issued set to 1. So checking for it to be set is not necessary. Patchworks-ID: 35286 Signed-off-by: Amit Shah <amit.shah@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2009-10-18bsd-user: fix breakage by 78cfb07fe0dc556cae662a0fab5fe1bd33daabdbBlue Swirl1-0/+1
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18Suppress warnings about 'warn_unused_result' attribute directiveBlue Swirl3-1/+26
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18bsd-user: FreeBSD updateJuergen Lock9-31/+462
basic FreeBSD sysarch(2) handling fixed syscall errno return Signed-off-by: Juergen Lock <nox@jelal.kn-bremen.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18x86: add 'static' to please SparseBlue Swirl1-5/+5
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-18target-ppc: simpler definitions for microcontrollers based on e300Thomas Monjalon1-68/+44
No need to alias e300 core for each CPU package. Differences between microcontrollers have to be implemented in a higher layer than translate_init.c Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: add declarations of microcontrollers based on e300Thomas Monjalon1-8/+40
Add CPU declarations of MPC8343, MPC8343E, MPC8347 and MPC8347E. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-ppc: better support of e300 CPU coreThomas Monjalon1-2/+8
Declare HID2 register. Use high BATs for e300 (8 instead of 4). Fix index of high BATs registers. Before the fix, IBAT4-7 were overwriting IBAT0-3. Signed-off-by: François Armand <francois.armand@os4i.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-arm: fix bugs introduced by 1b2b1e547bd912b7d3c4863d0a0f75f6f38330edAurelien Jarno1-5/+7
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate correct code when rn = 15. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-18target-arm: fix bugs introduced by 3174f8e91fecf8756e861d1febb049f3c619a2c7Aurelien Jarno1-3/+3
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate correct code when rn = 15. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove T0 and T1Aurelien Jarno1-2/+0
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove cpu_T for ARM once and for allFilip Navara2-35/+0
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert VFP not to use cpu_TFilip Navara1-28/+22
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_iwmmxt_insn not to use cpu_TFilip Navara1-252/+219
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_dsp_insn not use cpu_TFilip Navara1-39/+20
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_neon_ls_insn not to use cpu_TFilip Navara1-33/+34
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert disas_neon_data_insn and helpers not to use cpu_TFilip Navara1-296/+271
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_TFilip Navara1-41/+56
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: replace thumb usage of cpu_T registers by proper register ↵Filip Navara1-129/+139
allocations The goal is eventually to get rid of all cpu_T register usage and to use just short-lived tmp/tmp2 registers. This patch converts all the places where cpu_T was used in the Thumb code and replaces it with explicit TCG register allocation. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: fix TANDC and TORC instructionsFilip Navara1-0/+2
Uninitialized register was used instead of proper TCG variable. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCGFilip Navara3-73/+142
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16 helpers used fixed registers to return values. This patch replaces that with TCG code, so T0/T1 is no longer directly used by the helper functions. Bugs in the gen_neon_unzip register load code were also fixed. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: convert gen_lookup_tb not to use cpu_TFilip Navara1-2/+1
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: get rid of gen_set_psr_T0 and replace it by ↵Filip Navara1-20/+24
gen_set_psr/gen_set_psr_im Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: fix SRS/RFE instructionsFilip Navara1-15/+16
The encoding of 'IA' and 'DB' conditions was swapped. SRS instruction must store banked SPSR instead of CPSR at the specific address. Missing 'return' statement at the end of RFE handling. Fixed write-back code to reference correct registers. From: Hyeonsung Jang <hsjang@ok-labs.com> Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove unused gen_movl_T2_reg functionFilip Navara1-5/+0
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: remove useless line that sets register that is never used againFilip Navara1-1/+0
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: get rid of temporary variable cacheFilip Navara1-28/+3
The temporary variable cache in no longer need since tcg_temp_free was introduced. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17target-arm: use tcg_global_mem_new_i32 to allocate registersFilip Navara1-17/+23
Currently each read/write of ARM register involves a LD/ST TCG operation. This patch uses TCG memory-backed registers to represent the ARM register set. With memory-backed registers the LD/ST operations are transparently generated by TCG and host registers could be used to optimize the generated code. Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2009-10-17Re: linux-user/syscall.c - don't add GUEST_BASE to NULL pointerJan-Simon Möller1-2/+6
This patch fixes the mount call. GUEST_BASE shouldn't be added to a NULL pointer on arg5 . failing call: mount("rootfs", "/", 0x47a78, MS_MGC_VAL|MS_REMOUNT, 0x10000) = -1 EFAULT (Bad address) correct call: mount("rootfs", "/", 0x37ab0, MS_MGC_VAL|MS_REMOUNT, NULL) = 0 Signed-off-by:  Jan-Simon Möller  <dl9pf@gmx.de> Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
2009-10-17Only IDE needs limits for CHS configurationBlue Swirl1-3/+3
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2009-10-17linux-user: KD/VT/FB ioctlsUlrich Hecht4-0/+83
everything needed to run SDL on a framebuffer device in the userspace emulator Signed-off-by: Ulrich Hecht <uli@suse.de> Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
2009-10-16linux-user: Update ARM hwcapsRiku Voipio1-1/+8
Update ARM hwcaps to match Linux kernel 2.6.31 state Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
2009-10-16linux-user: don't zero a buffer twicePaul Bolle1-1/+0
prepare_binprm() zeroes bprm->buf. That buffer is already zeroed in main() and hasn't been touched since so that is not necessary. Signed-off-by: Paul Bolle <pebolle@tiscali.nl> Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
2009-10-15linux-user: fix ppc target_stat64 st_blocks layoutMax Filippov1-1/+1
Swap __pad1 and st_blocks fields location to maintain proper alignment. This fixes incorrect 'du' and 'stat' report on ppc guest. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
generated by cgit v1.1 at 2025-02-05 20:08:17 +0000