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2012-10-12hw/ds1338: Remove 'now' field from state structPeter Maydell1-20/+21
The 'struct tm now' field in the state structure is in fact only ever used as a temporary (the actual RTC state is held in 'offset'). Remove it from the state structure in favour of using local variables to avoid confusion about whether it needs to be saved on migration. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-12hw/ds1338: Recapture current time when register pointer wraps aroundPeter Maydell1-17/+42
The DS1338 datasheet documents that the current time is captured into the secondary registers when the register pointer wraps round to zero as well as at a START condition. Implement this. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-12hw/ds1338: Fix mishandling of register pointerPeter Maydell1-7/+13
Correct several deficiencies in the handling of the register pointer: * it should wrap around after 0x3f, not 0xff * guard against the caller handing us an out of range pointer (on h/w this can never happen, because only a 7 bit value is transferred over the I2C bus) * there was confusion over whether nvram[] holds only the 56 bytes of guest-accessible NVRAM, or also the secondary registers which hold the value of the clock captured at the start of a multibyte read. Correct to consistently be the latter, by fixing the array size and the offset used for NVRAM writes. * ds1338_send was attempting to use 'data' as both the data and the register offset simultaneously, which meant that writes to any register were broken; fix to use the register pointer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-12hw/arm_gic.c: Fix improper DPRINTF output.Evgeny Voevodin1-1/+1
s->cpu_enabled is an array, so s->cpu_enabled ? "En" : "Dis" returns "En" always. We should use s->cpu_enabled[cpu] here. Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-12cadence_ttc: Fix 'clear on read' behaviorSoren Brinkmann1-1/+1
A missing call to qemu_set_irq() when reading the IRQ register required SW to write to the IRQ register to acknowledge an interrupt. With this patch the behavior is fixed: - Reading the interrupt register clears it and updates the timers interrupt status - Writes to the interrupt register are ignored Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10ssi: Add slave autoconnect helperPeter Crosthwaite4-3/+44
Added helper function to automatically connect SPI slaves based on the QOM child nodes of a device. A SSI master device can call this routine to automatically hook-up all child nodes to its SPI bus. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10MAINTAINERS: Added maintainerships for SSIPeter A. G. Crosthwaite1-0/+8
Added maintainership for SSI, M25P80 and the Xilinx SPI controllers. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10xilinx_zynq: Added SPI controllers + flashesPeter A. G. Crosthwaite1-0/+34
Added the two SPI controllers to the zynq machine model. Attached two SPI flash devices to each controller. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10xilinx_spips: Xilinx Zynq SPI cntrlr device modelPeter A. G. Crosthwaite2-0/+353
Added device model for the Xilinx Zynq SPI controller (SPIPS). Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10petalogix-ml605: added SPI controller with n25q128Peter A. G. Crosthwaite1-0/+27
Added SPI controller to the reference design, with two n25q128 spi-flashes connected. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10xilinx_spi: Initial impl. of Xilinx SPI controllerPeter A. G. Crosthwaite2-0/+384
Device model for xilinx XPS SPI controller (v2.0) Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-10-10m25p80: Initial implementation of SPI flash devicePeter A. G. Crosthwaite5-0/+604
Added device model for m25p80 style SPI flash family. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-10-10hw: Added generic FIFO API.Peter A. G. Crosthwaite3-0/+178
Added a FIFO API that can be used to create and operate byte FIFOs. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-10-10stellaris: Removed SSI muxPeter A. G. Crosthwaite3-78/+18
Removed the explicit SSI mux and wired the CS line directly up to the SSI devices. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com>
2012-10-10qdev: allow multiple qdev_init_gpio_in() callsPeter A. G. Crosthwaite3-11/+33
Allow multiple qdev_init_gpio_in() calls for the one device. The first call will define GPIOs 0-N-1, the next GPIOs N- ... . Allows different GPIOs to be handled with different handlers. Needed when two levels of the QOM class heirachy both define GPIO functionality, as a single GPIO handler with an index selecter is not possible. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10ssi: Added create_slave_no_init()Peter A. G. Crosthwaite2-2/+8
Slave creation function that can be used to create an SSI slave without qdev_init() being called. This give machine models a chance to set properties. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10ssi: Implemented CS behaviourPeter A. G. Crosthwaite9-16/+118
Added default CS behaviour for SSI slaves. SSI devices can set a property to enable CS behaviour which will create a GPIO on the device which is the CS. Tristating of the bus on SSI transfers is implemented. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-10ssi: Support for multiple attached devicesPeter A. G. Crosthwaite1-15/+9
Removed assertion that only one device is attached to the SSI bus. When multiple devices are attached, all slaves have their transfer function called for transfers. Each device is responsible for knowing whether or not its CS is active, and if not returning 0. The returned data is the logical or of all responses from the (mulitple) devices. Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@petalogix.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
2012-10-07Merge branch 'master' of git.qemu.org:/pub/git/qemuBlue Swirl1-1/+1
* 'master' of git.qemu.org:/pub/git/qemu: qemu-barrier: Fix compilation on i386 hosts
2012-10-07qemu-barrier: Fix compilation on i386 hostsAurelien Jarno1-1/+1
Commit 1d31fca470648ec66afd8743491bfb5846306341 tried to fix bug introduced by 610b823ef66b993660f1ab1447a769f190e4f3b3 by including qemu-common.h, which breaks the build further. Include compiler.h instead, as suggested by Blue Swirl. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-07target-sparc: Optimize conditionals using SUBCCRichard Henderson1-61/+131
Aka "normal" comparisons. We now have the infrastructure to pass back non-boolean results from gen_compare. This will automatically get used by both branches and conditional moves. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Fall through from not-taken trapRichard Henderson1-5/+7
Now that we've cleaned up global temporary allocation, we can continue translating the fallthru path of a conditional trap. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Cleanup "global" temporary allocationRichard Henderson1-19/+19
There are 6 temporaries that disas_sparc_insn relies on having been allocated. Now that they are no longer referenced across branches, they need not be allocated as local temps. Move the allocation/free of these temporaries to make it clear that they are local to the translation of a single insn. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use movcond for FMOV*RRichard Henderson1-30/+16
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use movcond in mulsccRichard Henderson1-6/+5
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Move taddcctv and tsubcctv out of lineRichard Henderson3-102/+66
The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Note that gen_op_t{add,sub}_cc were identical to gen_op_{add,sub}_cc. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy TccRichard Henderson1-38/+53
Share more code between unconditional and conditional paths. Move the computation of the trap number into the conditional BB; avoid using temporaries that have gone out of scope (cpu_tmp32) or rely on local temps (cpu_dst). Fully fold the exception number when the trap number is %g0+imm. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Move sdivx and udivx out of lineRichard Henderson5-52/+37
The branches around the exception are maintaining an otherwise unnecessary use of local temps for the cpu destination. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use movcond in gen_generic_branchRichard Henderson1-11/+7
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare and movcond in MOVRRichard Henderson1-17/+14
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare and movcond in MOVCCRichard Henderson1-24/+20
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare and movcond in FMOVR, FMOVCCRichard Henderson1-117/+86
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Use DisasCompare in TccRichard Henderson1-9/+11
Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Introduce DisasCompare and functions to generate itRichard Henderson1-9/+83
For the moment gen_cond et al retain their existing interface, using setcond to turn a (potential) comparison back into a boolean. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy gen_generic_branch interfaceRichard Henderson1-8/+7
The arguments passed are always the same. Pass down just DisasContext instead. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy save_npc interfaceRichard Henderson1-4/+4
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy gen_mov_pc_npc interfaceRichard Henderson1-6/+6
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy save_state interfaceRichard Henderson1-49/+49
Use the cpu_cond global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy gen_trap_ifnofpu interfaceRichard Henderson1-18/+28
We always pass cpu_cond to the cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy flush_cond interfaceRichard Henderson1-5/+5
We always pass cpu_cond to the cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy do_branch interfacesRichard Henderson1-20/+18
We always pass cpu_cond to the r_cond parameter. Use that global register directly instead of passing it down. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Make CPU_LOG_INT useful by defaultRichard Henderson2-11/+4
No need for ifdefs when the log mask does just as well. No need to print pc/npc when we're dumping the whole cpu state. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07target-sparc: Tidy cpu_dump_stateRichard Henderson1-4/+3
We don't really need to be told that %g are general register, etc. Issue a trailing newline to separate blocks. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-07tcg: Remove redundant pointer from TCGContextStefan Weil2-3/+1
The pointer entry 'temps' always refers to the array entry 'static_temps'. Removing the pointer and renaming 'static_temps' to 'temps' reduces the size of TCGContext (4 or 8 byte) and allows better code generation. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-10-06Merge branch 'target-arm.for-upstream' of ↵Aurelien Jarno14-238/+183
git://git.linaro.org/people/pmaydell/qemu-arm * 'target-arm.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm: target-arm: Drop unused DECODE_CPREG_CRN macro target-arm: use deposit instead of hardcoded version target-arm: mark a few integer helpers const and pure target-arm: convert sar, shl and shr helpers to TCG target-arm: convert add_cc and sub_cc helpers to TCG target-arm: use globals for CC flags target-arm: Reinstate display of VFP registers in cpu_dump_state cpu_dump_state: move DUMP_FPU and DUMP_CCOP flags from x86-only to generic
2012-10-06Merge branch 'trivial-patches' of git://github.com/stefanha/qemuAurelien Jarno54-111/+56
* 'trivial-patches' of git://github.com/stefanha/qemu: versatilepb: Use symbolic indices for ARM PIC qdev: kill bogus comment qemu-barrier: Fix compiler version check for future gcc versions hw: Add missing 'static' attribute for QEMUMachine cleanup useless return sentence qemu-sockets: Fix compiler warning (regression for MinGW) vnc: Fix spelling (hellmen -> hellman) in comment slirp: Fix spelling in comment (enought -> enough, insure -> ensure) tcg/arm: Use tcg_out_mov_reg rather than inline equivalent code cpu: Add missing 'static' attribute to qemu_global_mutex configure: Support empty target list (--target-list=) hw: Fix return value check for bdrv_read, bdrv_write
2012-10-06Merge branch 'ppc-for-upstream' of git://repo.or.cz/qemu/agrafAurelien Jarno21-430/+569
* 'ppc-for-upstream' of git://repo.or.cz/qemu/agraf: (35 commits) PPC: KVM: Fix BAT put PPC: e500: Only expose even TLB sizes in initial TLB ppc/pseries: Reset VPA registration on CPU reset pseries: Don't test for MSR_PR for hypercalls under KVM PPC: e500: calculate initrd_base like dt_base PPC: e500: increase DTC_LOAD_PAD device tree: simplify dumpdtb code fdt: move dumpdtb interpretation code to device_tree.c target-ppc: Remove unused power_mode field from cpu state pseries: Set hash table size based on RAM size pseries: Remove unnecessary locking from PAPR hash table hcalls ppc405_uc: Fix buffer overflow target-ppc: KVM: Fix some kernel version edge cases for kvmppc_reset_htab() pseries: Fix semantics of RTAS int-on, int-off and set-xive functions pseries: Rework implementation of TCE bypass pseries: Remove never used flags field from spapr vio devices pseries: Remove XICS irq type enum type pseries: Remove C bitfields from xics code pseries: Small cleanup to H_CEDE implementation pseries: Fix XICS reset ...
2012-10-06qemu-barrier: Fix compilation on i386 hostsStefan Weil1-0/+2
Commit 610b823ef66b993660f1ab1447a769f190e4f3b3 uses QEMU_GNUC_PREREQ on i386 hosts. That macro is defined in qemu-common.h which is not always included before qemu-barrier.h, so compilation on i386 hosts was broken. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: Add tcg_high_condRichard Henderson2-15/+19
The table that was recently added for hppa is generally usable. And with the renumbering of the TCG_COND constants it's not too difficult to compute rather than have a table. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2012-10-06tcg: Add TCG_COND_NEVER, TCG_COND_ALWAYSRichard Henderson11-41/+102
There are several cases that can be handled easier inside both translators and code generators if we have out-of-band values for conditions. It's easy enough to handle ALWAYS and NEVER in the natural way inside the tcg middle-end. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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