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2017-07-21Merge remote-tracking branch 'remotes/yongbok/tags/mips-20170721' into stagingPeter Maydell7-120/+660
MIPS patches 2017-07-21 Changes: * Add Enhanced Virtual Addressing (EVA) support # gpg: Signature made Fri 21 Jul 2017 03:25:15 BST # gpg: using RSA key 0x2238EB86D5F797C2 # gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA 2B5C 2238 EB86 D5F7 97C2 * remotes/yongbok/tags/mips-20170721: target/mips: Enable CP0_EBase.WG on MIPS64 CPUs target/mips: Add EVA support to P5600 target/mips: Implement segmentation control target/mips: Add segmentation control registers target/mips: Add an MMU mode for ERL target/mips: Abstract mmu_idx from hflags target/mips: Check memory permissions with mem_idx target/mips: Decode microMIPS EVA load & store instructions target/mips: Decode MIPS32 EVA load & store instructions target/mips: Prepare loads/stores for EVA target/mips: Add CP0_Ebase.WG (write gate) support target/mips: Weaken TLB flush on UX,SX,KX,ASID changes target/mips: Fix TLBWI shadow flush for EHINV,XI,RI target/mips: Fix MIPS64 MFC0 UserLocal on BE host Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-21Merge remote-tracking branch ↵Peter Maydell23-59/+488
'remotes/stsquad/tags/pull-ci-updates-for-softfreeze-180717-2' into staging Final CI updates for soft-freeze Tweaks from Paolo for J=x Travis compiles Bunch of updated cross-compile targets from Philippe Additional debug tools in travis image from Me # gpg: Signature made Tue 18 Jul 2017 11:00:26 BST # gpg: using RSA key 0xFBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-ci-updates-for-softfreeze-180717-2: (32 commits) docker: install clang since Shippable setup_ve() verify it is available docker: warn users to use newer debian8/debian9 base image docker: add debian Ports base image shippable: add win32/64 targets docker: add MXE (M cross environment) base image for MinGW-w64 shippable: add mips64el targets docker: add debian/mips64el image shippable: use debian/mips[eb] targets docker: add debian/mips[eb] images shippable: add powerpc target docker: add debian/powerpc based on Jessie docker: add 'apt-fake' script which generate fake debian packages docker: add qemu:debian-jessie based on outdated jessie release shippable: add x86_64 targets shippable: add ppc64el targets shippable: add armel targets docker: enable nettle to extend code coverage on arm64 docker: enable gcrypt to extend code coverage on amd64 docker: enable netmap to extend code coverage on amd64 docker: enable virgl to extend code coverage on amd64 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-21bsd-user/elfload.c: Fix set-but-not-used warningsPeter Maydell1-6/+4
Fix various warnings about set-but-not-used variables on OpenBSD: bsd-user/elfload.c:1158:15: warning: variable 'mapped_addr' set but not used [-Wunused-but-set-variable] bsd-user/elfload.c:1165:9: warning: variable 'status' set but not used [-Wunused-but-set-variable] bsd-user/elfload.c:1168:15: warning: variable 'elf_stack' set but not used [-Wunused-but-set-variable] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500395194-21455-3-git-send-email-peter.maydell@linaro.org
2017-07-21bsd-user/mmap.c: Move __thread attribute to right placePeter Maydell1-1/+1
Avoid a compiler warning on OpenBSD: bsd-user/mmap.c:28:1: warning: '__thread' is not at beginning of declaration [-Wold-style-declaration] by moving the __thread attribute to its proper place. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 1500395194-21455-2-git-send-email-peter.maydell@linaro.org
2017-07-21Use qemu_tolower() and qemu_toupper(), not tolower() and toupper()Peter Maydell4-5/+5
On NetBSD, where tolower() and toupper() are implemented using an array lookup, the compiler warns if you pass a plain 'char' to these functions: gdbstub.c:914:13: warning: array subscript has type 'char' This reflects the fact that toupper() and tolower() give undefined behaviour if they are passed a value that isn't a valid 'unsigned char' or EOF. We have qemu_tolower() and qemu_toupper() to avoid this problem; use them. (The use in scsi-generic.c does not trigger the warning because it passes a uint8_t; we switch it anyway, for consistency.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: Christian Borntraeger <borntraeger@de.ibm.com> for the s390 part. Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-id: 1500568290-7966-1-git-send-email-peter.maydell@linaro.org
2017-07-21util/oslib-posix.c: Avoid warning on NetBSDPeter Maydell1-1/+1
On NetBSD the compiler warns: util/oslib-posix.c: In function 'sigaction_invoke': util/oslib-posix.c:589:5: warning: missing braces around initializer [-Wmissing-braces] siginfo_t si = { 0 }; ^ util/oslib-posix.c:589:5: warning: (near initialization for 'si.si_pad') [-Wmissing-braces] because on this platform siginfo_t is defined as typedef union siginfo { char si_pad[128]; /* Total size; for future expansion */ struct _ksiginfo _info; } siginfo_t; Avoid this warning by initializing the struct with {} instead; this is a GCC extension but we use it all over the codebase already. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Message-id: 1500568341-8389-1-git-send-email-peter.maydell@linaro.org
2017-07-21target/mips: Enable CP0_EBase.WG on MIPS64 CPUsJames Hogan1-0/+2
Enable the CP0_EBase.WG (write gate) on the I6400 and MIPS64R2-generic CPUs. This allows 64-bit guests to run KVM itself, which uses CP0_EBase.WG to point CP0_EBase at XKPhys. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-21target/mips: Add EVA support to P5600James Hogan1-6/+8
Add the Enhanced Virtual Addressing (EVA) feature to the P5600 core configuration, along with the related Segmentation Control (SC) feature and writable CP0_EBase.WG bit. This allows it to run Malta EVA kernels. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Implement segmentation controlJames Hogan1-39/+152
Implement the optional segmentation control feature in the virtual to physical address translation code. The fixed legacy segment and xkphys handling is replaced with a dynamic layout based on the segmentation control registers (which should be set up even when the feature is not exposed to the guest). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Add segmentation control registersJames Hogan5-2/+150
The optional segmentation control registers CP0_SegCtl0, CP0_SegCtl1 & CP0_SegCtl2 control the behaviour and required privilege of the legacy virtual memory segments. Add them to the CP0 interface so they can be read and written when CP0_Config3.SC=1, and initialise them to describe the standard legacy layout so they can be used in future patches regardless of whether they are exposed to the guest. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Add an MMU mode for ERLJames Hogan2-4/+23
The segmentation control feature allows a legacy memory segment to become unmapped uncached at error level (according to CP0_Status.ERL), and in fact the user segment is already treated in this way by QEMU. Add a new MMU mode for this state so that QEMU's mappings don't persist between ERL=0 and ERL=1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Abstract mmu_idx from hflagsJames Hogan3-4/+10
The MIPS mmu_idx is sometimes calculated from hflags without an env pointer available as cpu_mmu_index() requires. Create a common hflags_mmu_index() for the purpose of this calculation which can operate on any hflags, not just with an env pointer, and update cpu_mmu_index() itself and gen_intermediate_code() to use it. Also update debug_post_eret() and helper_mtc0_status() to log the MMU mode with the status change (SM, UM, or nothing for kernel mode) based on cpu_mmu_index() rather than directly testing hflags. This will also allow the logic to be more easily updated when a new MMU mode is added. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Check memory permissions with mem_idxJames Hogan1-8/+9
When performing virtual to physical address translation, check the required privilege level based on the mem_idx rather than the mode in the hflags. This will allow EVA loads & stores to operate safely only on user memory from kernel mode. For the cases where the mmu_idx doesn't need to be overridden (mips_cpu_get_phys_page_debug() and cpu_mips_translate_address()), we calculate the required mmu_idx using cpu_mmu_index(). Note that this only tests the MIPS_HFLAG_KSU bits rather than MIPS_HFLAG_MODE, so we don't test the debug mode hflag MIPS_HFLAG_DM any longer. This should be fine as get_physical_address() only compares against MIPS_HFLAG_UM and MIPS_HFLAG_SM, neither of which should get set by compute_hflags() when MIPS_HFLAG_DM is set. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Decode microMIPS EVA load & store instructionsJames Hogan1-4/+115
Implement decoding of microMIPS EVA load and store instruction groups in the POOL31C pool. These use the same gen_ld(), gen_st(), gen_st_cond() helpers as the MIPS32 decoding, passing the equivalent MIPS32 opcodes as opc. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Decode MIPS32 EVA load & store instructionsJames Hogan1-0/+106
Implement decoding of MIPS32 EVA loads and stores. These access the user address space from kernel mode when implemented, so for each instruction we need to check that EVA is available from Config5.EVA & check for sufficient COP0 privilege (with the new check_eva()), and then override the mem_idx used for the operation. Unfortunately some Loongson 2E instructions use overlapping encodings, so we must be careful not to prevent those from being decoded when EVA is absent. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Prepare loads/stores for EVAJames Hogan1-35/+42
EVA load and store instructions access the user mode address map, so they need to use mem_idx of MIPS_HFLAG_UM. Update the various utility functions to allow mem_idx to be more easily overridden from the decoding logic. Specifically we add a mem_idx argument to the op_ld/st_* helpers used for atomics, and a mem_idx local variable to gen_ld(), gen_st(), and gen_st_cond(). Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Add CP0_Ebase.WG (write gate) supportJames Hogan6-15/+31
Add support for the CP0_EBase.WG bit, which allows upper bits to be written (bits 31:30 on MIPS32, or bits 63:30 on MIPS64), along with the CP0_Config5.CV bit to control whether the exception vector for Cache Error exceptions is forced into KSeg1. This is necessary on MIPS32 to support Segmentation Control and Enhanced Virtual Addressing (EVA) extensions (where KSeg1 addresses may not represent an unmapped uncached segment). It is also useful on MIPS64 to allow the exception base to reside in XKPhys, and possibly out of range of KSEG0 and KSEG1. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: minor changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Weaken TLB flush on UX,SX,KX,ASID changesJames Hogan2-2/+2
There is no need to invalidate any shadow TLB entries when the ASID changes or when access to one of the 64-bit segments has been disabled, since doing so doesn't reveal to software whether any TLB entries have been evicted into the shadow half of the TLB. Therefore weaken the tlb flushes in these cases to only flush the QEMU TLB. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Fix TLBWI shadow flush for EHINV,XI,RIJames Hogan1-2/+10
Writing specific TLB entries with TLBWI flushes shadow TLB entries unless an existing entry is having its access permissions upgraded. This is necessary as software would from then on expect the previous mapping in that entry to no longer be in effect (even if QEMU has quietly evicted it to the shadow TLB on a TLBWR). However it won't do this if only EHINV, XI, or RI bits have been set, even if that results in a reduction of permissions, so add the necessary checks to invoke the flush when these bits are set. Fixes: 2fb58b73746e ("target-mips: add RI and XI fields to TLB entry") Fixes: 9456c2fbcd82 ("target-mips: add TLBINV support") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Tested-by: Yongbok Kim <yongbok.kim@imgtec.com> [yongbok.kim@imgtec.com: cosmetic changes] Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20target/mips: Fix MIPS64 MFC0 UserLocal on BE hostJames Hogan1-2/+3
Using MFC0 to read CP0_UserLocal uses tcg_gen_ld32s_tl, however CP0_UserLocal is a target_ulong. On a big endian host with a MIPS64 target this reads and sign extends the more significant half of the 64-bit register. Fix this by using ld_tl to load the whole target_ulong and ext32s_tl to sign extend it, as done for various other target_ulong COP0 registers. Fixes: d279279e2b5c ("target-mips: implement UserLocal Register") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
2017-07-20Merge remote-tracking branch 'remotes/kraxel/tags/usb-20170720-pull-request' ↵Peter Maydell1-2/+4
into staging usb: Fix build with newer gcc # gpg: Signature made Thu 20 Jul 2017 09:44:55 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/usb-20170720-pull-request: usb: Fix build with newer gcc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20Merge remote-tracking branch 'remotes/kraxel/tags/ui-20170720-pull-request' ↵Peter Maydell2-3/+10
into staging ui fixes (vnc docs, keymaps) for 2.10 # gpg: Signature made Thu 20 Jul 2017 08:54:25 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/ui-20170720-pull-request: keymaps: fr-ca: more fixups vnc: Clarify documentation of QMP command change Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20tests: Handle $RANDOM not being supported by the shellPeter Maydell1-2/+2
In various places in our test makefiles and scripts we use the shell $RANDOM to create a random number. This is a bash specific extension, and doesn't work on other shells. With dash the shell doesn't complain, it just effectively always evaluates $RANDOM to 0: echo $((RANDOM + 32768)) => 32768 However, on NetBSD the shell will complain: "-sh: arith: syntax error: "RANDOM + 32768" which means that "make check" fails. Switch to using "${RANDOM:-0}" instead of $RANDOM, which will portably either give us a random number or zero. This means that on non-bash shells we don't get such good test coverage via the MALLOC_PERTURB_ setting, but we were already in that situation for non-bash shells. Our only other uses of $RANDOM (in tests/qemu-iotests/check and tests/qemu-iotests/162) are in shell scripts which use a #!/bin/bash line so they are always run under bash. Suggested-by: Eric Blake <eblake@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Fam Zheng <famz@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1500029117-6387-1-git-send-email-peter.maydell@linaro.org
2017-07-20configure: Don't build ivshmem tools unless CONFIG_IVSHMEM is setKamil Rytarowski3-2/+6
Don't try to build the ivshmem-server and ivshmem-client tools unless CONFIG_IVSHMEM is set. This fixes in passing a build bug on NetBSD, which fails to build the ivshmem tools because they use shm_open() and on NetBSD that requires linking against -lrt. Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500021225-4118-4-git-send-email-peter.maydell@linaro.org [PMM: moved some code into earlier patches; minor bugfixes; added commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20configure: Use an explicit CONFIG_IVSHMEM rather than CONFIG_EVENTFDKamil Rytarowski3-3/+12
Rather than relying on everywhere that cares about whether the host supports ivshmem using CONFIG_EVENTFD, make configure set an explicit CONFIG_IVSHMEM. Signed-off-by: Kamil Rytarowski <n54@gmx.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1500021225-4118-3-git-send-email-peter.maydell@linaro.org [PMM: split out from another patch, add commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20configure: Rename CONFIG_IVSHMEM to CONFIG_IVSHMEM_DEVICEPeter Maydell2-2/+2
The current CONFIG_IVSHMEM is confusing, because it looks like it's a flag for "do we have ivshmem support?", but actually it's a flag for "is the ivshmem PCI device being compiled?" (and implicitly "do we have ivshmem support?" is tested with CONFIG_EVENTFD). Rename it to CONFIG_IVSHMEM_DEVICE to clear this confusion up; shortly we will add a new CONFIG_IVSHMEM which really does indicate whether the host can support ivshmem. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Markus Armbruster <armbru@redhat.com> Message-id: 1500021225-4118-2-git-send-email-peter.maydell@linaro.org
2017-07-20Merge remote-tracking branch ↵Peter Maydell2-0/+44
'remotes/kraxel/tags/misc-20170720-pull-request' into staging git orderfile and editorconfig for 2.10 # gpg: Signature made Thu 20 Jul 2017 09:00:01 BST # gpg: using RSA key 0x4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" # Primary key fingerprint: A032 8CFF B93A 17A7 9901 FE7D 4CB6 D8EE D3E8 7138 * remotes/kraxel/tags/misc-20170720-pull-request: add editorconfig add scripts/git.orderfile Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20170719' into stagingPeter Maydell31-146/+218
Queued tcg and tcg code gen related cleanups # gpg: Signature made Thu 20 Jul 2017 00:32:00 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-tcg-20170719: tcg: Pass generic CPUState to gen_intermediate_code() tcg/tci: enable bswap16_i64 target/alpha: optimize gen_cvtlq() using deposit op target/sparc: optimize gen_op_mulscc() using deposit op target/sparc: optimize various functions using extract op target/ppc: optimize various functions using extract op target/m68k: optimize bcd_flags() using extract op target/arm: optimize aarch32 rev16 target/arm: Optimize aarch64 rev16 coccinelle: add a script to optimize tcg op using tcg_gen_extract() coccinelle: ignore ASTs pre-parsed cached C files tcg: Expand glue macros before stringifying helper names util/cacheinfo: Add missing include for ppc linux tcg/mips: reserve a register for the guest_base. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20Replace 'struct ucontext' with 'ucontext_t' typeKhem Raj9-22/+22
glibc used to have: typedef struct ucontext { ... } ucontext_t; glibc now has: typedef struct ucontext_t { ... } ucontext_t; (See https://sourceware.org/bugzilla/show_bug.cgi?id=21457 for detail and rationale for the glibc change) However, QEMU used "struct ucontext" in declarations. This is a private name and compatibility cannot be guaranteed. Switch to only using the standardized type name. Signed-off-by: Khem Raj <raj.khem@gmail.com> Message-id: 20170628204452.41230-1-raj.khem@gmail.com Cc: Kamil Rytarowski <kamil@netbsd.org> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> [PMM: Rewrote commit message, based mostly on the one from Nathaniel McCallum] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-20usb: Fix build with newer gccEric Blake1-2/+4
gcc 7 is pickier about our sources: hw/usb/bus.c: In function ‘usb_port_location’: hw/usb/bus.c:410:66: error: ‘%d’ directive output may be truncated writing between 1 and 11 bytes into a region of size between 0 and 15 [-Werror=format-truncation=] snprintf(downstream->path, sizeof(downstream->path), "%s.%d", ^~ hw/usb/bus.c:410:9: note: ‘snprintf’ output between 3 and 28 bytes into a destination of size 16 snprintf(downstream->path, sizeof(downstream->path), "%s.%d", ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ upstream->path, portnr); ~~~~~~~~~~~~~~~~~~~~~~~ But we know that there are at most 5 levels of USB hubs, with at most two digits per level; that plus the separating dots means we use at most 15 bytes (including trailing NUL) of our 16-byte field. Adding an assertion to show gcc that we checked for truncation is enough to shut up the false-positive warning. Inspired by an idea by Dr. David Alan Gilbert <dgilbert@redhat.com>. Signed-off-by: Eric Blake <eblake@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20170717151334.17954-1-eblake@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2017-07-20add editorconfigGerd Hoffmann1-0/+15
Add a .editorconfig file for qemu. Specifies the indent and tab style for various files (C code and Makefiles for starters). Most popular editors support this either natively or via plugin. Check http://editorconfig.org/ for details. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20170717101547.22295-1-kraxel@redhat.com
2017-07-20add scripts/git.orderfileGerd Hoffmann1-0/+29
Based on a old patch by Laszlo. Time to get this in ... Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Emilio G. Cota <cota@braap.org> Message-id: 20170717101632.23247-1-kraxel@redhat.com
2017-07-20keymaps: fr-ca: more fixupsGerd Hoffmann1-1/+9
Fixes: https://bugs.launchpad.net/qemu/+bug/533613 Cc: Thomas Huth <thuth@redhat.com> Suggested-by: Jérôme Poulin <jeromepoulin@gmail.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Message-id: 20170717133444.16743-1-kraxel@redhat.com
2017-07-20vnc: Clarify documentation of QMP command changeMarkus Armbruster1-2/+1
QMP command { "execute": "change", "arguments": { "device": "vnc", "target": "password", "arg": PWD } } behaves just like { "execute": "change-vnc-password", "arguments": { "password", "arg": PWD } } Their documentation differs, however. According to change-vnc-password's documentation, "an empty password [...] will set the password to the empty string", while change's documentation claims "no future logins will be allowed". The former is actually correct. Replace the incorrect claim by a reference to change-vnc-password. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-id: 1500448182-21376-1-git-send-email-armbru@redhat.com Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2017-07-19tcg: Pass generic CPUState to gen_intermediate_code()Lluís Vilanova24-64/+49
Needed to implement a target-agnostic gen_intermediate_code() in the future. Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Benneé <alex.benee@linaro.org> Reviewed-by: Emilio G. Cota <cota@braap.org> Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Message-Id: <150002025498.22386.18051908483085660588.stgit@frigg.lan> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19tcg/tci: enable bswap16_i64Philippe Mathieu-Daudé1-1/+0
Altough correctly implemented, bswap16_i64() never got tested/executed so the safety TODO() statement was never removed. Since it got now tested the TODO() can be removed. while running Alex Bennée's image aarch64-linux-3.15rc2-buildroot.img: Trace 0x7fa1904b0890 [0: ffffffc00036cd04] ---------------- IN: 0xffffffc00036cd24: 5ac00694 rev16 w20, w20 OP: ---- ffffffc00036cd24 0000000000000000 0000000000000000 ext32u_i64 tmp3,x20 ext16u_i64 tmp2,tmp3 bswap16_i64 x20,tmp2 movi_i64 tmp4,$0x10 shr_i64 tmp2,tmp3,tmp4 ext16u_i64 tmp2,tmp2 bswap16_i64 tmp2,tmp2 deposit_i64 x20,x20,tmp2,$0x10,$0x10 Linking TBs 0x7fa1904b0890 [ffffffc00036cd04] index 0 -> 0x7fa1904b0aa0 [ffffffc00036cd24] Trace 0x7fa1904b0aa0 [0: ffffffc00036cd24] TODO qemu/tci.c:1049: tcg_qemu_tb_exec() qemu/tci.c:1049: tcg fatal error Aborted Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Jaroslaw Pelczar <j.pelczar@samsung.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-Id: <20170718045540.16322-11-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/alpha: optimize gen_cvtlq() using deposit opPhilippe Mathieu-Daudé1-5/+3
Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170718045540.16322-10-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/sparc: optimize gen_op_mulscc() using deposit opPhilippe Mathieu-Daudé1-4/+1
Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170718045540.16322-9-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/sparc: optimize various functions using extract opPhilippe Mathieu-Daudé1-10/+5
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/ppc: optimize various functions using extract opPhilippe Mathieu-Daudé2-30/+15
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-by: David Gibson <david@gibson.dropbear.id.au> Message-Id: <20170718045540.16322-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/m68k: optimize bcd_flags() using extract opPhilippe Mathieu-Daudé1-2/+1
Done with the Coccinelle semantic patch scripts/coccinelle/tcg_gen_extract.cocci. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Acked-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170718045540.16322-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/arm: optimize aarch32 rev16Aurelien Jarno1-2/+4
Use the same mask to avoid having to load two different constants, as suggested by Richard Henderson. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-Id: <20170516230159.4195-2-aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19target/arm: Optimize aarch64 rev16Richard Henderson1-18/+6
It is much shorter to reverse all 4 half-words in parallel than extract, reverse, and deposit each in turn. Suggested-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19coccinelle: add a script to optimize tcg op using tcg_gen_extract()Philippe Mathieu-Daudé1-0/+107
The following thread was helpful while writing this script: https://github.com/coccinelle/coccinelle/issues/86 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170718045540.16322-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19coccinelle: ignore ASTs pre-parsed cached C filesPhilippe Mathieu-Daudé1-0/+2
files generated using coccinelle tool: 'spatch --use-cache' Reviewed-by: Eric Blake <eblake@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170718045540.16322-2-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19tcg: Expand glue macros before stringifying helper namesRichard Henderson1-6/+11
Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19util/cacheinfo: Add missing include for ppc linuxPhilippe Mathieu-Daudé1-0/+1
This include was forgotten when splitting cacheinfo.c out of tcg/ppc/tcg-target.inc.c (see commit b255b2c8). For a Centos7 host, the include path <signal.h> <bits/sigcontext.h> <asm/sigcontext.h> <asm/elf.h> <asm/auxvec.h> implicitly pulls in the desired AT_* defines. Not so for Debian Jessie. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20170711015524.22936-1-f4bug@amsat.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
2017-07-19tcg/mips: reserve a register for the guest_base.Jiang Biao1-4/+13
Reserve a register for the guest_base using ppc code for reference. By doing so, we do not have to recompute it for every memory load. Signed-off-by: Jiang Biao <jiang.biao2@zte.com.cn> Signed-off-by: Richard Henderson <rth@twiddle.net> Message-Id: <1499677934-2249-1-git-send-email-jiang.biao2@zte.com.cn>
2017-07-19Merge remote-tracking branch ↵Peter Maydell28-245/+1499
'remotes/berrange/tags/pull-qcrypto-2017-07-18-2' into staging Merge qcrypto 2017/07/18 v2 # gpg: Signature made Wed 19 Jul 2017 10:11:21 BST # gpg: using RSA key 0xBE86EBB415104FDF # gpg: Good signature from "Daniel P. Berrange <dan@berrange.com>" # gpg: aka "Daniel P. Berrange <berrange@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: DAF3 A6FD B26B 6291 2D0E 8E3F BE86 EBB4 1510 4FDF * remotes/berrange/tags/pull-qcrypto-2017-07-18-2: tests: crypto: add hmac speed benchmark support tests: crypto: add hash speed benchmark support tests: crypto: add cipher speed benchmark support crypto: hmac: add af_alg-backend hmac support crypto: hash: add afalg-backend hash support crypto: cipher: add afalg-backend cipher support crypto: introduce some common functions for af_alg backend crypto: hmac: add hmac driver framework crypto: hmac: introduce qcrypto_hmac_ctx_new for glib-backend crypto: hmac: introduce qcrypto_hmac_ctx_new for nettle-backend crypto: hmac: introduce qcrypto_hmac_ctx_new for gcrypt-backend crypto: hmac: move crypto/hmac.h into include/crypto/ crypto: hash: add hash driver framework crypto: cipher: add cipher driver framework crypto: cipher: introduce qcrypto_cipher_ctx_new for builtin-backend crypto: cipher: introduce qcrypto_cipher_ctx_new for nettle-backend crypto: cipher: introduce qcrypto_cipher_ctx_new for gcrypt-backend crypto: cipher: introduce context free function Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2017-07-19Merge remote-tracking branch 'remotes/rth/tags/pull-axp-20170718' into stagingPeter Maydell7-161/+194
Queued target/alpha patches # gpg: Signature made Wed 19 Jul 2017 05:42:55 BST # gpg: using RSA key 0xAD1270CC4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" # Primary key fingerprint: 9CB1 8DDA F8E8 49AD 2AFC 16A4 AD12 70CC 4DD0 279B * remotes/rth/tags/pull-axp-20170718: target/alpha: Log temp leaks target/alpha: Fix temp leak in gen_fbcond target/alpha: Fix temp leak in gen_call_pal target/alpha: Fix temp leak in gen_mtpr target/alpha: Fix temp leak in gen_bcond target/alpha: Merge several flag bytes into ENV->FLAGS target/alpha: Copy tb->flags into DisasContext target/alpha: Remove amask from tb->flags Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-14 11:11:58 +0000