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2012-12-11hw/arm_gic_common: Correct GICC_PMR reset value for newer GICsPeter Maydell2-2/+8
The GIC architecture specification for v1 and v2 GICs (as found on the Cortex-A9 and newer) states that the GICC_PMR reset value is zero; this differs from the 0xf0 reset value used on 11MPCore. The NVIC is different again in not having a CPU interface; since we share the GIC code we must force the priority mask field to allow through all interrupts. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-12-11hw/arm_gic: Fix comparison with priority mask registerPeter Maydell1-1/+1
The GIC spec states that only interrupts with higher priority than the value in the GICC_PMR priority mask register are passed through to the processor. We were incorrectly allowing through interrupts with a priority equal to the specified value: correct the comparison operation to match the spec. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-12-11hw/arm_boot, exynos4210, highbank: Fix secondary boot GIC initPeter Maydell3-8/+26
Fix the code in the secondary CPU boot stubs so that it correctly initialises the GIC rather than relying on bugs or implementation dependent aspects of the QEMU GIC implementation: * set the GIC_PMR.Priority field to all-ones, so that all interrupts are passed through. The default of all-zeroes means all interrupts are masked, and QEMU only booted because of a bug in the priority masking in our GIC implementation. * add a barrier after GIC setup and before WFI to ensure that GIC config is complete before we go into a possible low power state. This isn't needed with the software GIC model but could be required when using KVM and executing this code on the real hardware CPU. Note that of the three secondary stub implementations, only the common generic one needs to support both v6 and v7 DSB encodings; highbank and exynos4210 will always be v7 CPUs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Igor Mitsyanko <i.mitsyanko@samsung.com>
2012-12-10Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori16-132/+149
* afaerber/qom-cpu: target-i386: Postpone cpuid_level update to realize time target-i386: Use define for cpuid vendor string size target-i386: Separate feature string parsing from CPU model lookup target-i386/cpu.c: Coding style fixes qdev: qdev_create(): use error_report() instead of hw_error() sysemu.h: Include qemu-types.h instead of qemu-common.h Create qemu-types.h for struct typedefs qlist.h: Do not include qemu-common.h qga/channel-posix.c: Include headers it needs qapi/qmp-registry.c: Include headers it needs ui/vnc-palette.c: Include headers it needs user: Rename qemu-types.h to qemu-user-types.h user: Move *-user/qemu-types.h to main directory Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori19-48/+32
* stefanha/trivial-patches: pc_sysfw: Plug memory leak on pc_fw_add_pflash_drv() error path qemu-options: Fix space at EOL Fix spelling in comments and documentation Clean up pci_drive_hot_add()'s use of BlockInterfaceType arm: a9mpcore: remove un-used ptimer_iomem field target-sparc: Remove t0, t1 from CPUSPARCState target-m68k: Remove t1 from CPUM68KState target-alpha: Remove t0, t1 from CPUAlphaState s390x: Spelling fixes (endianess -> endianness, occured -> occurred) Fix comments (adress -> address, layed -> laid, wierd -> weird) Fix spelling (prefered -> preferred) configure: Remove stray debug output sd: Send debug printfery to stderr not stdout Conflicts: configure Resolve spelling conflict in configure. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'kraxel/acpi.1' into stagingAnthony Liguori11-415/+317
* kraxel/acpi.1: acpi: drop debug port q35: update lpc pci config space according to configured devices apci: switch piix4 pci hotplug to memory api acpi: remove acpi_gpe_blk apci: switch piix4 gpe to memory api acpi: fix piix4 smbus mapping acpi: switch smbus to memory api acpi: cleanup ich9 memory region apci: switch ich9 smi to memory api apci: switch ich9 gpe to memory api acpi: cleanup vt82c686 memory region acpi: cleanup piix4 memory region apci: switch evt to memory api apci: switch cnt to memory api apci: switch timer to memory api apci: switch vt82c686 to memory api apci: switch ich9 to memory api apci: switch piix4 to memory api Conflicts: hw/lpc_ich9.c Resolved merge conflict due to apm_init adding an argument. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'aneesh/for-upstream' into stagingAnthony Liguori1-29/+64
* aneesh/for-upstream: virtfs-proxy-helper: use setresuid and setresgid Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-10Merge remote-tracking branch 'kraxel/usb.74' into stagingAnthony Liguori13-9/+168
* kraxel/usb.74: usb-tablet: Allow connecting to ehci ehci: Lower timer freq when the periodic schedule is idle usb: Allow overriding of usb_desc at the device level usb: Don't allow USB_RET_ASYNC for interrupt packets usb: Call wakeup when data becomes available for all devices with int eps add pc-1.4 Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2012-12-08configure: Default to 'cc', not 'gcc'Peter Maydell1-2/+11
Default to 'cc' as our compiler, rather than 'gcc'. We used to have to insist on gcc when we still kept the CPU env in a fixed global register, but this is no longer necessary and we will now compile OK on clang as well as gcc. Using 'cc' should generally result in us using the most standard and maintained system compiler for the platform. (For instance on newer MacOS X 'gcc' exists but is an elderly compiler provided mostly for legacy reasons, and 'cc' (which is clang) is definitely the better choice.) On Linux there will generally be no user-visible change since cc will be gcc. This changeover necessitates a slight reworking of how we set the 'cc' variable, because GNU cross toolchains generally provide a '${cross_prefix}gcc' but not a '${cross_prefix}cc'. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08linux-user: Merge pread/pwrite into pread64/pwrite64Peter Maydell6-32/+8
The Linux syscalls underlying pread() and pwrite() take a 64 bit offset on all architectures, even if some of them name the syscall "pread/pwrite" rather than "pread64/pwrite64" for historical reasons. So move the four QEMU target architectures (arm, i386, sparc, unicore32) which were defining TARGET_NR_pread/pwrite to define TARGET_NR_pread64/pwrite64 instead, and drop the TARGET_NR_pread/pwrite implementation code completely. (Based on examination of the kernel sources for the four architectures this patch affects.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: use movcond where possibleMax Filippov1-50/+42
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX opcodes. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: add s32c1i unit testsMax Filippov2-0/+40
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: add SR accessibility unit testsMax Filippov3-1/+92
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: implement MISC SRMax Filippov3-0/+6
The Miscellaneous Special Registers Option provides zero to four scratch registers within the processor readable and writable by RSR, WSR, and XSR. These registers are privileged. They may be useful for some application-specific exception and interrupt processing tasks in the kernel. The MISC registers are undefined after reset. See ISA, 4.7.3 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: better control rsr/wsr/xsr access to SRsMax Filippov1-19/+30
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs, and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal opcode exception on illegal access to these SRs. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: restrict available SRs by enabled optionsMax Filippov3-105/+130
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr, xsr) are associated with their corresponding SR and raise illegal opcode exception in case the register is not configured for the core. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: implement CACHEATTR SRMax Filippov5-1/+25
In XEA1, the Options for Memory Protection and Translation and the corresponding TLB management instructions are not available. Instead, functionality similar to the Region Protection Option is available through the cache attribute register. See ISA, A.2.14 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08target-xtensa: implement ATOMCTL SRMax Filippov7-14/+131
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory type. See ISA, 4.3.12.4 for details. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl6-15/+55
* 'master' of git.qemu-project.org:/pub/git/qemu: target-mips: Fix incorrect shift for SHILO and SHILOV target-mips: Fix incorrect code and test for INSV xilinx_uartlite: Accept input after rx FIFO pop xilinx_uartlite: suppress "cannot receive message" xilinx_axienet: Implement R_IS behaviour
2012-12-08finally kill cpudef config section supportEduardo Habkost1-49/+0
The external CPU models were removed on QEMU 1.2, and the support for the "cpudef" config sections was documented as deprecated, but the actual removal of the config section was pending. Now that QEMU 1.3 was released, we can finally kill the support for cpudef config sections, and support only the built-in CPU models from target-i386/cpu.c. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08Merge branch 'memory-ioport' of git://github.com/afaerber/qemu-cpuBlue Swirl13-78/+178
* 'memory-ioport' of git://github.com/afaerber/qemu-cpu: hw/dma.c: Replace register_ioport_* hw/pc.c: Replace register_ioport_* serial: Replace register_ioport_* hw/cirrus_vga.c: Replace register_ioport_* hw/apm.c: Replace register_ioport_* isa: Add isa_address_space_io()
2012-12-08HACKING: List areas where we may rely on impdef C behaviourPeter Maydell1-0/+20
Add a section to HACKING saying which version of the C spec we use and describing the bits of implementation defined C compiler behaviour which C code in QEMU is allowed to rely on. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08pixman: require 0.18.4 or newerGerd Hoffmann1-2/+2
When older versions are found the internal pixman version is prefered. Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08TCG: Remove unused global gen_opc_ arrays.Evgeny Voevodin2-8/+0
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin16-46/+47
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin16-16/+16
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin15-33/+34
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08tcg/tcg.h: Duplicate global TCG gen_opc_ arrays into TCGContext.Evgeny Voevodin1-0/+3
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08curses: Remove OpenBSD workaroundBrad Smith1-4/+0
I removed the same sort of workaround for OpenBSD within the configure script with commit 4dcc3f5876fa638d5c35bd47be3b717ea74cc2e7 but didn't bother to grep further to come across this same chunk of code in the curses code itself. So the following diff removes the same workaround chunk within the curses code. Signed-off-by: Brad Smith <brad@comstyle.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-08exec: Advise huge pages for the TCG code gen bufferRichard Henderson1-0/+2
After allocating 32MB or more contiguous memory, huge pages would seem to be ideal. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
2012-12-07target-i386: Postpone cpuid_level update to realize timeIgor Mammedov1-3/+5
Delay capping cpuid_level to 7 to realize time so property setters for cpuid_7_0_ebx_features and "level" could be used in any order/time between x86_cpu_initfn() and x86_cpu_realize(). Signed-off-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-07pc_sysfw: Plug memory leak on pc_fw_add_pflash_drv() error pathMarkus Armbruster1-1/+3
Harmless, because we the error inevitably leads to another, fatal one in pc_system_flash_init(): PC system firmware (pflash) not available. Fix it anyway. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07qemu-options: Fix space at EOLMichal Privoznik1-1/+1
There's no need to add a space at the end of line. Moreover, it can make problems in some projects that store the help output into a file (and run couple of tests based on that) and have space at EOL forbidden. Signed-off-by: Michal Privoznik <mprivozn@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07Fix spelling in comments and documentationStefan Weil2-4/+4
These spelling bugs were found by codespell: supressing -> suppressing transfered -> transferred Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07Clean up pci_drive_hot_add()'s use of BlockInterfaceTypeMarkus Armbruster3-13/+8
pci_drive_hot_add() parameter type has the wrong type: int instead of BlockInterfaceType. It's actually redundant, so we can just drop it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07arm: a9mpcore: remove un-used ptimer_iomem fieldPeter Crosthwaite1-1/+0
I'm guessing this is a hangover from a previous coreification of the mptimer sub-module. This field is completely unused - removed. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07target-sparc: Remove t0, t1 from CPUSPARCStateRichard Henderson1-1/+0
These fields are no longer used. Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07target-m68k: Remove t1 from CPUM68KStateRichard Henderson1-3/+0
This field is no longer used. Cc: Paul Brook <paul@codesourcery.com> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07target-alpha: Remove t0, t1 from CPUAlphaStateRichard Henderson1-7/+0
These fields are no longer (or were never?) used. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07s390x: Spelling fixes (endianess -> endianness, occured -> occurred)Stefan Weil2-4/+4
Replace also "write into" by "write to". Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07Fix comments (adress -> address, layed -> laid, wierd -> weird)Stefan Weil3-5/+5
Remove also a duplicated 'the'. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07Fix spelling (prefered -> preferred)Stefan Weil2-4/+5
Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07configure: Remove stray debug outputPeter Maydell1-2/+0
Rather than printing a message saying we're silently falling back to gthread coroutines when running on MacOS, actually do it silently. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-07sd: Send debug printfery to stderr not stdoutPeter Crosthwaite1-2/+2
Some debug printfs for SD are coming up in stdout. Redirected them to stderr instead. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2012-12-06target-i386: Use define for cpuid vendor string sizeIgor Mammedov2-3/+5
Signed-off-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-06target-i386: Separate feature string parsing from CPU model lookupEduardo Habkost1-23/+46
Instead of parsing the whole cpu_model string inside cpu_x86_find_by_name(), first split it into the CPU model name and the full feature string, then parse the feature string into pieces. When using CPU model classes, those two pieces of information will be used at different moments (CPU model name will be used to find CPU class, feature string will be used after CPU object was created), so making the split in two steps will make it easier to refactor the code later. This should also help on the CPU properties work, that will just need to replace the cpu_x86_parse_featurestr() logic (and can keep the CPU model lookup code as-is). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-06target-i386/cpu.c: Coding style fixesEduardo Habkost1-14/+16
- Use spaces instead of tabs on cpu_x86_cpuid(). - Use braces on 'if' statement cpu_x86_find_by_name(). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-06qdev: qdev_create(): use error_report() instead of hw_error()Eduardo Habkost1-3/+5
hw_error() is specific for fatal hardware emulation errors, not for internal errors related to the qdev object/class abstraction or object initialization. Replace it with an error_report() call, followed by abort(). This will also help reduce dependencies of the qdev code (as hw_error() is from cpus.o, and depends on the CPU list from exec.o). Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-06sysemu.h: Include qemu-types.h instead of qemu-common.hEduardo Habkost1-1/+1
It just needs the Monitor and DeviceState typedefs, so it doesn't need all of qemu-common.h. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
2012-12-06Create qemu-types.h for struct typedefsEduardo Habkost3-61/+63
Instead of keeping all those struct typedefs in qemu-common.h, move it to a header that can be safely included by other headers, containing only the struct typedefs and not pulling in other dependencies. Also, move some of the qdev-core.h typedefs to the new file, too, so other headers don't need to include qdev-core.h only because of DeviceState and other typedefs. This will help us remove qemu-common.h dependencies from some headers later. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
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