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2019-12-17migration-test: Move -serial handling to common commandlineJuan Quintela1-25/+16
Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17migration-test: Move -name handling to common commandlineJuan Quintela1-13/+9
Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17migration-test: Move shmem handling to common commandlineJuan Quintela1-42/+34
Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17migration-test: Move memory size to common commandlineJuan Quintela1-19/+25
Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17migration-test: Move -machine to common commandlineJuan Quintela1-21/+30
Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17migration-test: Move hide_stderr to common commandlineJuan Quintela1-12/+8
Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17migration-test: Create cmd_soure and cmd_targetJuan Quintela1-19/+25
We are repeating almost everything for each machine while creating the command line for migration. And once for source and another for destination. We start putting there opts_src and opts_dst. Signed-off-by: Juan Quintela <quintela@redhat.com> Tested-by: Cornelia Huck <cohuck@redhat.com> #s390x Tested-by: Laurent Vivier <lvivier@redhat.com>
2019-12-17kvm: Reallocate dirty_bmap when we change a slotDr. David Alan Gilbert1-15/+29
kvm_set_phys_mem can be called to reallocate a slot by something the guest does (e.g. writing to PAM and other chipset registers). This can happen in the middle of a migration, and if we're unlucky it can now happen between the split 'sync' and 'clear'; the clear asserts if there's no bmap to clear. Recreate the bmap whenever we change the slot, keeping the clear path happy. Typically this is triggered by the guest rebooting during a migrate. Corresponds to: https://bugzilla.redhat.com/show_bug.cgi?id=1772774 https://bugzilla.redhat.com/show_bug.cgi?id=1771032 Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Reviewed-by: Peter Xu <peterx@redhat.com>
2019-12-17Merge remote-tracking branch ↵Peter Maydell43-9345/+26
'remotes/huth-gitlab/tags/pull-request-2019-12-17' into staging * Removal of the deprecated bluetooth code * Some qtest and misc patches # gpg: Signature made Tue 17 Dec 2019 08:09:08 GMT # gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5 # gpg: issuer "thuth@redhat.com" # gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full] # gpg: aka "Thomas Huth <thuth@redhat.com>" [full] # gpg: aka "Thomas Huth <huth@tuxfamily.org>" [full] # gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown] # Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5 * remotes/huth-gitlab/tags/pull-request-2019-12-17: tests: use g_test_rand_int tests/Makefile: Fix check-report.* targets shown in check-help glib: use portable g_setenv() hw/misc/ivshmem: Bury dead legacy INTx code pseries: disable migration-test if /dev/kvm cannot be used tests: fix modules-test 'duplicate test case' error Remove libbluetooth / bluez from the CI tests Remove the core bluetooth code hw/usb: Remove the USB bluetooth dongle device hw/arm/nseries: Replace the bluetooth chardev with a "null" chardev Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17Merge remote-tracking branch 'remotes/cleber/tags/python-next-pull-request' ↵Peter Maydell17-197/+284
into staging Python queue 2019-12-17 # gpg: Signature made Tue 17 Dec 2019 05:12:43 GMT # gpg: using RSA key 7ABB96EB8B46B94D5E0FE9BB657E8D33A5F209F3 # gpg: Good signature from "Cleber Rosa <crosa@redhat.com>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 7ABB 96EB 8B46 B94D 5E0F E9BB 657E 8D33 A5F2 09F3 * remotes/cleber/tags/python-next-pull-request: python/qemu: Remove unneeded imports in __init__ python/qemu: accel: Add tcg_available() method python/qemu: accel: Strengthen kvm_available() checks python/qemu: accel: Add list_accel() method python/qemu: Move kvm_available() to its own module Acceptance tests: use relative location for tests Acceptance tests: use avocado tags for machine type Acceptance tests: introduce utility method for tags unique vals Acceptance test x86_cpu_model_versions: use default vm tests/acceptance: Makes linux_initrd and empty_cpu_model use QEMUMachine python/qemu: Add set_qmp_monitor() to QEMUMachine analyze-migration.py: replace numpy with python 3.2 analyze-migration.py: fix find() type error Revert "Acceptance test: cancel test if m68k kernel packages goes missing" tests/boot_linux_console: Fetch assets from Debian snapshot archives Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.0-20191217' ↵Peter Maydell65-955/+2454
into staging ppc patch queue 2019-12-17 This is the first pull request for the qemu-5.0 branch. It has a lot of accumulated changes, including: * SLOF update to support boot using the IOMMU (will become necessary for secure guests) * Clean ups to pnv handling of chip models * A number of extensions to the powernv machine model * TCG extensions to allow powernv emulated systems to run KVM guests * Outline support for POWER10 chips in powernv * Cleanups to the ibm,client-architecture-support feature negotiation path * XIVE reworks to better handle the powernv machine * Improvements to not waste interrupt queues and other semi-scarce resources when using XIVE under KVM # gpg: Signature made Tue 17 Dec 2019 04:42:20 GMT # gpg: using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392 # gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full] # gpg: aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full] # gpg: aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full] # gpg: aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown] # Primary key fingerprint: 75F4 6586 AE61 A66C C44E 87DC 6C38 CACA 20D9 B392 * remotes/dgibson/tags/ppc-for-5.0-20191217: (88 commits) pseries: Update SLOF firmware image ppc/pnv: Drop PnvChipClass::type ppc/pnv: Introduce PnvChipClass::xscom_pcba() method ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom() ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() ppc/pnv: Introduce PnvChipClass::xscom_core_base() method ppc/pnv: Introduce PnvChipClass::intc_print_info() method ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat ppc/pnv: Drop PnvPsiClass::chip_type ppc/pnv: Introduce PnvPsiClass::compat ppc: Drop useless extern annotation for functions ppc/pnv: Fix OCC common area region mapping ppc/pnv: Introduce PBA registers ppc/pnv: Make PnvXScomInterface an incomplete type ppc/pnv: populate the DT with realized XSCOM devices ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodes target/ppc: Add SPR TBU40 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17Merge remote-tracking branch 'remotes/ehabkost/tags/x86-next-pull-request' ↵Peter Maydell2-28/+76
into staging x86 queue, 2019-12-16 Feature: * Cooperlake CPU model Cleanups: * Use g_autofree in a few places # gpg: Signature made Mon 16 Dec 2019 19:36:51 GMT # gpg: using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6 # gpg: issuer "ehabkost@redhat.com" # gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full] # Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF D1AA 2807 936F 984D C5A6 * remotes/ehabkost/tags/x86-next-pull-request: i386: Use g_autofree in a few places i386: Add new CPU model Cooperlake i386: Add macro for stibp i386: Add MSR feature bit for MDS-NO Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-12-17tests: use g_test_rand_intPaolo Bonzini3-7/+7
g_test_rand_int provides a reproducible random integer number, using a different number seed every time but allowing reproduction using the --seed command line option. It is thus better suited to tests than g_random_int or random. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1576113478-42926-1-git-send-email-pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17tests/Makefile: Fix check-report.* targets shown in check-helpWainer dos Santos Moschetta1-3/+1
The check-report.html and check-report.xml targets were replaced with check-report.tap in commit 9df43317b82 but the check-help text was not updated so it still lists check-report.html. Fixes: 9df43317b82 Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Message-Id: <20191211204427.4681-2-wainersm@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17glib: use portable g_setenv()Marc-André Lureau8-30/+6
We have a setenv() wrapper in os-win32.c that no one is actually using. Drop it and change to g_setenv() uniformly. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1576074210-52834-7-git-send-email-pbonzini@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17hw/misc/ivshmem: Bury dead legacy INTx codeMarkus Armbruster1-35/+0
Devices "ivshmem-plain" and "ivshmem-doorbell" support only MSI-X. Config space register Interrupt Pin is zero. Device "ivshmem" additionally supported legacy INTx, but it was removed in commit 5a0e75f0a9 "hw/misc/ivshmem: Remove deprecated "ivshmem" legacy device". The commit left ivshmem_update_irq() behind. Since the Interrupt Pin register is zero, the function does nothing. Remove it. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20191205203557.11254-1-armbru@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17pseries: disable migration-test if /dev/kvm cannot be usedLaurent Vivier1-1/+2
On ppc64, migration-test only works with kvm_hv, and we already have a check to verify the module is loaded. kvm_hv module can be loaded in memory and /sys/module/kvm_hv exists, but on some systems (like build systems) /dev/kvm can be missing (by administrators choice). And as kvm_hv exists test-migration is started but QEMU falls back to TCG because it cannot be used: Could not access KVM kernel module: No such file or directory failed to initialize KVM: No such file or directory Back to tcg accelerator And as the test is done with TCG, it fails. As for s390x, we must check for the existence and the access rights of /dev/kvm. Reported-by: Cole Robinson <crobinso@redhat.com> Signed-off-by: Laurent Vivier <lvivier@redhat.com> Message-Id: <20191120170955.242900-1-lvivier@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17tests: fix modules-test 'duplicate test case' errorCole Robinson1-1/+2
./configure --enable-sdl --audio-drv-list=sdl --enable-modules Will generate two identical test names: /$arch/module/load/sdl Which generates an error like: (tests/modules-test:23814): GLib-ERROR **: 18:23:06.359: duplicate test case path: /aarch64//module/load/sdl Add the subsystem prefix in the name as well, so instead we get: /$arch/module/load/audio-sdl /$arch/module/load/ui-sdl Signed-off-by: Cole Robinson <crobinso@redhat.com> Message-Id: <d64c9aa098cc6e5c0b638438c4959eddfa7e24e2.1573679311.git.crobinso@redhat.com> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17Remove libbluetooth / bluez from the CI testsThomas Huth4-4/+1
Since the bluetooth code has been removed, we don't need to test with this library anymore. Message-Id: <20191120091014.16883-5-thuth@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17Remove the core bluetooth codeThomas Huth19-8651/+0
It's been deprecated since QEMU v3.1. We've explicitly asked in the deprecation message that people should speak up on qemu-devel in case they are still actively using the bluetooth part of QEMU, but nobody ever replied that they are really still using it. I've tried it on my own to use this bluetooth subsystem for one of my guests, but I was also not able to get it running anymore: When I was trying to pass-through a real bluetooth device, either the guest did not see the device at all, or the guest crashed. Even worse for the emulated device: When running qemu-system-x86_64 -bt device:keyboard QEMU crashes once you hit a key. So it seems like the bluetooth stack is not only neglected, it is completely bitrotten, as far as I can tell. The only attention that this code got during the past years were some CVEs that have been spotted there. So this code is a burden for the developers, without any real benefit anymore. Time to remove it. Note: hw/bt/Kconfig only gets cleared but not removed here yet. Otherwise there is a problem with the *-softmmu/config-devices.mak.d dependency files - they still contain a reference to this file which gets evaluated first on some build hosts, before the file gets properly recreated. To avoid breaking these builders, we still need the file around for some time. It will get removed in a couple of weeks instead. Message-Id: <20191120091014.16883-4-thuth@redhat.com> Reviewed-by: Ján Tomko <jtomko@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
2019-12-17pseries: Update SLOF firmware imageAlexey Kardashevskiy3-1/+1
This fixes PCI bridges support regression. This enables IOMMU support in virtio drivers. The full list of changes is: Alexey Kardashevskiy (12): allocator: Fix format strings for DEBUG virtio: Make virtio_set_qaddr static client: Load initramdisk location sloffs: Fix -Wunused-result gcc warnings in read/write pci-phb: Reimplement dma-map-in/out virtio: Store queue descriptors in virtio_device virtio-net: Init queues after features negotiation virtio: Enable IOMMU ibm,client-architecture-support: Fix stack handling fdt: Fix updating the tree at H_CAS version: update to 20191206 version: update to 20191217 Michael Roth (1): dma: Define default dma methods for using by client/package instances Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Drop PnvChipClass::typeGreg Kurz2-14/+0
It isn't used anymore. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623844102.360005.12070225703151669294.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_pcba() methodGreg Kurz3-13/+25
The XSCOM bus is implemented with a QOM interface, which is mostly generic from a CPU type standpoint, except for the computation of addresses on the Pervasive Connect Bus (PCB) network. This is handled by the pnv_xscom_pcba() function with a switch statement based on the chip_type class level attribute of the CPU chip. This can be achieved using QOM. Also the address argument is masked with PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different sizes with other CPU types. Have each CPU chip type handle the appropriate computation with a QOM xscom_pcba() method. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623843543.360005.13996472463887521794.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpersGreg Kurz1-10/+0
They aren't used anymore. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623842986.360005.1787401623906380181.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom()Greg Kurz3-21/+14
Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "compatible" property. Just pass the compat string and its size as arguments. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623842430.360005.9513965612524265862.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom()Greg Kurz3-17/+14
Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "reg" property. Just pass the base address and address size as arguments. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623841868.360005.17577624823547136435.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PnvChipClass::xscom_core_base() methodGreg Kurz2-7/+25
The pnv_chip_core_realize() function configures the XSCOM MMIO subregion for each core of a single chip. The base address of the subregion depends on the CPU type. Its computation is currently open-code using the pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623841311.360005.4705705734873339545.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PnvChipClass::intc_print_info() methodGreg Kurz2-5/+26
The pnv_pic_print_info() callback checks the type of the chip in order to forward to the request appropriate interrupt controller. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. This also prepares ground for the upcoming interrupt controller of POWER10 chips. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623840755.360005.5002022339473369934.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpersGreg Kurz1-10/+0
They aren't used anymore. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623840200.360005.1300941274565357363.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PnvMachineClass::dt_power_mgt()Greg Kurz2-6/+12
We add an extra node to advertise power management on some machines, namely powernv9 and powernv10. This is achieved by using the pnv_is_power9() and pnv_is_power10() helpers. This can be achieved with QOM. Add a method to the base class for powernv machines and have it implemented by machine types that support power management instead. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623839642.360005.9243510140436689941.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compatGreg Kurz2-14/+31
The pnv_dt_create() function generates different contents for the "compatible" property of the root node in the DT, depending on the CPU type. This is open coded with multiple ifs using pnv_is_powerXX() helpers. It seems cleaner to achieve with QOM. Introduce a base class for the powernv machine and a compat attribute that each child class can use to provide the value for the "compatible" property. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623839085.360005.4046508784077843216.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> [dwg: Folded in small fix Greg spotted after posting] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-16python/qemu: Remove unneeded imports in __init__Wainer dos Santos Moschetta1-6/+0
__init_.py import some sub-modules unnecessarily. So let's clean it up. Signed-off-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Suggested-by: Cleber Rosa <crosa@redhat.com> Reviewed-by: Cleber Rosa <crosa@redhat.com> Tested-by: Cleber Rosa <crosa@redhat.com> Message-Id: <20191216191438.93418-6-wainersm@redhat.com> Signed-off-by: Cleber Rosa <crosa@redhat.com>
2019-12-17ppc/pnv: Drop PnvPsiClass::chip_typeGreg Kurz2-4/+0
It isn't used anymore. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623838530.360005.15470128760871845396.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PnvPsiClass::compatGreg Kurz2-14/+13
The Processor Service Interface (PSI) model has a chip_type class level attribute, which is used to generate the content of the "compatible" DT property according to the CPU type. Since the PSI model already has specialized classes for each supported CPU type, it seems cleaner to achieve this with QOM. Provide the content of the "compatible" property with a new class level attribute. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623837974.360005.14706607446188964477.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc: Drop useless extern annotation for functionsGreg Kurz2-14/+14
Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <157623837421.360005.412120366652768311.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Fix OCC common area region mappingCédric Le Goater4-11/+16
The OCC common area is mapped at a unique address on the system and each OCC is assigned a segment to expose its sensor data : ------------------------------------------------------------------------- | Start (Offset from | End | Size |Description | | BAR2 base address) | | | | ------------------------------------------------------------------------- | 0x00580000 | 0x005A57FF |150kB |OCC 0 Sensor Data Block| | 0x005A5800 | 0x005CAFFF |150kB |OCC 1 Sensor Data Block| | : | : | : | : | | 0x00686800 | 0x006ABFFF |150kB |OCC 7 Sensor Data Block| | 0x006AC000 | 0x006FFFFF |336kB |Reserved | ------------------------------------------------------------------------- Maximum size is 1.5MB. We could define a "OCC common area" memory region at the machine level and sub regions for each OCC. But it adds some extra complexity to the models. Fix the current layout with a simpler model. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191211082912.2625-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce PBA registersCédric Le Goater6-44/+134
The PBA bridge unit (Power Bus Access) connects the OCC (On Chip Controller) to the Power bus and System Memory. The PBA is used to gather sensor data, for power management, for sleep states, for initial boot, among other things. The PBA logic provides a set of four registers PowerBus Access Base Address Registers (PBABAR0..3) which map the OCC address space to the PowerBus space. These registers are setup by the initial FW and define the PowerBus Range of system memory that can be accessed by PBA. The current modeling of the PBABAR registers is done under the common XSCOM handlers. We introduce a specific XSCOM regions for these registers and fix : - BAR sizes and BAR masks - The mapping of the OCC common area. It is common to all chips and should be mapped once. We will address per-OCC area in the next change. - OCC common area is in BAR 3 on P8 Inspired by previous work of Balamuruhan S <bala24@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191211082912.2625-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Make PnvXScomInterface an incomplete typeGreg Kurz1-4/+2
PnvXScomInterface is an interface instance. It should never be dereferenced. Drop the dummy type definition for extra safety, which is the common practice with QOM interfaces. While here also convert the bogus OBJECT_CHECK() to INTERFACE_CHECK(). Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157608025541.186670.1577861507610404326.stgit@bahia.lan> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: populate the DT with realized XSCOM devicesCédric Le Goater1-1/+4
Some devices could be initialized in the instance_init handler but not realized for configuration reasons. Nodes should not be added in the DT for such devices. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191210135845.19773-3-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Loop on the whole hierarchy to populate the DT with the XSCOM nodesCédric Le Goater1-1/+6
Some PnvXScomInterface objects lie a bit deeper (PnvPBCQState) than the first layer, so we need to loop on the whole object hierarchy to catch them. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191210135845.19773-2-clg@kaod.org> Reviewed-by: Greg Kurz <groug@kaod.org> [dwg: Corrected error in comment] Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Add SPR TBU40Suraj Jitindar Singh5-0/+39
The spr TBU40 is used to set the upper 40 bits of the timebase register, present on POWER5+ and later processors. This register can only be written by the hypervisor, and cannot be read. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Add SPR ASDRSuraj Jitindar Singh2-0/+7
The Access Segment Descriptor Register (ASDR) provides information about the storage element when taking a hypervisor storage interrupt. When performing nested radix address translation, this is normally the guest real address. This register is present on POWER9 processors and later. Implement the ADSR, note read and write access is limited to the hypervisor. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Work [S]PURR implementation and add HV supportSuraj Jitindar Singh6-20/+30
The Processor Utilisation of Resources Register (PURR) and Scaled Processor Utilisation of Resources Register (SPURR) provide an estimate of the resources used by the thread, present on POWER7 and later processors. Currently the [S]PURR registers simply count at the rate of the timebase. Preserve this behaviour but rework the implementation to store an offset like the timebase rather than doing the calculation manually. Also allow hypervisor write access to the register along with the currently available read access. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Implement the VTB for HV accessSuraj Jitindar Singh7-4/+51
The virtual timebase register (VTB) is a 64-bit register which increments at the same rate as the timebase register, present on POWER8 and later processors. The register is able to be read/written by the hypervisor and read by the supervisor. All other accesses are illegal. Currently the VTB is just an alias for the timebase (TB) register. Implement the VTB so that is can be read/written independent of the TB. Make use of the existing method for accessing timebase facilities where by the compensation is stored and used to compute the value on reads/is updated on writes. Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com> [ clg: rebased on current ppc tree ] Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191128134700.16091-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: add a LPC Controller model for POWER10Cédric Le Goater4-12/+53
Same a POWER9, only the MMIO window changes. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-6-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: add a PSI bridge model for POWER10Cédric Le Goater5-8/+58
The POWER10 PSIHB controller is very similar to the one on POWER9. We should probably introduce a common PnvPsiXive object. The ESB page size should be changed to 64k when P10 support is ready. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-5-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/psi: cleanup definitionsCédric Le Goater1-2/+5
Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-4-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc/pnv: Introduce a POWER10 PnvChip and a powernv10 machineCédric Le Goater5-11/+232
This is an empty shell with the XSCOM bus and cores. The chip controllers will come later. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-3-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17target/ppc: Add POWER10 DD1.0 model informationCédric Le Goater5-6/+237
This includes in QEMU a new CPU model for the POWER10 processor with the same capabilities of a POWER9 process. The model will be extended when support is completed. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191205184454.10722-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-12-17ppc: Make PPCVirtualHypervisor an incomplete typeGreg Kurz1-4/+0
PPCVirtualHypervisor is an interface instance. It should never be dereferenced. Drop the dummy type definition for extra safety, which is the common practice with QOM interfaces. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157589808041.21182.18121655959115011353.stgit@bahia.lan> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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