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2018-08-15Merge remote-tracking branch 'remotes/armbru/tags/pull-misc-2018-08-15' into ↵Peter Maydell7-19/+27
staging Miscellaneous patches for 2018-08-15 # gpg: Signature made Wed 15 Aug 2018 07:15:31 BST # gpg: using RSA key 3870B400EB918653 # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * remotes/armbru/tags/pull-misc-2018-08-15: monitor: fix oob command leak tests: fix crumple/recursive leak qapi: Fix some pycodestyle-3 complaints tests: change /0.15/* tests to /qmp/* qmp-shell: learn to send commands with quoted arguments Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-15Merge remote-tracking branch ↵Peter Maydell13-57/+154
'remotes/famz/tags/block-and-testing-pull-request' into staging Block and testing patches for 3.1 - aio fixes by me - nvme fixes by Paolo and me - test improvements by Peter, Phil and me # gpg: Signature made Wed 15 Aug 2018 04:11:43 BST # gpg: using RSA key CA35624C6A9171C6 # gpg: Good signature from "Fam Zheng <famz@redhat.com>" # Primary key fingerprint: 5003 7CB7 9706 0F76 F021 AD56 CA35 624C 6A91 71C6 * remotes/famz/tags/block-and-testing-pull-request: aio-posix: Improve comment around marking node deleted tests/vm: Add vm-build-all/vm-clean-all in help text tests/vm: Use make's --output-sync option tests/vm: Bump guest RAM up from 2G to 4G tests/vm: Propagate V=1 down into the make inside the VM tests/vm: Pass the jobs parallelism setting to 'make check' tests: vm: Add vm-clean-all tests: Add centos VM testing tests: Allow overriding archive path with SRC_ARCHIVE tests: Add an option for snapshot (default: off) docker: Install more packages in centos7 aio: Do aio_notify_accept only during blocking aio_poll aio-posix: Don't count ctx->notifier as progress when polling nvme: simplify plug/unplug nvme: Fix nvme_init error handling tests/vm: Add flex and bison to the vm image tests/vm: Only use -cpu 'host' if KVM is available Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-15Merge remote-tracking branch ↵Peter Maydell30-499/+1725
'remotes/pmaydell/tags/pull-target-arm-20180814' into staging target-arm queue: * Implement more of ARMv6-M support * Support direct execution from non-RAM regions; use this to implmeent execution from small (<1K) MPU regions * GICv2: implement the virtualization extensions * support a virtualization-capable GICv2 in the virt and xlnx-zynqmp boards * arm: Fix return code of arm_load_elf() so we can detect failure to load the file correctly * Implement HCR_EL2.TGE ("trap general exceptions") bit * Implement tailchaining for M profile cores * Fix bugs in SVE compare, saturating add/sub, WHILE, MOVZ # gpg: Signature made Tue 14 Aug 2018 17:23:38 BST # gpg: using RSA key 3C2525ED14360CDE # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" # gpg: aka "Peter Maydell <pmaydell@gmail.com>" # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20180814: (45 commits) target/arm: Fix typo in helper_sve_movz_d target/arm: Reorganize SVE WHILE target/arm: Fix typo in do_sat_addsub_64 target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzw target/arm: Implement tailchaining for M profile cores target/arm: Restore M-profile CONTROL.SPSEL before any tailchaining target/arm: Initialize exc_secure correctly in do_v7m_exception_exit() target/arm: Improve exception-taken logging target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is set target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO} target/arm: Honour HCR_EL2.TGE when raising synchronous exceptions target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checks target/arm: Mask virtual interrupts if HCR_EL2.TGE is set arm: Fix return code of arm_load_elf arm/virt: Add support for GICv2 virtualization extensions xlnx-zynqmp: Improve GIC wiring and MMIO mapping intc/arm_gic: Improve traces intc/arm_gic: Implement maintenance interrupt generation intc/arm_gic: Implement gic_update_virt() function intc/arm_gic: Implement the virtual interface registers ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-15monitor: fix oob command leakMarc-André Lureau1-0/+2
Spotted by ASAN, during make check... Direct leak of 40 byte(s) in 1 object(s) allocated from: #0 0x7f8e27262c48 in malloc (/lib64/libasan.so.5+0xeec48) #1 0x7f8e26a5f3c5 in g_malloc (/lib64/libglib-2.0.so.0+0x523c5) #2 0x555ab67078a8 in qstring_from_str /home/elmarco/src/qq/qobject/qstring.c:67 #3 0x555ab67071e4 in qstring_new /home/elmarco/src/qq/qobject/qstring.c:24 #4 0x555ab6713fbf in qstring_from_escaped_str /home/elmarco/src/qq/qobject/json-parser.c:144 #5 0x555ab671738c in parse_literal /home/elmarco/src/qq/qobject/json-parser.c:506 #6 0x555ab67179c3 in parse_value /home/elmarco/src/qq/qobject/json-parser.c:569 #7 0x555ab6715123 in parse_pair /home/elmarco/src/qq/qobject/json-parser.c:306 #8 0x555ab6715483 in parse_object /home/elmarco/src/qq/qobject/json-parser.c:357 #9 0x555ab671798b in parse_value /home/elmarco/src/qq/qobject/json-parser.c:561 #10 0x555ab6717a6b in json_parser_parse_err /home/elmarco/src/qq/qobject/json-parser.c:592 #11 0x555ab4fd4dcf in handle_qmp_command /home/elmarco/src/qq/monitor.c:4257 #12 0x555ab6712c4d in json_message_process_token /home/elmarco/src/qq/qobject/json-streamer.c:105 #13 0x555ab67e01e2 in json_lexer_feed_char /home/elmarco/src/qq/qobject/json-lexer.c:323 #14 0x555ab67e0af6 in json_lexer_feed /home/elmarco/src/qq/qobject/json-lexer.c:373 #15 0x555ab6713010 in json_message_parser_feed /home/elmarco/src/qq/qobject/json-streamer.c:124 #16 0x555ab4fd58ec in monitor_qmp_read /home/elmarco/src/qq/monitor.c:4337 #17 0x555ab6559df2 in qemu_chr_be_write_impl /home/elmarco/src/qq/chardev/char.c:175 #18 0x555ab6559e95 in qemu_chr_be_write /home/elmarco/src/qq/chardev/char.c:187 #19 0x555ab6560127 in fd_chr_read /home/elmarco/src/qq/chardev/char-fd.c:66 #20 0x555ab65d9c73 in qio_channel_fd_source_dispatch /home/elmarco/src/qq/io/channel-watch.c:84 #21 0x7f8e26a598ac in g_main_context_dispatch (/lib64/libglib-2.0.so.0+0x4c8ac) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180809114417.28718-4-marcandre.lureau@redhat.com> [Screwed up in commit b27314567d4] Cc: qemu-stable@nongnu.org Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-08-15tests: fix crumple/recursive leakMarc-André Lureau1-0/+1
Spotted by ASAN: ================================================================= ==27907==ERROR: LeakSanitizer: detected memory leaks Direct leak of 4120 byte(s) in 1 object(s) allocated from: #0 0x7f913458ce50 in calloc (/lib64/libasan.so.5+0xeee50) #1 0x7f9133fd641d in g_malloc0 (/lib64/libglib-2.0.so.0+0x5241d) #2 0x5561c6643c95 in qdict_crumple_test_recursive /home/elmarco/src/qq/tests/check-block-qdict.c:438 #3 0x7f9133ff7c49 (/lib64/libglib-2.0.so.0+0x73c49) Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180809114417.28718-2-marcandre.lureau@redhat.com> [Screwed up in commit 2860b2b2cb8] Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-08-15qapi: Fix some pycodestyle-3 complaintsMarkus Armbruster3-13/+17
Fix the following issues: common.py:873:13: E129 visually indented line with same indent as next logical line common.py:1766:5: E741 ambiguous variable name 'l' common.py:1784:1: E305 expected 2 blank lines after class or function definition, found 1 common.py:1833:1: E305 expected 2 blank lines after class or function definition, found 1 common.py:1843:1: E305 expected 2 blank lines after class or function definition, found 1 visit.py:181:18: E127 continuation line over-indented for visual indent Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180621083551.775-1-armbru@redhat.com> [Fixup squashed in:] Message-ID: <871sd0nzw9.fsf@dusky.pond.sub.org> Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
2018-08-15tests: change /0.15/* tests to /qmp/*Marc-André Lureau1-5/+5
Presumably 0.15 was the version it was first introduced, but qmp keeps evolving. There is no point in having that version as test prefix, 'qmp' makes more sense here. Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20180326150916.9602-12-marcandre.lureau@redhat.com> Reviewed-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-08-15qmp-shell: learn to send commands with quoted argumentsMarc-André Lureau1-1/+2
Use shlex to split the CLI command, respecting quoted arguments, and also comments. This allows to call for ex: (QEMU) human-monitor-command command-line="screendump /dev/null" {"execute": "human-monitor-command", "arguments": {"command-line": "screendump /dev/null"}} Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Message-Id: <20180326150916.9602-3-marcandre.lureau@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2018-08-15aio-posix: Improve comment around marking node deletedFam Zheng1-1/+1
The counter is for qemu_lockcnt_inc/dec sections (read side), qemu_lockcnt_lock/unlock is for the write side. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180803063917.30292-1-famz@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Add vm-build-all/vm-clean-all in help textFam Zheng1-0/+3
Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180727083445.21436-1-famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Use make's --output-sync optionPeter Maydell4-8/+8
Use make's --output-sync option when running tests inside VMs, so that if we're building with parallelization the output doesn't get scrambled. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180803085230.30574-6-peter.maydell@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Bump guest RAM up from 2G to 4GPeter Maydell1-1/+1
Currently we run the guests in a VM which is given only 2G of RAM. Since the guests are configured without any swap space, builds can fail because the system runs out of memory and kills the compiler, especially if the job count is set for a lot of parallelism. Bump the setting up from 2G to 4G to give us some more headroom. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180803085230.30574-5-peter.maydell@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Propagate V=1 down into the make inside the VMPeter Maydell7-8/+13
Invoking 'make vm-build-freebsd' and friends with V=1 should propagate that verbosity setting down into the build run inside the VM. Make sure we do that. This brings it into line with how the container tests handle V=1. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180803085230.30574-4-peter.maydell@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Pass the jobs parallelism setting to 'make check'Peter Maydell4-4/+4
Our test suite works for parallel execution too, and this can noticeably speed up a test run; pass the 'jobs' setting to it as well as to the build proper. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20180803085230.30574-3-peter.maydell@linaro.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests: vm: Add vm-clean-allFam Zheng1-1/+4
The images are big. Add a rule to clean up easily. Suggested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180716020008.31468-1-famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests: Add centos VM testingFam Zheng2-1/+86
This one does docker testing in the VM. It is intended to replace the native docker testing on patchew testers. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180712012829.20231-5-famz@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests: Allow overriding archive path with SRC_ARCHIVEFam Zheng1-2/+5
In VM based tests, the source archive is created in host, we don't have to run archive-source.sh again, as it complicates the Makefile and scripts. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180712012829.20231-4-famz@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests: Add an option for snapshot (default: off)Fam Zheng1-1/+6
Not using snapshot has the benefit of automatically persisting useful test harnesses, such as docker images and ccache database. Although it will lose some cleanness, it is imaginably useful for patchew. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180712012829.20231-2-famz@redhat.com> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15docker: Install more packages in centos7Fam Zheng1-0/+3
This makes test-block work. Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180711065813.14894-1-famz@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15aio: Do aio_notify_accept only during blocking aio_pollFam Zheng2-3/+4
An aio_notify() pairs with an aio_notify_accept(). The former should happen in the main thread or a vCPU thread, and the latter should be done in the IOThread. There is one rare case that the main thread or vCPU thread may "steal" the aio_notify() event just raised by itself, in bdrv_set_aio_context() [1]. The sequence is like this: main thread IO Thread =============================================================== bdrv_drained_begin() aio_disable_external(ctx) aio_poll(ctx, true) ctx->notify_me += 2 ... bdrv_drained_end() ... aio_notify() ... bdrv_set_aio_context() aio_poll(ctx, false) [1] aio_notify_accept(ctx) ppoll() /* Hang! */ [1] is problematic. It will clear the ctx->notifier event so that the blocked ppoll() will not return. (For the curious, this bug was noticed when booting a number of VMs simultaneously in RHV. One or two of the VMs will hit this race condition, making the VIRTIO device unresponsive to I/O commands. When it hangs, Seabios is busy waiting for a read request to complete (read MBR), right after initializing the virtio-blk-pci device, using 100% guest CPU. See also https://bugzilla.redhat.com/show_bug.cgi?id=1562750 for the original bug analysis.) aio_notify() only injects an event when ctx->notify_me is set, correspondingly aio_notify_accept() is only useful when ctx->notify_me _was_ set. Move the call to it into the "blocking" branch. This will effectively skip [1] and fix the hang. Furthermore, blocking aio_poll is only allowed on home thread (in_aio_context_home_thread), because otherwise two blocking aio_poll()'s can steal each other's ctx->notifier event and cause hanging just like described above. Cc: qemu-stable@nongnu.org Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180809132259.18402-3-famz@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15aio-posix: Don't count ctx->notifier as progress when pollingFam Zheng1-1/+2
The same logic exists in fd polling. This change is especially important to avoid busy loop once we limit aio_notify_accept() to blocking aio_poll(). Cc: qemu-stable@nongnu.org Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180809132259.18402-2-famz@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15nvme: simplify plug/unplugPaolo Bonzini1-10/+10
bdrv_io_plug/bdrv_io_unplug take care of keeping a nesting count, so change s->plugged to just a bool. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <20180813144320.12382-2-pbonzini@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15nvme: Fix nvme_init error handlingFam Zheng1-25/+12
It is wrong to leave this field as 1, as nvme_close() called in the error handling code in nvme_file_open() will use it and try to free s->queues again. Another problem is the cleaning ups are duplicated between the fail* labels of nvme_init() and nvme_file_open(), which calls nvme_close(). A third problem is nvme_close() misses g_free() and event_notifier_cleanup(). Fix all of them. Cc: qemu-stable@nongnu.org Signed-off-by: Fam Zheng <famz@redhat.com> Message-Id: <20180712025420.4932-1-famz@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Add flex and bison to the vm imagePhilippe Mathieu-Daudé1-1/+1
Similar to 79f24568e5e70, this fixes the following warnings: CHK version_gen.h LEX convert-dtsv0-lexer.lex.c make[1]: flex: Command not found BISON dtc-parser.tab.c make[1]: bison: Command not found LEX dtc-lexer.lex.c make[1]: flex: Command not found Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180628153535.1411-5-f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-15tests/vm: Only use -cpu 'host' if KVM is availablePhilippe Mathieu-Daudé1-1/+2
If KVM is not available, then use the 'max' cpu. This fixes: ERROR:root:Log: ERROR:root:qemu-system-x86_64: CPU model 'host' requires KVM Failed to prepare guest environment error: [Errno 104] Connection reset by peer source/qemu/tests/vm/Makefile.include:25: recipe for target 'tests/vm/ubuntu.i386.img' failed make: *** [tests/vm/ubuntu.i386.img] Error 2 Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20180628153535.1411-4-f4bug@amsat.org> Signed-off-by: Fam Zheng <famz@redhat.com>
2018-08-14target/arm: Fix typo in helper_sve_movz_dRichard Henderson1-1/+1
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180801123111.3595-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14target/arm: Reorganize SVE WHILERichard Henderson2-22/+32
The pseudocode for this operation is an increment + compare loop, so comparing <= the maximum integer produces an all-true predicate. Rather than bound in both the inline code and the helper, pass the helper the number of predicate bits to set instead of the number of predicate elements to set. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180801123111.3595-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14target/arm: Fix typo in do_sat_addsub_64Richard Henderson1-1/+1
Used the wrong temporary in the computation of subtractive overflow. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180801123111.3595-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14target/arm: Fix sign of sve_cmpeq_ppzw/sve_cmpne_ppzwRichard Henderson1-6/+6
The normal vector element is sign-extended before comparing with the wide vector element. Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> Message-id: 20180801123111.3595-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14target/arm: Implement tailchaining for M profile coresPeter Maydell1-0/+16
Tailchaining is an optimization in handling of exception return for M-profile cores: if we are about to pop the exception stack for an exception return, but there is a pending exception which is higher priority than the priority we are returning to, then instead of unstacking and then immediately taking the exception and stacking registers again, we can chain to the pending exception without unstacking and stacking. For v6M and v7M it is IMPDEF whether tailchaining happens for pending exceptions; for v8M this is architecturally required. Implement it in QEMU for all M-profile cores, since in practice v6M and v7M hardware implementations generally do have it. (We were already doing tailchaining for derived exceptions which happened during exception return, like the validity checks and stack access failures; these have always been required to be tailchained for all versions of the architecture.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180720145647.8810-5-peter.maydell@linaro.org
2018-08-14target/arm: Restore M-profile CONTROL.SPSEL before any tailchainingPeter Maydell1-6/+10
On exception return for M-profile, we must restore the CONTROL.SPSEL bit from the EXCRET value before we do any kind of tailchaining, including for the derived exceptions on integrity check failures. Otherwise we will give the guest an incorrect EXCRET.SPSEL value on exception entry for the tailchained exception. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180720145647.8810-4-peter.maydell@linaro.org
2018-08-14target/arm: Initialize exc_secure correctly in do_v7m_exception_exit()Peter Maydell1-1/+1
In do_v7m_exception_exit(), we use the exc_secure variable to track whether the exception we're returning from is secure or non-secure. Unfortunately the statement initializing this was accidentally inside an "if (env->v7m.exception != ARMV7M_EXCP_NMI)" conditional, which meant that we were using the wrong value for NMI handlers. Move the initialization out to the right place. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180720145647.8810-3-peter.maydell@linaro.org
2018-08-14target/arm: Improve exception-taken loggingPeter Maydell1-6/+11
Improve the exception-taken logging by logging in v7m_exception_taken() the exception we're going to take and whether it is secure/nonsecure. This requires us to move logging at many callsites from after the call to before it, so that the logging appears in a sensible order. (This will make tail-chaining produce more useful logs; for the current callers of v7m_exception_taken() we know which exception we're going to take, so custom log messages at the callsite sufficed; for tail-chaining only v7m_exception_taken() knows the exception number that we're going to tail-chain to.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20180720145647.8810-2-peter.maydell@linaro.org
2018-08-14target/arm: Treat SCTLR_EL1.M as if it were zero when HCR_EL2.TGE is setPeter Maydell1-0/+8
One of the required effects of setting HCR_EL2.TGE is that when SCR_EL3.NS is 1 then SCTLR_EL1.M must behave as if it is zero for all purposes except direct reads. That is, it effectively disables the MMU for the NS EL0/EL1 translation regime. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-6-peter.maydell@linaro.org
2018-08-14target/arm: Provide accessor functions for HCR_EL2.{IMO, FMO, AMO}Peter Maydell3-18/+71
The IMO, FMO and AMO bits in HCR_EL2 are defined to "behave as 1 for all purposes other than direct reads" if HCR_EL2.TGE is set and HCR_EL2.E2H is 0, and to "behave as 0 for all purposes other than direct reads" if HCR_EL2.TGE is set and HRC_EL2.E2H is 1. To avoid having to check E2H and TGE everywhere where we test IMO and FMO, provide accessors arm_hcr_el2_imo(), arm_hcr_el2_fmo()and arm_hcr_el2_amo(). We don't implement ARMv8.1-VHE yet, so the E2H case will never be true, but we include the logic to save effort when we eventually do get to that. (Note that in several of these callsites the change doesn't actually make a difference as either the callsite is handling TGE specially anyway, or the CPU can't get into that situation with TGE set; we change everywhere for consistency.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-5-peter.maydell@linaro.org
2018-08-14target/arm: Honour HCR_EL2.TGE when raising synchronous exceptionsPeter Maydell1-0/+14
Whene we raise a synchronous exception, if HCR_EL2.TGE is set then exceptions targeting NS EL1 must be redirected to EL2. Implement this in raise_exception() -- all synchronous exceptions go through this function. (Asynchronous exceptions go via arm_cpu_exec_interrupt(), which already honours HCR_EL2.TGE when it determines the target EL in arm_phys_excp_target_el().) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-4-peter.maydell@linaro.org
2018-08-14target/arm: Honour HCR_EL2.TGE and MDCR_EL2.TDE in debug register access checksPeter Maydell1-6/+12
Some debug registers can be trapped via MDCR_EL2 bits TDRA, TDOSA, and TDA, which we implement in the functions access_tdra(), access_tdosa() and access_tda(). If MDCR_EL2.TDE or HCR_EL2.TGE are 1, the TDRA, TDOSA and TDA bits should behave as if they were 1. Implement this by having the access functions check MDCR_EL2.TDE and HCR_EL2.TGE. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-3-peter.maydell@linaro.org
2018-08-14target/arm: Mask virtual interrupts if HCR_EL2.TGE is setPeter Maydell1-2/+4
If the "trap general exceptions" bit HCR_EL2.TGE is set, we must mask all virtual interrupts (as per DDI0487C.a D1.14.3). Implement this in arm_excp_unmasked(). Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180724115950.17316-2-peter.maydell@linaro.org
2018-08-14arm: Fix return code of arm_load_elfAdam Lackorzynski1-4/+4
Use an int64_t as a return type to restore the negative check for arm_load_as. Signed-off-by: Adam Lackorzynski <adam@l4re.org> Message-id: 20180730173712.GG4987@os.inf.tu-dresden.de Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14arm/virt: Add support for GICv2 virtualization extensionsLuc Michel3-12/+50
Add support for GICv2 virtualization extensions by mapping the necessary I/O regions and connecting the maintenance IRQ lines. Declare those additions in the device tree and in the ACPI tables. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-21-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14xlnx-zynqmp: Improve GIC wiring and MMIO mappingLuc Michel2-10/+86
This commit improve the way the GIC is realized and connected in the ZynqMP SoC. The security extensions are enabled only if requested in the machine state. The same goes for the virtualization extensions. All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ, vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also added (HYP and SEC timers). The GIC maintenance IRQs are back-wired to the correct GIC PPIs. Finally, the MMIO mappings are reworked to take into account the ZynqMP specifics. The GIC (v)CPU interface is aliased 16 times: * for the first 0x1000 bytes from 0xf9010000 to 0xf901f000 * for the second 0x1000 bytes from 0xf9020000 to 0xf902f000 Mappings of the virtual interface and virtual CPU interface are mapped only when virtualization extensions are requested. The XlnxZynqMPGICRegion struct has been enhanced to be able to catch all this information. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20180727095421.386-20-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Improve tracesLuc Michel2-8/+35
Add some traces to the ARM GIC to catch register accesses (distributor, (v)cpu interface and virtual interface), and to take into account virtualization extensions (print `vcpu` instead of `cpu` when needed). Also add some virtualization extensions specific traces: LR updating and maintenance IRQ generation. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-19-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement maintenance interrupt generationLuc Michel1-0/+97
Implement the maintenance interrupt generation that is part of the GICv2 virtualization extensions. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-18-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement gic_update_virt() functionLuc Michel1-39/+136
Add the gic_update_virt() function to update the vCPU interface states and raise vIRQ and vFIQ as needed. This commit renames gic_update() to gic_update_internal() and generalizes it to handle both cases, with a `virt' parameter to track whether we are updating the CPU or vCPU interfaces. The main difference between CPU and vCPU is the way we select the best IRQ. This part has been split into the gic_get_best_(v)irq functions. For the virt case, the LRs are iterated to find the best candidate. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-17-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement the virtual interface registersLuc Michel1-2/+233
Implement the read and write functions for the virtual interface of the virtualization extensions in the GICv2. One mirror region per CPU is also created, which maps to that specific CPU id. This is required by the GIC architecture specification. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-16-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Wire the vCPU interfaceLuc Michel1-2/+35
Add the read/write functions to handle accesses to the vCPU interface. Those accesses are forwarded to the real CPU interface, with the CPU id being converted to the corresponding vCPU id (vCPU id = CPU id + GIC_NCPU). Signed-off-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180727095421.386-15-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write)Luc Michel1-5/+15
Implement virtualization extensions in the gic_cpu_read() and gic_cpu_write() functions. Those are the last bits missing to fully support virtualization extensions in the CPU interface path. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-14-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement virtualization extensions in ↵Luc Michel1-4/+47
gic_(deactivate|complete_irq) Implement virtualization extensions in the gic_deactivate_irq() and gic_complete_irq() functions. When the guest writes an invalid vIRQ to V_EOIR or V_DIR, since the GICv2 specification is not entirely clear here, we adopt the behaviour observed on real hardware: * When V_CTRL.EOIMode is false (EOI split is disabled): - In case of an invalid vIRQ write to V_EOIR: -> If some bits are set in H_APR, an invalid vIRQ write to V_EOIR triggers a priority drop, and increments V_HCR.EOICount. -> If V_APR is already cleared, nothing happen - An invalid vIRQ write to V_DIR is ignored. * When V_CTRL.EOIMode is true: - In case of an invalid vIRQ write to V_EOIR: -> If some bits are set in H_APR, an invalid vIRQ write to V_EOIR triggers a priority drop. -> If V_APR is already cleared, nothing happen - An invalid vIRQ write to V_DIR increments V_HCR.EOICount. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180727095421.386-13-luc.michel@greensocs.com Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irqLuc Michel1-19/+33
Implement virtualization extensions in the gic_acknowledge_irq() function. This function changes the state of the highest priority IRQ from pending to active. When the current CPU is a vCPU, modifying the state of an IRQ modifies the corresponding LR entry. However if we clear the pending flag before setting the active one, we lose track of the LR entry as it becomes invalid. The next call to gic_get_lr_entry() will fail. To overcome this issue, we call gic_activate_irq() before gic_clear_pending(). This does not change the general behaviour of gic_acknowledge_irq. We also move the SGI case in gic_clear_pending_sgi() to enhance code readability as the virtualization extensions support adds a if-else level. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-12-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2018-08-14intc/arm_gic: Implement virtualization extensions in ↵Luc Michel1-12/+38
gic_(activate_irq|drop_prio) Implement virtualization extensions in gic_activate_irq() and gic_drop_prio() and in gic_get_prio_from_apr_bits() called by gic_drop_prio(). When the current CPU is a vCPU: - Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt counterparts, - the vCPU APR is stored in the virtual interface, in h_apr. Signed-off-by: Luc Michel <luc.michel@greensocs.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20180727095421.386-11-luc.michel@greensocs.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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