riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-06-23	block/nvme: keep BDRVNVMeState pointer in NVMeQueuePair	Stefan Hajnoczi	1	-32/+38
2020-06-23	block/nvme: clarify that free_req_queue is protected by q->lock	Stefan Hajnoczi	1	-1/+1
2020-06-23	block/nvme: switch to a NVMeRequest freelist	Stefan Hajnoczi	1	-27/+54
2020-06-23	block/nvme: don't access CQE after moving cq.head	Stefan Hajnoczi	1	-1/+4
2020-06-23	block/nvme: drop tautologous assertion	Stefan Hajnoczi	1	-1/+0
2020-06-23	block/nvme: poll queues without q->lock	Stefan Hajnoczi	1	-0/+12
2020-06-23	check-block: enable iotests with SafeStack	Daniele Buono	1	-1/+11
2020-06-23	configure: add flags to support SafeStack	Daniele Buono	1	-0/+73
2020-06-23	coroutine: add check for SafeStack in sigaltstack	Daniele Buono	1	-0/+4
2020-06-23	coroutine: support SafeStack in ucontext backend	Daniele Buono	2	-0/+33
2020-06-23	minikconf: explicitly set encoding to UTF-8	Stefan Hajnoczi	1	-3/+3
2020-06-22	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...	Peter Maydell	26	-182/+1350
2020-06-19	Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request...	Peter Maydell	3	-37/+40
2020-06-19	qht: Fix threshold rate calculation	Richard Henderson	1	-1/+2
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng	2	-0/+5
2020-06-19	hw/riscv: sifive_u: Sort the SoC memmap table entries	Bin Meng	1	-2/+2
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng	2	-8/+37
2020-06-19	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	Bin Meng	3	-15/+17
2020-06-19	target/riscv: Rename IBEX CPU init routine	Bin Meng	1	-2/+2
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng	2	-0/+8
2020-06-19	hw/riscv: sifive_u: Rename serial property get/set functions to a generic name	Bin Meng	1	-6/+8
2020-06-19	hw/riscv: sifive_u: Add reset functionality	Bin Meng	1	-1/+23
2020-06-19	hw/riscv: sifive_gpio: Do not blindly trigger output IRQs	Bin Meng	1	-1/+3
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng	2	-2/+60
2020-06-19	hw/riscv: sifive_gpio: Add a new 'ngpio' property	Bin Meng	2	-11/+22
2020-06-19	hw/riscv: sifive_gpio: Clean up the codes	Bin Meng	2	-11/+9
2020-06-19	hw/riscv: sifive_u: Generate device tree node for OTP	Bin Meng	1	-0/+11
2020-06-19	hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit	Bin Meng	1	-6/+1
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-15/+14
2020-06-19	hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-12/+12
2020-06-19	target/riscv: Use a smaller guess size for no-MMU PMP	Alistair Francis	1	-5/+9
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis	2	-2/+36
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis	2	-2/+15
2020-06-19	hw/intc: Initial commit of lowRISC Ibex PLIC	Alistair Francis	4	-0/+327
2020-06-19	hw/char: Initial commit of Ibex UART	Alistair Francis	5	-0/+609
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis	1	-1/+2
2020-06-19	target/riscv: Implement checks for hfence	Alistair Francis	3	-26/+24
2020-06-19	target/riscv: Move the hfence instructions to the rvh decode	Alistair Francis	4	-41/+63
2020-06-19	target/riscv: Report errors validating 2nd-stage PTEs	Alistair Francis	1	-2/+7
2020-06-19	target/riscv: Set access as data_load when validating stage-2 PTEs	Alistair Francis	1	-1/+1
2020-06-19	riscv: Keep the CPU init routine names consistent	Bin Meng	1	-4/+4
2020-06-19	riscv: Generalize CPU init routine for the imacu CPU	Bin Meng	1	-21/+10
2020-06-19	riscv: Generalize CPU init routine for the gcsu CPU	Bin Meng	1	-14/+6
2020-06-19	riscv: Generalize CPU init routine for the base CPU	Bin Meng	1	-13/+5
2020-06-19	sifive_e: Support the revB machine	Alistair Francis	2	-4/+31
2020-06-19	riscv: Add helper to make NaN-boxing for FP register	Ian Jiang	1	-2/+15
2020-06-19	Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20200618' into staging	Peter Maydell	32	-78/+1075
2020-06-19	hw/audio/gus: Fix registers 32-bit access	Allan Peramaki	2	-2/+2
2020-06-18	Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into st...	Peter Maydell	19	-449/+905
2020-06-18	Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20200617a'...	Peter Maydell	7	-51/+56