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2021-10-27qapi: Add feature flags to enum membersMarkus Armbruster13-14/+57
This is quite similar to commit 84ab008687 "qapi: Add feature flags to struct members", only for enums instead of structs. Special feature flag 'deprecated' is silently ignored there. This is okay only because it will be implemented shortly. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20211025042405.3762351-3-armbru@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>
2021-10-27qapi: Enable enum member introspection to show more than nameMarkus Armbruster4-10/+54
The next commit will add feature flags to enum members. There's a problem, though: query-qmp-schema shows an enum type's members as an array of member names (SchemaInfoEnum member @values). If it showed an array of objects with a name member, we could simply add more members to these objects. Since it's just strings, we can't. I can see three ways to correct this design mistake: 1. Do it the way we should have done it, plus compatibility goo. We want a ['SchemaInfoEnumMember'] member in SchemaInfoEnum. Since changing @values would be a compatibility break, add a new member @members instead. @values is now redundant. In my testing, output of qemu-system-x86_64's query-qmp-schema grows by 11% (18.5KiB). We can deprecate @values now and drop it later. This will break outmoded clients. Well-behaved clients such as libvirt are expected to break cleanly. 2. Like 1, but omit "boring" elements of @member, and empty @member. @values does not become redundant. @members augments it. Somewhat cumbersome, but output of query-qmp-schema grows only as we make enum members non-boring. There is nothing to deprecate here. 3. Versioned query-qmp-schema. query-qmp-schema provides either @values or @members. The QMP client can select which version it wants. There is no redundant output. We can deprecate old versions and eventually drop them. This will break outmoded clients. Breaking cleanly is easier than for 1. While 1 and 2 operate within the common rules for compatible evolution apply (section "Compatibility considerations" in docs/devel/qapi-code-gen.rst), 3 bypasses them. Attractive when operating within the rules is just too awkward. Not the case here. This commit implements 1. Libvirt developers prefer it. Deprecate @values in favour of @members. Since query-qmp-schema compatibility is pretty fundamental for management applications, an extended grace period is advised. Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Tested-by: Peter Krempa <pkrempa@redhat.com> Acked-by: Peter Krempa <pkrempa@redhat.com> Message-Id: <20211025042405.3762351-2-armbru@redhat.com> Reviewed-by: John Snow <jsnow@redhat.com>
2021-10-27qapi: Improve input_type_enum()'s error messageMarkus Armbruster8-12/+13
The error message claims the parameter is invalid: $ qemu-system-x86_64 -object qom-type=nonexistent qemu-system-x86_64: -object qom-type=nonexistent: Invalid parameter 'nonexistent' What's wrong is actually the *value* 'nonexistent'. Improve the message to qemu-system-x86_64: -object qom-type=nonexistent: Parameter 'qom-type' does not accept value 'nonexistent' Fixes: https://gitlab.com/qemu-project/qemu/-/issues/608 Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211020180231.434071-1-armbru@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com>
2021-10-26Merge remote-tracking branch 'remotes/dagrh/tags/pull-virtiofs-20211026' ↵Richard Henderson3-45/+58
into staging Virtiofsd pull 2021-10-26 New 'unsupported' feature for xattr mapping Good for hiding selinux Plus some tidy ups and error handling. Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> # gpg: Signature made Tue 26 Oct 2021 03:28:44 AM PDT # gpg: using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7 # gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full] * remotes/dagrh/tags/pull-virtiofs-20211026: virtiofsd: Error on bad socket group name virtiofsd: Add a helper to stop all queues virtiofsd: Add a helper to send element on virtqueue virtiofsd: Remove unused virtio_fs_config definition virtiofsd: xattr mapping add a new type "unsupported" Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-25virtiofsd: Error on bad socket group nameDr. David Alan Gilbert1-0/+7
Make the '--socket-group=' option fail if the group name is unknown: ./tools/virtiofsd/virtiofsd .... --socket-group=zaphod vhost socket: unable to find group 'zaphod' Reported-by: Xiaoling Gao <xiagao@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Message-Id: <20211014122554.34599-1-dgilbert@redhat.com> Reviewed-by: Vivek Goyal <vgoyal@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-10-25virtiofsd: Add a helper to stop all queuesVivek Goyal1-9/+13
Use a helper to stop all the queues. Later in the patch series I am planning to use this helper at one more place later in the patch series. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20210930153037.1194279-6-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-10-25virtiofsd: Add a helper to send element on virtqueueVivek Goyal1-27/+18
We have open coded logic to take locks and push element on virtqueue at three places. Add a helper and use it everywhere. Code is easier to read and less number of lines of code. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20210930153037.1194279-5-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-10-25virtiofsd: Remove unused virtio_fs_config definitionVivek Goyal1-6/+0
"struct virtio_fs_config" definition seems to be unused in fuse_virtio.c. Remove it. Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <20210930153037.1194279-4-vgoyal@redhat.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-10-25virtiofsd: xattr mapping add a new type "unsupported"Vivek Goyal2-3/+20
Right now for xattr remapping, we support types of "prefix", "ok" or "bad". Type "bad" returns -EPERM on setxattr and hides xattr in listxattr. For getxattr, mapping code returns -EPERM but getxattr code converts it to -ENODATA. I need a new semantics where if an xattr is unsupported, then getxattr()/setxattr() return -ENOTSUP and listxattr() should hide the xattr. This is needed to simulate that security.selinux is not supported by virtiofs filesystem and in that case client falls back to some default label specified by policy. So add a new type "unsupported" which returns -ENOTSUP on getxattr() and setxattr() and hides xattrs in listxattr(). For example, one can use following mapping rule to not support security.selinux xattr and allow others. "-o xattrmap=/unsupported/all/security.selinux/security.selinux//ok/all///" Suggested-by: "Dr. David Alan Gilbert" <dgilbert@redhat.com> Signed-off-by: Vivek Goyal <vgoyal@redhat.com> Message-Id: <YUt9qbmgAfCFfg5t@redhat.com> Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2021-10-23Merge remote-tracking branch ↵Richard Henderson11-90/+87
'remotes/vivier/tags/trivial-branch-for-6.2-pull-request' into staging Trivial patches pull request 20211023 # gpg: Signature made Sat 23 Oct 2021 11:30:42 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier/tags/trivial-branch-for-6.2-pull-request: analyze-migration.py: fix extract contents ('-x') errors analyze-migration.py: fix a long standing typo README: Fix some documentation URLs hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse device hw/nvram: Fix Memory Leak in Xilinx Versal eFuse device hw/nvram: Fix Memory Leak in Xilinx eFuse QOM softmmu/physmem.c: Fix typo in comment MAINTAINERS: Add myself as reviewer of 'Machine core' API disas/nios2: Simplify endianess conversion disas/nios2: Fix style in print_insn_nios2() po: update turkish translation Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-23analyze-migration.py: fix extract contents ('-x') errorsLaurent Vivier1-2/+2
When we try to use 'analyze-migration.py -x' with python3, we have the following errors: Traceback (most recent call last): File "scripts/analyze-migration.py", line 593, in <module> f.write(jsonenc.encode(dump.vmsd_desc)) TypeError: a bytes-like object is required, not 'str' Traceback (most recent call last): File "scripts/analyze-migration.py", line 601, in <module> f.write(jsonenc.encode(dict)) TypeError: a bytes-like object is required, not 'str' This happens because the file 'f' is open in binary mode while jsonenc.encode() returns a string. The results are human-readable files, 'desc.json' and 'state.json', so there is no reason to use the binary mode. Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211015131645.501281-3-lvivier@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23analyze-migration.py: fix a long standing typoLaurent Vivier1-1/+1
The parameters of '-d' can be either 'state' or 'desc', not 'dump' as it is reported in the error message. Fixes: b17425701d66 ("Add migration stream analyzation script") Signed-off-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211015131645.501281-2-lvivier@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23README: Fix some documentation URLsGreg Kurz1-7/+7
All of these pages live in the wiki, not in the main web site. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Tested-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <163456470882.196333.17366490695504718038.stgit@bahia.huguette> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23hw/nvram: Fix Memory Leak in Xilinx ZynqMP eFuse deviceTong Ho1-6/+12
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015203532.2463705-4-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23hw/nvram: Fix Memory Leak in Xilinx Versal eFuse deviceTong Ho1-5/+15
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015203532.2463705-3-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23hw/nvram: Fix Memory Leak in Xilinx eFuse QOMTong Ho1-3/+6
Signed-off-by: Tong Ho <tong.ho@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20211015203532.2463705-2-tong.ho@xilinx.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23softmmu/physmem.c: Fix typo in commentGreg Kurz1-1/+1
Fix the comment to match what the code is doing, as explained in the changelog of commit 86cf9e154632cb28d749db0ea47946fba8cf3f09 that introduced the change: Commit 9458a9a1df1a4c719e24512394d548c1fc7abd22 added synchronization of vCPU and migration operations through calling run_on_cpu operation. However, in replay mode this synchronization is unneeded, because I/O and vCPU threads are already synchronized. This patch disables such synchronization for record/replay mode. Signed-off-by: Greg Kurz <groug@kaod.org> Reviewed-by: David Hildenbrand <david@redhat.com> Message-Id: <163429018454.1146856.3429437540871060739.stgit@bahia.huguette> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-23MAINTAINERS: Add myself as reviewer of 'Machine core' APIPhilippe Mathieu-Daudé1-0/+1
In order to help Eduardo and Marcel with the machine core API, add myself as reviewer. That will also help me to learn more about this subsystem :) Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed by: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> Message-Id: <20211007093108.323223-1-philmd@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-22Merge remote-tracking branch ↵Richard Henderson28-779/+720
'remotes/alistair23/tags/pull-riscv-to-apply-20211022-2' into staging Fourth RISC-V PR for QEMU 6.2 - Vector extension bug fixes - Bit manipulation extension bug fix - Support vhost-user and numa mem options on all boards - Rationalise XLEN and operand lengths - Bump the OpenTitan FPGA support - Remove the Ibex PLIC - General code cleanup # gpg: Signature made Fri 22 Oct 2021 06:36:10 AM PDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full] * remotes/alistair23/tags/pull-riscv-to-apply-20211022-2: (33 commits) hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_id hw/riscv: microchip_pfsoc: Use MachineState::ram and MachineClass::default_ram_id hw/intc: sifive_plic: Cleanup the irq_request function hw/intc: sifive_plic: Cleanup the realize function hw/intc: sifive_plic: Move the properties hw/intc: Remove the Ibex PLIC hw/riscv: opentitan: Update to the latest build target/riscv: Compute mstatus.sd on demand target/riscv: Use riscv_csrrw_debug for cpu_dump target/riscv: Use gen_shift*_per_ol for RVB, RVI target/riscv: Use gen_unary_per_ol for RVB target/riscv: Adjust trans_rev8_32 for riscv64 target/riscv: Use gen_arith_per_ol for RVM target/riscv: Replace DisasContext.w with DisasContext.ol target/riscv: Replace is_32bit with get_xl/get_xlen target/riscv: Properly check SEW in amo_op ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-22Merge remote-tracking branch ↵Richard Henderson13-0/+0
'remotes/kraxel/tags/seabios-20211022-pull-request' into staging seabios: update to master branch snapshot. # gpg: Signature made Fri 22 Oct 2021 05:14:00 AM PDT # gpg: using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138 # gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full] # gpg: aka "Gerd Hoffmann <gerd@kraxel.org>" [full] # gpg: aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full] * remotes/kraxel/tags/seabios-20211022-pull-request: update seabios binaries update seabios to master branch snapshot Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-22disas/nios2: Simplify endianess conversionPhilippe Mathieu-Daudé3-26/+5
Since commit 12b6e9b27d4 ("disas: Clean up CPUDebug initialization") the disassemble_info->bfd_endian enum is set for all targets in target_disas(). We can directly call print_insn_nios2() and simplify. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-3-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-22disas/nios2: Fix style in print_insn_nios2()Philippe Mathieu-Daudé1-28/+27
We are going to modify this function, fix its style first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210807110939.95853-2-f4bug@amsat.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-22po: update turkish translationOğuz Ersen1-13/+12
Message-Id: <lDpmNUjNrVETJ2QoHoYmSoRvKoEIVFbF4IZAa1R5PVzqPCTh7nmV_ERHQlgYtNJN1Ppagtvelbo4uhSihEd5bSqIxCvGQchEWVpP-ofn2kw=@protonmail.com> Signed-off-by: Oğuz Ersen <oguzersen@protonmail.com> Reviewed-by: Laurent Vivier <laurent@vivier.eu> [lv,pb: s/K_opyala/_Kopyala/;s/Se_kmeleri/_Sekmeleri/] Signed-off-by: Laurent Vivier <laurent@vivier.eu>
2021-10-22Merge remote-tracking branch 'remotes/clg/tags/pull-aspeed-20211022' into ↵Richard Henderson5-5/+91
staging Aspeed patches : * New fp5280g2-bmc board (John) * Small cleanup in Aspeed SMC model (Cedric) # gpg: Signature made Fri 22 Oct 2021 12:55:18 AM PDT # gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1 # gpg: Good signature from "Cédric Le Goater <clg@kaod.org>" [marginal] # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1 * remotes/clg/tags/pull-aspeed-20211022: speed/sdhci: Add trace events aspeed/smc: Use a container for the flash mmio address space aspeed: Add support for the fp5280g2-bmc board Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-22Merge remote-tracking branch 'remotes/vivier-m68k/tags/q800-pull-request' ↵Richard Henderson4-5/+189
into staging Pull request Q800 20211022 GLUE updates for A/UX mode # gpg: Signature made Fri 22 Oct 2021 12:16:29 AM PDT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] * remotes/vivier-m68k/tags/q800-pull-request: q800: drop 8-bit graphic_depth check for Apple 21 inch display q800: add NMI handler q800: wire up remaining IRQs in classic mode q800: route SONIC on-board Ethernet IRQ via nubus IRQ 9 in classic mode q800: wire up auxmode GPIO to GLUE mac_via: add GPIO for A/UX mode q800: use GLUE IRQ numbers instead of IRQ level for GLUE IRQs q800: move VIA1 IRQ from level 1 to level 6 mac_via: update comment for VIA1B_vMystery bit Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-10-22hw/riscv: spike: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-7-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/riscv: sifive_u: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-6-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/riscv: sifive_e: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-5-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/riscv: shakti_c: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+2
Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211020014112.7336-4-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/riscv: opentitan: Use MachineState::ram and MachineClass::default_ram_idBin Meng1-4/+12
Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. While at it add check for user supplied RAM size and error out if it mismatches board expected value. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-3-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/riscv: microchip_pfsoc: Use MachineState::ram and ↵Bin Meng1-16/+20
MachineClass::default_ram_id Using memory_region_init_ram(), which can't possibly handle vhost-user, and can't work as expected with '-numa node,memdev' options. Use MachineState::ram instead of manually initializing RAM memory region, as well as by providing MachineClass::default_ram_id to opt in to memdev scheme. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Message-id: 20211020014112.7336-2-bmeng.cn@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22hw/intc: sifive_plic: Cleanup the irq_request functionAlistair Francis1-6/+4
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 4200da222a65c89ed1ba35f754dcca7fdd9f08d6.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/intc: sifive_plic: Cleanup the realize functionAlistair Francis1-21/+24
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: b94c098cb221e744683349b1ac794c23102ef471.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/intc: sifive_plic: Move the propertiesAlistair Francis1-15/+15
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 3c125e27c49a4969df82bf8b197535ccd1996939.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/intc: Remove the Ibex PLICAlistair Francis2-308/+0
The Ibex PLIC is now spec compliant. Let's remove the Ibex PLIC and instead use the SiFive PLIC. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 5557935c2660c5e6281b6d21e6514e019593662e.1634524691.git.alistair.francis@wdc.com
2021-10-22hw/riscv: opentitan: Update to the latest buildAlistair Francis2-8/+20
Update the OpenTitan machine model to match the latest OpenTitan FPGA design. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Message-id: 18b1b681b0f8dd2461e819d1217bf0b530812680.1634524691.git.alistair.francis@wdc.com
2021-10-22target/riscv: Compute mstatus.sd on demandRichard Henderson3-20/+25
The position of this read-only field is dependent on the current xlen. Rather than having to compute that difference in many places, compute it only on read. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-16-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Use riscv_csrrw_debug for cpu_dumpRichard Henderson1-44/+45
Use the official debug read interface to the csrs, rather than referencing the env slots directly. Put the list of csrs to dump into a table. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-15-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Use gen_shift*_per_ol for RVB, RVIRichard Henderson3-52/+97
Most shift instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-14-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Use gen_unary_per_ol for RVBRichard Henderson2-17/+32
The count zeros instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-13-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Adjust trans_rev8_32 for riscv64Richard Henderson1-1/+6
When target_long is 64-bit, we still want a 32-bit bswap for rev8. Since this opcode is specific to RV32, we need not conditionalize. Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-12-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Use gen_arith_per_ol for RVMRichard Henderson2-3/+39
The multiply high-part instructions require a separate implementation for RV32 when TARGET_LONG_BITS == 64. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-11-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22update seabios binariesGerd Hoffmann12-0/+0
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-10-22update seabios to master branch snapshotGerd Hoffmann1-0/+0
A new seabios release is planned for november. Update to a master branch snapshot, to (a) increase test coverage of the changes. (b) make the delta smaller when updating to the final release during the qemu 6.2 freeze. Most noteworthy this fixes the nvme boot regression caused by adding namespace support to the qemu nvme emulation. seabios shortlog ================ Alex Martens via SeaBIOS (1): nvme: fix missing newline on sq full print Alexander Graf (4): nvme: Record maximum allowed request size nvme: Allow to set PRP2 nvme: Pass large I/O requests as PRP lists nvme: Split requests by maximum allowed size Daniel P. Berrangé (1): smbios: avoid integer overflow when adding SMBIOS type 0 table David Woodhouse (1): nvme: Clean up nvme_cmd_readwrite() Gerd Hoffmann (9): output: add support for uppercase hex numbers dsdt: add support for pnp ids as strings usb: add boot prio support for mmio host adapters usb/xhci: split xhci setup into generic and pci parts usb/xhci: add support for mmio host adapters (via acpi). usb boot: add xhci mmio example nvme: improve namespace allocation nvme: drive desc should not include the newline Increase BUILD_MIN_BIOSTABLE for large roms Matt DeVillier (1): usb.c: Fix devices using non-primary interface descriptor Mike Banon (1): Support booting USB drives with a write protect switch enabled Sergei Trofimovich (1): vgasrc: ignore .node.gnu.property (binutils-2.36 support) Stefan Berger (4): tcgbios: Fix details in log entries Add implementations for sha256, sha384, and sha512 tcgbios: Use The proper sha function for each PCR bank tcgbios: Disable platform hierarchy in case of failure Stefan Ott via SeaBIOS (1): usb-hid: Increase MAX_KBD_EVENT Volker Rümelin (2): stacks: call check_irqs() in run_thread() stacks: call check_irqs() after switch_next() weitaowang-oc@zhaoxin.com (1): USB:Fix xHCI initail fail by using longer reset and CNR clear timeout value Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2021-10-22speed/sdhci: Add trace eventsCédric Le Goater2-0/+9
Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20211018132609.160008-6-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22aspeed/smc: Use a container for the flash mmio address spaceCédric Le Goater2-5/+8
Because AddressSpaces must not be sysbus-mapped, commit e9c568dbc225 ("hw/arm/aspeed: Do not sysbus-map mmio flash region directly, use alias") introduced an alias for the flash mmio region. Using a container is cleaner. Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> Message-Id: <20211018132609.160008-5-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22aspeed: Add support for the fp5280g2-bmc boardJohn Wang1-0/+74
The fp5280g2-bmc is supported by OpenBMC, It's based on the following device tree https://github.com/openbmc/linux/blob/dev-5.10/arch/arm/boot/dts/aspeed-bmc-inspur-fp5280g2.dts Signed-off-by: John Wang <wangzhiqiang02@inspur.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20211014064548.934799-1-wangzhiqiang02@inspur.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
2021-10-22target/riscv: Replace DisasContext.w with DisasContext.olRichard Henderson4-43/+62
In preparation for RV128, consider more than just "w" for operand size modification. This will be used for the "d" insns from RV128 as well. Rename oper_len to get_olen to better match get_xlen. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-10-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Replace is_32bit with get_xl/get_xlenRichard Henderson1-14/+17
In preparation for RV128, replace a simple predicate with a more versatile test. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-9-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2021-10-22target/riscv: Properly check SEW in amo_opRichard Henderson1-12/+14
We're currently assuming SEW <= 3, and the "else" from the SEW == 3 must be less. Use a switch and explicitly bound both SEW and SEQ for all cases. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-8-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2024-12-29 18:19:45 +0000