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2022-02-08hw/arm: imx: Don't enable PSCI conduit when booting guest in EL3Peter Maydell4-6/+6
Change the iMX-SoC based boards to use the new boot.c functionality to allow us to enable psci-conduit only if the guest is being booted in EL1 or EL2, so that if the user runs guest EL3 firmware code our PSCI emulation doesn't get in its way. To do this we stop setting the psci-conduit property on the CPU objects in the SoC code, and instead set the psci_conduit field in the arm_boot_info struct to tell the common boot loader code that we'd like PSCI if the guest is starting at an EL that it makes sense with. This affects the mcimx6ul-evk and mcimx7d-sabre boards. Note that for the mcimx7d board, this means that when running guest code at EL3 there is currently no way to power on the secondary CPUs, because we do not currently have a model of the system reset controller module which should be used to do that for the imx7 SoC, only for the imx6 SoC. (Previously EL3 code which knew it was running on QEMU could use a PSCI call to do this.) This doesn't affect the imx6ul-evk board because it is uniprocessor. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Cédric Le Goater <clg@kaod.org> Acked-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220127154639.2090164-5-peter.maydell@linaro.org
2022-02-08hw/arm/boot: Support setting psci-conduit based on guest ELPeter Maydell2-0/+60
Currently we expect board code to set the psci-conduit property on CPUs and ensure that secondary CPUs are created with the start-powered-off property set to false, if the board wishes to use QEMU's builtin PSCI emulation. This worked OK for the virt board where we first wanted to use it, because the virt board directly creates its CPUs and is in a reasonable position to set those properties. For other boards which model real hardware and use a separate SoC object, however, it is more awkward. Most PSCI-using boards just set the psci-conduit board unconditionally. This was never strictly speaking correct (because you would not be able to run EL3 guest firmware that itself provided the PSCI interface, as the QEMU implementation would overrule it), but mostly worked in practice because for non-PSCI SMC calls QEMU would emulate the SMC instruction as normal (by trapping to guest EL3). However, we would like to make our PSCI emulation follow the part of the SMCC specification that mandates that SMC calls with unknown function identifiers return a failure code, which means that all SMC calls will be handled by the PSCI code and the "emulate as normal" path will no longer be taken. We tried to implement that in commit 9fcd15b9193e81 ("arm: tcg: Adhere to SMCCC 1.3 section 5.2"), but this regressed attempts to run EL3 guest code on the affected boards: * mcimx6ul-evk, mcimx7d-sabre, orangepi, xlnx-zcu102 * for the case only of EL3 code loaded via -kernel (and not via -bios or -pflash), virt and xlnx-versal-virt so for the 7.0 release we reverted it (in commit 4825eaae4fdd56f). This commit provides a mechanism that boards can use to arrange that psci-conduit is set if running guest code at a low enough EL but not if it would be running at the same EL that the conduit implies that the QEMU PSCI implementation is using. (Later commits will convert individual board models to use this mechanism.) We do this by moving the setting of the psci-conduit and start-powered-off properties to arm_load_kernel(). Boards which want to potentially use emulated PSCI must set a psci_conduit field in the arm_boot_info struct to the type of conduit they want to use (SMC or HVC); arm_load_kernel() will then set the CPUs up accordingly if it is not going to start the guest code at the same or higher EL as the fake QEMU firmware would be at. Board/SoC code which uses this mechanism should no longer set the CPU psci-conduit property directly. It should only set the start-powered-off property for secondaries if EL3 guest firmware running bare metal expects that rather than the alternative "all CPUs start executing the firmware at once". Note that when calculating whether we are going to run guest code at EL3, we ignore the setting of arm_boot_info::secure_board_setup, which might cause us to run a stub bit of guest code at EL3 which does some board-specific setup before dropping to EL2 or EL1 to run the guest kernel. This is OK because only one board that enables PSCI sets secure_board_setup (the highbank board), and the stub code it writes will behave the same way whether the one SMC call it makes is handled by "emulate the SMC" or by "PSCI default returns an error code". So we can leave that stub code in place until after we've changed the PSCI default behaviour; at that point we will remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20220127154639.2090164-4-peter.maydell@linaro.org
2022-02-08cpu.c: Make start-powered-off settable after realizePeter Maydell1-1/+21
The CPU object's start-powered-off property is currently only settable before the CPU object is realized. For arm machines this is awkward, because we would like to decide whether the CPU should be powered-off based on how we are booting the guest code, which is something done in the machine model code and in common code called by the machine model, which runs much later and in completely different parts of the codebase from the SoC object code that is responsible for creating and realizing the CPU objects. Allow start-powered-off to be set after realize. Since this isn't something that's supported by the DEFINE_PROP_* macros, we have to switch the property definition to use the object_class_property_add_bool() function. Note that it doesn't conceptually make sense to change the setting of the property after the machine has been completely initialized, beacuse this would mean that the behaviour of the machine when first started would differ from its behaviour when the system is subsequently reset. (It would also require the underlying state to be migrated, which we don't do.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20220127154639.2090164-3-peter.maydell@linaro.org
2022-02-08target/arm: make psci-conduit settable after realizePeter Maydell1-1/+5
We want to allow the psci-conduit property to be set after realize, because the parts of the code which are best placed to decide if it's OK to enable QEMU's builtin PSCI emulation (the board code and the arm_load_kernel() function are distant from the code which creates and realizes CPUs (typically inside an SoC object's init and realize method) and run afterwards. Since the DEFINE_PROP_* macros don't have support for creating properties which can be changed after realize, change the property to be created with object_property_add_uint32_ptr(), which is what we already use in this function for creating settable-after-realize properties like init-svtor and init-nsvtor. Note that it doesn't conceptually make sense to change the setting of the property after the machine has been completely initialized, beacuse this would mean that the behaviour of the machine when first started would differ from its behaviour when the system is subsequently reset. (It would also require the underlying state to be migrated, which we don't do.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Cédric Le Goater <clg@kaod.org> Message-id: 20220127154639.2090164-2-peter.maydell@linaro.org
2022-02-08hw/arm/xlnx-zynqmp: 'Or' the QSPI / QSPI DMA IRQsFrancisco Iglesias2-2/+14
'Or' the IRQs coming from the QSPI and QSPI DMA models. This is done for avoiding the situation where one of the models incorrectly deasserts an interrupt asserted from the other model (which will result in that the IRQ is lost and will not reach guest SW). Signed-off-by: Francisco Iglesias <francisco.iglesias@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Luc Michel <luc@lmichel.fr> Message-id: 20220203151742.1457-1-francisco.iglesias@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08target/arm: Use CPTR_TFP with CPTR_EL3 in fp_exception_elRichard Henderson1-1/+1
Use the named bit rather than a bare extract32. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20220127063428.30212-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08target/arm: Fix {fp, sve}_exception_el for VHE mode runningRichard Henderson1-17/+60
When HCR_EL2.E2H is set, the format of CPTR_EL2 changes to look more like CPACR_EL1, with ZEN and FPEN fields instead of TZ and TFP fields. Reported-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20220127063428.30212-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08target/arm: Tidy sve_exception_el for CPACR_EL1 accessRichard Henderson1-19/+17
Extract entire fields for ZEN and FPEN, rather than testing specific bits. This makes it easier to follow the code versus the ARM spec. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20220127063428.30212-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-08target/arm: Fix sve_zcr_len_for_el for VHE mode runningRichard Henderson1-1/+2
When HCR_EL2.{E2H,TGE} == '11', ZCR_EL1 is unused. Reported-by: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com> Message-id: 20220127063428.30212-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-07Merge remote-tracking branch ↵Peter Maydell26-113/+167
'remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request' into staging Linux-user pull request 20220207 Fix target rlimits for alpha Add startime in /proc/self/stat # gpg: Signature made Mon 07 Feb 2022 08:27:27 GMT # gpg: using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C # gpg: issuer "laurent@vivier.eu" # gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full] # gpg: aka "Laurent Vivier <laurent@vivier.eu>" [full] # gpg: aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full] # Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F 5173 F30C 38BD 3F2F BE3C * remotes/lvivier-gitlab/tags/linux-user-for-7.0-pull-request: linux-user/syscall: Translate TARGET_RLIMIT_RTTIME linux-user: Move generic TARGET_RLIMIT* definitions to generic/target_resource.h linux-user: Implement starttime field in self stat emulation linux-user: sigprocmask check read perms first linux-user: rt_sigprocmask, check read perms first linux-user: Fix inotify on aarch64 linux-user/alpha: Fix target rlimits for alpha and rearrange for clarity linux-user: Remove unnecessary 'aligned' attribute from TaskState Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-06Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell29-36/+1429
virtio,pc: features, cleanups, fixes Part of ACPI ERST support fixes, cleanups Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Sun 06 Feb 2022 09:36:24 GMT # gpg: using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469 # gpg: issuer "mst@redhat.com" # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [full] # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" [full] # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (24 commits) util/oslib-posix: Fix missing unlock in the error path of os_mem_prealloc() ACPI ERST: step 6 of bios-tables-test.c ACPI ERST: bios-tables-test testcase ACPI ERST: qtest for ERST ACPI ERST: create ACPI ERST table for pc/x86 machines ACPI ERST: build the ACPI ERST table ACPI ERST: support for ACPI ERST feature ACPI ERST: header file for ERST ACPI ERST: PCI device_id for ERST ACPI ERST: bios-tables-test.c steps 1 and 2 libvhost-user: Map shared RAM with MAP_NORESERVE to support virtio-mem with hugetlb libvhost-user: handle removal of identical regions libvhost-user: prevent over-running max RAM slots libvhost-user: fix VHOST_USER_REM_MEM_REG not closing the fd libvhost-user: Simplify VHOST_USER_REM_MEM_REG libvhost-user: Add vu_add_mem_reg input validation libvhost-user: Add vu_rem_mem_reg input validation tests: acpi: test short OEM_ID/OEM_TABLE_ID values in test_oem_fields() tests: acpi: update expected blobs acpi: fix OEM ID/OEM Table ID padding ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-06util/oslib-posix: Fix missing unlock in the error path of os_mem_prealloc()David Hildenbrand1-0/+1
We're missing an unlock in case installing the signal handler failed. Fortunately, we barely see this error in real life. Fixes: a960d6642d39 ("util/oslib-posix: Support concurrent os_mem_prealloc() invocation") Fixes: CID 1468941 Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Pankaj Gupta <pankaj.gupta@ionos.com> Cc: Daniel P. Berrangé <berrange@redhat.com> Cc: Michal Privoznik <mprivozn@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20220111120830.119912-1-david@redhat.com> Reviewed-by: Pankaj Gupta <pankaj.gupta@ionos.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: step 6 of bios-tables-test.cEric DeVolder6-5/+0
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 6. Below is the disassembly of tests/data/acpi/pc/ERST.acpierst. /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20180508 (64-bit version) * Copyright (c) 2000 - 2018 Intel Corporation * * Disassembly of tests/data/acpi/pc/ERST.acpierst, Thu Dec 2 13:32:07 2021 * * ACPI Data Table [ERST] * * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue */ [000h 0000 4] Signature : "ERST" [Error Record Serialization Table] [004h 0004 4] Table Length : 00000390 [008h 0008 1] Revision : 01 [009h 0009 1] Checksum : D6 [00Ah 0010 6] Oem ID : "BOCHS " [010h 0016 8] Oem Table ID : "BXPC " [018h 0024 4] Oem Revision : 00000001 [01Ch 0028 4] Asl Compiler ID : "BXPC" [020h 0032 4] Asl Compiler Revision : 00000001 [024h 0036 4] Serialization Header Length : 00000030 [028h 0040 4] Reserved : 00000000 [02Ch 0044 4] Instruction Entry Count : 0000001B [030h 0048 1] Action : 00 [Begin Write Operation] [031h 0049 1] Instruction : 03 [Write Register Value] [032h 0050 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [033h 0051 1] Reserved : 00 [034h 0052 12] Register Region : [Generic Address Structure] [034h 0052 1] Space ID : 00 [SystemMemory] [035h 0053 1] Bit Width : 20 [036h 0054 1] Bit Offset : 00 [037h 0055 1] Encoded Access Width : 03 [DWord Access:32] [038h 0056 8] Address : 00000000FEBF3000 [040h 0064 8] Value : 0000000000000000 [048h 0072 8] Mask : 00000000000000FF [050h 0080 1] Action : 01 [Begin Read Operation] [051h 0081 1] Instruction : 03 [Write Register Value] [052h 0082 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [053h 0083 1] Reserved : 00 [054h 0084 12] Register Region : [Generic Address Structure] [054h 0084 1] Space ID : 00 [SystemMemory] [055h 0085 1] Bit Width : 20 [056h 0086 1] Bit Offset : 00 [057h 0087 1] Encoded Access Width : 03 [DWord Access:32] [058h 0088 8] Address : 00000000FEBF3000 [060h 0096 8] Value : 0000000000000001 [068h 0104 8] Mask : 00000000000000FF [070h 0112 1] Action : 02 [Begin Clear Operation] [071h 0113 1] Instruction : 03 [Write Register Value] [072h 0114 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [073h 0115 1] Reserved : 00 [074h 0116 12] Register Region : [Generic Address Structure] [074h 0116 1] Space ID : 00 [SystemMemory] [075h 0117 1] Bit Width : 20 [076h 0118 1] Bit Offset : 00 [077h 0119 1] Encoded Access Width : 03 [DWord Access:32] [078h 0120 8] Address : 00000000FEBF3000 [080h 0128 8] Value : 0000000000000002 [088h 0136 8] Mask : 00000000000000FF [090h 0144 1] Action : 03 [End Operation] [091h 0145 1] Instruction : 03 [Write Register Value] [092h 0146 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [093h 0147 1] Reserved : 00 [094h 0148 12] Register Region : [Generic Address Structure] [094h 0148 1] Space ID : 00 [SystemMemory] [095h 0149 1] Bit Width : 20 [096h 0150 1] Bit Offset : 00 [097h 0151 1] Encoded Access Width : 03 [DWord Access:32] [098h 0152 8] Address : 00000000FEBF3000 [0A0h 0160 8] Value : 0000000000000003 [0A8h 0168 8] Mask : 00000000000000FF [0B0h 0176 1] Action : 04 [Set Record Offset] [0B1h 0177 1] Instruction : 02 [Write Register] [0B2h 0178 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [0B3h 0179 1] Reserved : 00 [0B4h 0180 12] Register Region : [Generic Address Structure] [0B4h 0180 1] Space ID : 00 [SystemMemory] [0B5h 0181 1] Bit Width : 20 [0B6h 0182 1] Bit Offset : 00 [0B7h 0183 1] Encoded Access Width : 03 [DWord Access:32] [0B8h 0184 8] Address : 00000000FEBF3008 [0C0h 0192 8] Value : 0000000000000000 [0C8h 0200 8] Mask : 00000000FFFFFFFF [0D0h 0208 1] Action : 04 [Set Record Offset] [0D1h 0209 1] Instruction : 03 [Write Register Value] [0D2h 0210 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [0D3h 0211 1] Reserved : 00 [0D4h 0212 12] Register Region : [Generic Address Structure] [0D4h 0212 1] Space ID : 00 [SystemMemory] [0D5h 0213 1] Bit Width : 20 [0D6h 0214 1] Bit Offset : 00 [0D7h 0215 1] Encoded Access Width : 03 [DWord Access:32] [0D8h 0216 8] Address : 00000000FEBF3000 [0E0h 0224 8] Value : 0000000000000004 [0E8h 0232 8] Mask : 00000000000000FF [0F0h 0240 1] Action : 05 [Execute Operation] [0F1h 0241 1] Instruction : 03 [Write Register Value] [0F2h 0242 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [0F3h 0243 1] Reserved : 00 [0F4h 0244 12] Register Region : [Generic Address Structure] [0F4h 0244 1] Space ID : 00 [SystemMemory] [0F5h 0245 1] Bit Width : 20 [0F6h 0246 1] Bit Offset : 00 [0F7h 0247 1] Encoded Access Width : 03 [DWord Access:32] [0F8h 0248 8] Address : 00000000FEBF3008 [100h 0256 8] Value : 000000000000009C [108h 0264 8] Mask : 00000000000000FF [110h 0272 1] Action : 05 [Execute Operation] [111h 0273 1] Instruction : 03 [Write Register Value] [112h 0274 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [113h 0275 1] Reserved : 00 [114h 0276 12] Register Region : [Generic Address Structure] [114h 0276 1] Space ID : 00 [SystemMemory] [115h 0277 1] Bit Width : 20 [116h 0278 1] Bit Offset : 00 [117h 0279 1] Encoded Access Width : 03 [DWord Access:32] [118h 0280 8] Address : 00000000FEBF3000 [120h 0288 8] Value : 0000000000000005 [128h 0296 8] Mask : 00000000000000FF [130h 0304 1] Action : 06 [Check Busy Status] [131h 0305 1] Instruction : 03 [Write Register Value] [132h 0306 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [133h 0307 1] Reserved : 00 [134h 0308 12] Register Region : [Generic Address Structure] [134h 0308 1] Space ID : 00 [SystemMemory] [135h 0309 1] Bit Width : 20 [136h 0310 1] Bit Offset : 00 [137h 0311 1] Encoded Access Width : 03 [DWord Access:32] [138h 0312 8] Address : 00000000FEBF3000 [140h 0320 8] Value : 0000000000000006 [148h 0328 8] Mask : 00000000000000FF [150h 0336 1] Action : 06 [Check Busy Status] [151h 0337 1] Instruction : 01 [Read Register Value] [152h 0338 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [153h 0339 1] Reserved : 00 [154h 0340 12] Register Region : [Generic Address Structure] [154h 0340 1] Space ID : 00 [SystemMemory] [155h 0341 1] Bit Width : 20 [156h 0342 1] Bit Offset : 00 [157h 0343 1] Encoded Access Width : 03 [DWord Access:32] [158h 0344 8] Address : 00000000FEBF3008 [160h 0352 8] Value : 0000000000000001 [168h 0360 8] Mask : 00000000000000FF [170h 0368 1] Action : 07 [Get Command Status] [171h 0369 1] Instruction : 03 [Write Register Value] [172h 0370 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [173h 0371 1] Reserved : 00 [174h 0372 12] Register Region : [Generic Address Structure] [174h 0372 1] Space ID : 00 [SystemMemory] [175h 0373 1] Bit Width : 20 [176h 0374 1] Bit Offset : 00 [177h 0375 1] Encoded Access Width : 03 [DWord Access:32] [178h 0376 8] Address : 00000000FEBF3000 [180h 0384 8] Value : 0000000000000007 [188h 0392 8] Mask : 00000000000000FF [190h 0400 1] Action : 07 [Get Command Status] [191h 0401 1] Instruction : 00 [Read Register] [192h 0402 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [193h 0403 1] Reserved : 00 [194h 0404 12] Register Region : [Generic Address Structure] [194h 0404 1] Space ID : 00 [SystemMemory] [195h 0405 1] Bit Width : 20 [196h 0406 1] Bit Offset : 00 [197h 0407 1] Encoded Access Width : 03 [DWord Access:32] [198h 0408 8] Address : 00000000FEBF3008 [1A0h 0416 8] Value : 0000000000000000 [1A8h 0424 8] Mask : 00000000000000FF [1B0h 0432 1] Action : 08 [Get Record Identifier] [1B1h 0433 1] Instruction : 03 [Write Register Value] [1B2h 0434 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [1B3h 0435 1] Reserved : 00 [1B4h 0436 12] Register Region : [Generic Address Structure] [1B4h 0436 1] Space ID : 00 [SystemMemory] [1B5h 0437 1] Bit Width : 20 [1B6h 0438 1] Bit Offset : 00 [1B7h 0439 1] Encoded Access Width : 03 [DWord Access:32] [1B8h 0440 8] Address : 00000000FEBF3000 [1C0h 0448 8] Value : 0000000000000008 [1C8h 0456 8] Mask : 00000000000000FF [1D0h 0464 1] Action : 08 [Get Record Identifier] [1D1h 0465 1] Instruction : 00 [Read Register] [1D2h 0466 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [1D3h 0467 1] Reserved : 00 [1D4h 0468 12] Register Region : [Generic Address Structure] [1D4h 0468 1] Space ID : 00 [SystemMemory] [1D5h 0469 1] Bit Width : 40 [1D6h 0470 1] Bit Offset : 00 [1D7h 0471 1] Encoded Access Width : 04 [QWord Access:64] [1D8h 0472 8] Address : 00000000FEBF3008 [1E0h 0480 8] Value : 0000000000000000 [1E8h 0488 8] Mask : FFFFFFFFFFFFFFFF [1F0h 0496 1] Action : 09 [Set Record Identifier] [1F1h 0497 1] Instruction : 02 [Write Register] [1F2h 0498 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [1F3h 0499 1] Reserved : 00 [1F4h 0500 12] Register Region : [Generic Address Structure] [1F4h 0500 1] Space ID : 00 [SystemMemory] [1F5h 0501 1] Bit Width : 40 [1F6h 0502 1] Bit Offset : 00 [1F7h 0503 1] Encoded Access Width : 04 [QWord Access:64] [1F8h 0504 8] Address : 00000000FEBF3008 [200h 0512 8] Value : 0000000000000000 [208h 0520 8] Mask : FFFFFFFFFFFFFFFF [210h 0528 1] Action : 09 [Set Record Identifier] [211h 0529 1] Instruction : 03 [Write Register Value] [212h 0530 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [213h 0531 1] Reserved : 00 [214h 0532 12] Register Region : [Generic Address Structure] [214h 0532 1] Space ID : 00 [SystemMemory] [215h 0533 1] Bit Width : 20 [216h 0534 1] Bit Offset : 00 [217h 0535 1] Encoded Access Width : 03 [DWord Access:32] [218h 0536 8] Address : 00000000FEBF3000 [220h 0544 8] Value : 0000000000000009 [228h 0552 8] Mask : 00000000000000FF [230h 0560 1] Action : 0A [Get Record Count] [231h 0561 1] Instruction : 03 [Write Register Value] [232h 0562 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [233h 0563 1] Reserved : 00 [234h 0564 12] Register Region : [Generic Address Structure] [234h 0564 1] Space ID : 00 [SystemMemory] [235h 0565 1] Bit Width : 20 [236h 0566 1] Bit Offset : 00 [237h 0567 1] Encoded Access Width : 03 [DWord Access:32] [238h 0568 8] Address : 00000000FEBF3000 [240h 0576 8] Value : 000000000000000A [248h 0584 8] Mask : 00000000000000FF [250h 0592 1] Action : 0A [Get Record Count] [251h 0593 1] Instruction : 00 [Read Register] [252h 0594 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [253h 0595 1] Reserved : 00 [254h 0596 12] Register Region : [Generic Address Structure] [254h 0596 1] Space ID : 00 [SystemMemory] [255h 0597 1] Bit Width : 20 [256h 0598 1] Bit Offset : 00 [257h 0599 1] Encoded Access Width : 03 [DWord Access:32] [258h 0600 8] Address : 00000000FEBF3008 [260h 0608 8] Value : 0000000000000000 [268h 0616 8] Mask : 00000000FFFFFFFF [270h 0624 1] Action : 0B [Begin Dummy Write] [271h 0625 1] Instruction : 03 [Write Register Value] [272h 0626 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [273h 0627 1] Reserved : 00 [274h 0628 12] Register Region : [Generic Address Structure] [274h 0628 1] Space ID : 00 [SystemMemory] [275h 0629 1] Bit Width : 20 [276h 0630 1] Bit Offset : 00 [277h 0631 1] Encoded Access Width : 03 [DWord Access:32] [278h 0632 8] Address : 00000000FEBF3000 [280h 0640 8] Value : 000000000000000B [288h 0648 8] Mask : 00000000000000FF [290h 0656 1] Action : 0D [Get Error Address Range] [291h 0657 1] Instruction : 03 [Write Register Value] [292h 0658 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [293h 0659 1] Reserved : 00 [294h 0660 12] Register Region : [Generic Address Structure] [294h 0660 1] Space ID : 00 [SystemMemory] [295h 0661 1] Bit Width : 20 [296h 0662 1] Bit Offset : 00 [297h 0663 1] Encoded Access Width : 03 [DWord Access:32] [298h 0664 8] Address : 00000000FEBF3000 [2A0h 0672 8] Value : 000000000000000D [2A8h 0680 8] Mask : 00000000000000FF [2B0h 0688 1] Action : 0D [Get Error Address Range] [2B1h 0689 1] Instruction : 00 [Read Register] [2B2h 0690 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [2B3h 0691 1] Reserved : 00 [2B4h 0692 12] Register Region : [Generic Address Structure] [2B4h 0692 1] Space ID : 00 [SystemMemory] [2B5h 0693 1] Bit Width : 40 [2B6h 0694 1] Bit Offset : 00 [2B7h 0695 1] Encoded Access Width : 04 [QWord Access:64] [2B8h 0696 8] Address : 00000000FEBF3008 [2C0h 0704 8] Value : 0000000000000000 [2C8h 0712 8] Mask : FFFFFFFFFFFFFFFF [2D0h 0720 1] Action : 0E [Get Error Address Length] [2D1h 0721 1] Instruction : 03 [Write Register Value] [2D2h 0722 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [2D3h 0723 1] Reserved : 00 [2D4h 0724 12] Register Region : [Generic Address Structure] [2D4h 0724 1] Space ID : 00 [SystemMemory] [2D5h 0725 1] Bit Width : 20 [2D6h 0726 1] Bit Offset : 00 [2D7h 0727 1] Encoded Access Width : 03 [DWord Access:32] [2D8h 0728 8] Address : 00000000FEBF3000 [2E0h 0736 8] Value : 000000000000000E [2E8h 0744 8] Mask : 00000000000000FF [2F0h 0752 1] Action : 0E [Get Error Address Length] [2F1h 0753 1] Instruction : 00 [Read Register] [2F2h 0754 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [2F3h 0755 1] Reserved : 00 [2F4h 0756 12] Register Region : [Generic Address Structure] [2F4h 0756 1] Space ID : 00 [SystemMemory] [2F5h 0757 1] Bit Width : 40 [2F6h 0758 1] Bit Offset : 00 [2F7h 0759 1] Encoded Access Width : 04 [QWord Access:64] [2F8h 0760 8] Address : 00000000FEBF3008 [300h 0768 8] Value : 0000000000000000 [308h 0776 8] Mask : 00000000FFFFFFFF [310h 0784 1] Action : 0F [Get Error Attributes] [311h 0785 1] Instruction : 03 [Write Register Value] [312h 0786 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [313h 0787 1] Reserved : 00 [314h 0788 12] Register Region : [Generic Address Structure] [314h 0788 1] Space ID : 00 [SystemMemory] [315h 0789 1] Bit Width : 20 [316h 0790 1] Bit Offset : 00 [317h 0791 1] Encoded Access Width : 03 [DWord Access:32] [318h 0792 8] Address : 00000000FEBF3000 [320h 0800 8] Value : 000000000000000F [328h 0808 8] Mask : 00000000000000FF [330h 0816 1] Action : 0F [Get Error Attributes] [331h 0817 1] Instruction : 00 [Read Register] [332h 0818 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [333h 0819 1] Reserved : 00 [334h 0820 12] Register Region : [Generic Address Structure] [334h 0820 1] Space ID : 00 [SystemMemory] [335h 0821 1] Bit Width : 20 [336h 0822 1] Bit Offset : 00 [337h 0823 1] Encoded Access Width : 03 [DWord Access:32] [338h 0824 8] Address : 00000000FEBF3008 [340h 0832 8] Value : 0000000000000000 [348h 0840 8] Mask : 00000000FFFFFFFF [350h 0848 1] Action : 10 [Execute Timings] [351h 0849 1] Instruction : 03 [Write Register Value] [352h 0850 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [353h 0851 1] Reserved : 00 [354h 0852 12] Register Region : [Generic Address Structure] [354h 0852 1] Space ID : 00 [SystemMemory] [355h 0853 1] Bit Width : 20 [356h 0854 1] Bit Offset : 00 [357h 0855 1] Encoded Access Width : 03 [DWord Access:32] [358h 0856 8] Address : 00000000FEBF3000 [360h 0864 8] Value : 0000000000000010 [368h 0872 8] Mask : 00000000000000FF [370h 0880 1] Action : 10 [Execute Timings] [371h 0881 1] Instruction : 00 [Read Register] [372h 0882 1] Flags (decoded below) : 00 Preserve Register Bits : 0 [373h 0883 1] Reserved : 00 [374h 0884 12] Register Region : [Generic Address Structure] [374h 0884 1] Space ID : 00 [SystemMemory] [375h 0885 1] Bit Width : 40 [376h 0886 1] Bit Offset : 00 [377h 0887 1] Encoded Access Width : 04 [QWord Access:64] [378h 0888 8] Address : 00000000FEBF3008 [380h 0896 8] Value : 0000000000000000 [388h 0904 8] Mask : FFFFFFFFFFFFFFFF Raw Table Data: Length 912 (0x390) Note that the contents of tests/data/q35/ERST.acpierst and tests/data/microvm/ERST.pcie are the same except for differences due to assigned base address. Files tests/data/pc/DSDT.acpierst and tests/data/acpi/q35/DSDT.acpierst are new files (and are included as a result of 'make check' process). Rather than provide the entire content, I am providing the differences between pc/DSDT and pc/DSDT.acpierst, and the difference between q35/DSDT and q35/DSDT.acpierst, with an explanation to follow. diff pc/DSDT pc/DSDT.acpierst: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/pc/DSDT, Thu Dec 2 10:10:13 2021 + * Disassembly of tests/data/acpi/pc/DSDT.acpierst, Thu Dec 2 12:59:36 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00001772 (6002) + * Length 0x00001751 (5969) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0x9E + * Checksum 0x95 * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -964,16 +964,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " Device (S18) { - Name (_SUN, 0x03) // _SUN: Slot User Number Name (_ADR, 0x00030000) // _ADR: Address - Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device - { - PCEJ (BSEL, _SUN) - } - + Name (ASUN, 0x03) Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method { - Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, _SUN)) + Return (PDSM (Arg0, Arg1, Arg2, Arg3, BSEL, ASUN)) } } @@ -1399,11 +1394,6 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " Method (DVNT, 2, NotSerialized) { - If ((Arg0 & 0x08)) - { - Notify (S18, Arg1) - } - If ((Arg0 & 0x10)) { Notify (S20, Arg1) diff q35/DSDT and q35/DSDT.acpierst: @@ -5,13 +5,13 @@ * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/DSDT, Thu Dec 2 10:10:13 2021 + * Disassembly of tests/data/acpi/q35/DSDT.acpierst, Thu Dec 2 12:59:36 2021 * * Original Table Header: * Signature "DSDT" - * Length 0x00002061 (8289) + * Length 0x00002072 (8306) * Revision 0x01 **** 32-bit table (V1), no 64-bit math support - * Checksum 0xFA + * Checksum 0x9A * OEM ID "BOCHS " * OEM Table ID "BXPC " * OEM Revision 0x00000001 (1) @@ -3278,6 +3278,11 @@ DefinitionBlock ("", "DSDT", 1, "BOCHS " } } + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + Method (PCNT, 0, NotSerialized) { } For both pc and q35, there is but a small difference between this DSDT.acpierst and the corresponding DSDT. In both cases, the changes occur under the hiearchy: Scope (\_SB) { Scope (PCI0) { which leads me to believe that the change to the DSDT was needed due to the introduction of the ERST PCI device. And is explained in detail by Ani Sinha: I have convinced myself of the changes we see in the DSDT tables. On i440fx side, we are adding a non-hotpluggable pci device on slot 3. So the changes we see are basically replacing an empty hotpluggable slot on the pci root port with a non-hotplugggable device. On q35, bsel on pcie root bus is not set (its not hotpluggable bus), so the change basically adds the address enumeration for the device. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Acked-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-11-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: bios-tables-test testcaseEric DeVolder1-0/+54
This change implements the test suite checks for the ERST table. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-10-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: qtest for ERSTEric DeVolder2-0/+166
This change provides a qtest that locates and then does a simple interrogation of the ERST feature within the guest. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-9-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: create ACPI ERST table for pc/x86 machinesEric DeVolder3-0/+35
This change exposes ACPI ERST support for x86 guests. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-8-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: build the ACPI ERST tableEric DeVolder1-0/+211
This builds the ACPI ERST table to inform OSPM how to communicate with the acpi-erst device. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-7-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: support for ACPI ERST featureEric DeVolder4-0/+862
This implements a PCI device for ACPI ERST. This implements the non-NVRAM "mode" of operation for ERST as it is supported by Linux and Windows. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-6-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: header file for ERSTEric DeVolder1-0/+19
This change introduces the public defintions for ACPI ERST. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-5-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: PCI device_id for ERSTEric DeVolder1-0/+1
This change reserves the PCI device_id for the new ACPI ERST device. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Acked-by: Ani Sinha <ani@anisinha.ca> Message-Id: <1643402289-22216-4-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-06ACPI ERST: bios-tables-test.c steps 1 and 2Eric DeVolder6-0/+5
Following the guidelines in tests/qtest/bios-tables-test.c, this change adds empty placeholder files per step 1 for the new ERST table, and excludes resulting changed files in bios-tables-test-allowed-diff.h per step 2. Signed-off-by: Eric DeVolder <eric.devolder@oracle.com> Acked-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <1643402289-22216-2-git-send-email-eric.devolder@oracle.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04libvhost-user: Map shared RAM with MAP_NORESERVE to support virtio-mem with ↵David Hildenbrand1-5/+5
hugetlb For fd-based shared memory, MAP_NORESERVE is only effective for hugetlb, otherwise it's ignored. Older Linux versions that didn't support reservation of huge pages ignored MAP_NORESERVE completely. The first client to mmap a hugetlb fd without MAP_NORESERVE will trigger reservation of huge pages for the whole mmapped range. There are two cases to consider: 1) QEMU mapped RAM without MAP_NORESERVE We're not dealing with a sparse mapping, huge pages for the whole range have already been reserved by QEMU. An additional mmap() without MAP_NORESERVE won't have any effect on the reservation. 2) QEMU mapped RAM with MAP_NORESERVE We're delaing with a sparse mapping, no huge pages should be reserved. Further mappings without MAP_NORESERVE should be avoided. For 1), it doesn't matter if we set MAP_NORESERVE or not, so we can simply set it. For 2), we'd be overriding QEMUs decision and trigger reservation of huge pages, which might just fail if there are not sufficient huge pages around. We must map with MAP_NORESERVE. This change is required to support virtio-mem with hugetlb: a virtio-mem device mapped into the guest physical memory corresponds to a sparse memory mapping and QEMU maps this memory with MAP_NORESERVE. Whenever memory in that sparse region will be accessed by the VM, QEMU populates huge pages for the affected range by preallocating memory and handling any preallocation errors gracefully. So let's map shared RAM with MAP_NORESERVE. As libvhost-user only supports Linux, there shouldn't be anything to take care of in regard of other OS support. Without this change, libvhost-user will fail mapping the region if there are currently not enough huge pages to perform the reservation: fv_panic: libvhost-user: region mmap error: Cannot allocate memory Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Raphael Norwitz <raphael.norwitz@nutanix.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Cc: Dr. David Alan Gilbert <dgilbert@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Message-Id: <20220111123939.132659-1-david@redhat.com> Acked-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
2022-02-04libvhost-user: handle removal of identical regionsRaphael Norwitz1-12/+16
Today if QEMU (or any other VMM) has sent multiple copies of the same region to a libvhost-user based backend and then attempts to remove the region, only one instance of the region will be removed, leaving stale copies of the region in dev->regions[]. This change resolves this by having vu_rem_mem_reg() iterate through all regions in dev->regions[] and delete all matching regions. Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <20220117041050.19718-7-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com>
2022-02-04libvhost-user: prevent over-running max RAM slotsRaphael Norwitz1-0/+8
When VHOST_USER_PROTOCOL_F_CONFIGURE_MEM_SLOTS support was added to libvhost-user, no guardrails were added to protect against QEMU attempting to hot-add too many RAM slots to a VM with a libvhost-user based backed attached. This change adds the missing error handling by introducing a check on the number of RAM slots the device has available before proceeding to process the VHOST_USER_ADD_MEM_REG message. Suggested-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <20220117041050.19718-6-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-04libvhost-user: fix VHOST_USER_REM_MEM_REG not closing the fdDavid Hildenbrand1-0/+2
We end up not closing the file descriptor, resulting in leaking one file descriptor for each VHOST_USER_REM_MEM_REG message. Fixes: 875b9fd97b34 ("Support individual region unmap in libvhost-user") Cc: Michael S. Tsirkin <mst@redhat.com> Cc: Raphael Norwitz <raphael.norwitz@nutanix.com> Cc: "Marc-André Lureau" <marcandre.lureau@redhat.com> Cc: Stefan Hajnoczi <stefanha@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Coiby Xu <coiby.xu@gmail.com> Signed-off-by: David Hildenbrand <david@redhat.com> Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <20220117041050.19718-5-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04libvhost-user: Simplify VHOST_USER_REM_MEM_REGDavid Hildenbrand1-16/+14
Let's avoid having to manually copy all elements. Copy only the ones necessary to close the hole and perform the operation in-place without a second array. Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: David Hildenbrand <david@redhat.com> Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <20220117041050.19718-4-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04libvhost-user: Add vu_add_mem_reg input validationRaphael Norwitz1-0/+15
Today if multiple FDs are sent from the VMM to the backend in a VHOST_USER_ADD_MEM_REG message, one FD will be mapped and the remaining FDs will be leaked. Therefore if multiple FDs are sent we report an error and fail the operation, closing all FDs in the message. Likewise in case the VMM sends a message with a size less than that of a memory region descriptor, we add a check to gracefully report an error and fail the operation rather than crashing. Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <20220117041050.19718-3-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com>
2022-02-04libvhost-user: Add vu_rem_mem_reg input validationRaphael Norwitz2-0/+17
Today if multiple FDs are sent from the VMM to the backend in a VHOST_USER_REM_MEM_REG message, one FD will be unmapped and the remaining FDs will be leaked. Therefore if multiple FDs are sent we report an error and fail the operation, closing all FDs in the message. Likewise in case the VMM sends a message with a size less than that of a memory region descriptor, we add a check to gracefully report an error and fail the operation rather than crashing. Signed-off-by: Raphael Norwitz <raphael.norwitz@nutanix.com> Message-Id: <20220117041050.19718-2-raphael.norwitz@nutanix.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: David Hildenbrand <david@redhat.com>
2022-02-04tests: acpi: test short OEM_ID/OEM_TABLE_ID values in test_oem_fields()Igor Mammedov1-6/+6
Previous patch [1] added explicit whitespace padding to OEM_ID/OEM_TABLE_ID values used in test_oem_fields() testcase to avoid false positive and bisection issues when QEMU is switched to \0' padding. As result testcase ceased to test values that were shorter than max possible length values. Update testcase to make sure that it's testing shorter IDs like it used to before [2]. 1) "tests: acpi: manually pad OEM_ID/OEM_TABLE_ID for test_oem_fields() test" 2) 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220114142641.1727679-1-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04tests: acpi: update expected blobsIgor Mammedov5-4/+0
Expected changes caused by previous commit: nvdimm ssdt (q35/pc/virt): - * OEM Table ID "NVDIMM " + * OEM Table ID "NVDIMM" SLIC test FADT (tests/data/acpi/q35/FACP.slic): -[010h 0016 8] Oem Table ID : "ME " +[010h 0016 8] Oem Table ID : "ME" Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220112130332.1648664-5-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04acpi: fix OEM ID/OEM Table ID paddingIgor Mammedov1-2/+2
Commit [2] broke original '\0' padding of OEM ID and OEM Table ID fields in headers of ACPI tables. While it doesn't have impact on default values since QEMU uses 6 and 8 characters long values respectively, it broke usecase where IDs are provided on QEMU CLI. It shouldn't affect guest (but may cause licensing verification issues in guest OS). One of the broken usecases is user supplied SLIC table with IDs shorter than max possible length, where [2] mangles IDs with extra spaces in RSDT and FADT tables whereas guest OS expects those to mirror the respective values of the used SLIC table. Fix it by replacing whitespace padding with '\0' padding in accordance with [1] and expectations of guest OS 1) ACPI spec, v2.0b 17.2 AML Grammar Definition ... //OEM ID of up to 6 characters. If the OEM ID is //shorter than 6 characters, it can be terminated //with a NULL character. 2) Fixes: 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Resolves: https://gitlab.com/qemu-project/qemu/-/issues/707 Reported-by: Dmitry V. Orekhov <dima.orekhov@gmail.com> Signed-off-by: Igor Mammedov <imammedo@redhat.com> Cc: qemu-stable@nongnu.org Message-Id: <20220112130332.1648664-4-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Ani Sinha <ani@anisinha.ca> Tested-by: Dmitry V. Orekhov dima.orekhov@gmail.com
2022-02-04tests: acpi: whitelist nvdimm's SSDT and FACP.slic expected blobsIgor Mammedov1-0/+4
The next commit will revert OEM fields whitespace padding to padding with '\0' as it was before [1]. That will change OEM Table ID for: * SSDT.*: where it was padded from 6 characters to 8 * FACP.slic: where it was padded from 2 characters to 8 after reverting whitespace padding, it will be replaced with '\0' which effectively will shorten OEM table ID to 6 and 2 characters. Whitelist affected tables before introducing the change. 1) 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220112130332.1648664-3-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04tests: acpi: manually pad OEM_ID/OEM_TABLE_ID for test_oem_fields() testIgor Mammedov1-9/+6
The next commit will revert OEM fields padding with whitespace to padding with '\0' as it was before [1]. As result test_oem_fields() will fail due to unexpectedly smaller ID sizes read from QEMU ACPI tables. Pad OEM_ID/OEM_TABLE_ID manually with spaces so that values the test puts on QEMU CLI and expected values match. 1) 602b458201 ("acpi: Permit OEM ID and OEM table ID fields to be changed") Signed-off-by: Igor Mammedov <imammedo@redhat.com> Message-Id: <20220112130332.1648664-2-imammedo@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04hw/i386: Add the possibility to disable the 'isapc' machineThomas Huth2-2/+5
We already have a CONFIG_ISAPC switch - but we're not using it yet. Add some "#ifdefs" to make it possible to disable this machine now. Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20220107160713.235918-1-thuth@redhat.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
2022-02-04cpuid: use unsigned for max cpuidMichael S. Tsirkin3-3/+3
__get_cpuid_max returns an unsigned value. For consistency, store the result in an unsigned variable. Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2022-02-03Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' ↵Peter Maydell7-41/+123
into staging Python patches Peter: I expect this to address the iotest 040,041 failures you observed on NetBSD. If it doesn't, let me know. # gpg: Signature made Thu 03 Feb 2022 01:59:32 GMT # gpg: using RSA key F9B7ABDBBCACDF95BE76CBD07DEF8106AAFC390E # gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>" [full] # Primary key fingerprint: FAEB 9711 A12C F475 812F 18F2 88A9 064D 1835 61EB # Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76 CBD0 7DEF 8106 AAFC 390E * remotes/jsnow-gitlab/tags/python-pull-request: python/aqmp: add socket bind step to legacy.py python: upgrade mypy to 0.780 python/machine: raise VMLaunchFailure exception from launch() python/aqmp: Fix negotiation with pre-"oob" QEMU Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-02Merge remote-tracking branch ↵Peter Maydell13-274/+282
'remotes/hdeller/tags/hppa-updates-pull-request' into staging Fixes and updates for hppa target This patchset fixes some important bugs in the hppa artist graphics driver: - Fix artist graphics for HP-UX and Linux - Mouse cursor fixes for HP-UX - Fix draw_line() function on artist graphic and it adds new qemu features for hppa: - Allow up to 16 emulated CPUs (instead of 8) - Add support for an emulated TOC/NMI button A new Seabios-hppa firmware is included as well: - Update SeaBIOS-hppa to VERSION 3 - New opt/hostid fw_cfg option to change hostid - Add opt/console fw_cfg option to select default console - Added 16x32 font to STI firmware Signed-off-by: Helge Deller <deller@gmx.de> # gpg: Signature made Wed 02 Feb 2022 18:08:34 GMT # gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F # gpg: Good signature from "Helge Deller <deller@gmx.de>" [unknown] # gpg: aka "Helge Deller <deller@kernel.org>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 4544 8228 2CD9 10DB EF3D 25F8 3E5F 3D04 A7A2 4603 # Subkey fingerprint: BCE9 123E 1AD2 9F07 C049 BBDE F712 B510 A23A 0F5F * remotes/hdeller/tags/hppa-updates-pull-request: hw/display/artist: Fix draw_line() artefacts hw/display/artist: Mouse cursor fixes for HP-UX hw/display/artist: rewrite vram access mode handling hppa: Add support for an emulated TOC/NMI button. hw/hppa: Allow up to 16 emulated CPUs seabios-hppa: Update SeaBIOS-hppa to VERSION 3 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-02python/aqmp: add socket bind step to legacy.pyJohn Snow2-3/+41
The synchronous QMP library would bind to the server address during __init__(). The new library delays this to the accept() call, because binding occurs inside of the call to start_[unix_]server(), which is an async method -- so it cannot happen during __init__ anymore. Python 3.7+ adds the ability to create the server (and thus the bind() call) and begin the active listening in separate steps, but we don't have that functionality in 3.6, our current minimum. Therefore ... Add a temporary workaround that allows the synchronous version of the client to bind the socket in advance, guaranteeing that there will be a UNIX socket in the filesystem ready for the QEMU client to connect to without a race condition. (Yes, it's a bit ugly. Fixing it more nicely will have to wait until our minimum Python version is 3.7+.) Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20220201041134.1237016-5-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-02-02python: upgrade mypy to 0.780John Snow2-28/+40
We need a slightly newer version of mypy in order to use some features of the asyncio server functions in the next commit. (Note: pipenv is not really suited to upgrading individual packages; I need to replace this tool with something better for the task. For now, the miscellaneous updates not related to the mypy upgrade are simply beyond my control. It's on my list to take care of soon.) Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20220201041134.1237016-4-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-02-02python/machine: raise VMLaunchFailure exception from launch()John Snow2-8/+40
This allows us to pack in some extra information about the failure, which guarantees that if the caller did not *intentionally* cause a failure (by capturing this Exception), some pretty good clues will be printed at the bottom of the traceback information. This will help make failures in the event of a non-negative return code more obvious when they go unhandled; the current behavior in _post_shutdown() is to print a warning message only in the event of signal-based terminations (for negative return codes). (Note: In Python, catching BaseException instead of Exception catches a broader array of Exception events, including SystemExit and KeyboardInterrupt. We do not want to "wrap" such exceptions as a VMLaunchFailure, because that will 'downgrade' the exception from a BaseException to a regular Exception. We do, however, want to perform cleanup in either case, so catch on the broadest scope and wrap-and-re-raise only in the more targeted scope.) Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20220201041134.1237016-3-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-02-02python/aqmp: Fix negotiation with pre-"oob" QEMUJohn Snow1-2/+2
QEMU versions prior to the "oob" capability *also* can't accept the "enable" keyword argument at all. Fix the handshake process with older QEMU versions. Signed-off-by: John Snow <jsnow@redhat.com> Reviewed-by: Hanna Reitz <hreitz@redhat.com> Reviewed-by: Kevin Wolf <kwolf@redhat.com> Message-id: 20220201041134.1237016-2-jsnow@redhat.com Signed-off-by: John Snow <jsnow@redhat.com>
2022-02-02hw/display/artist: Fix draw_line() artefactsSven Schnelle1-2/+3
The draw_line() function left artefacts on the screen because it was using the x/y variables which were incremented in the loop before. Fix it by using the unmodified x1/x2 variables instead. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de> Cc: qemu-stable@nongnu.org Signed-off-by: Helge Deller <deller@gmx.de>
2022-02-02hw/display/artist: Mouse cursor fixes for HP-UXHelge Deller1-8/+34
This patch fix the behaviour and positioning of the X11 mouse cursor in HP-UX. The current code missed to subtract the offset of the CURSOR_CTRL register from the current mouse cursor position. The HP-UX graphics driver stores in this register the offset of the mouse graphics compared to the current cursor position. Without this adjustment the mouse behaves strange at the screen borders. Additionally, depending on the HP-UX version, the mouse cursor position in the cursor_pos register reports different values. To accommodate this track the current min and max reported values and auto-adjust at runtime. With this fix the mouse now behaves as expected on HP-UX 10 and 11. Signed-off-by: Helge Deller <deller@gmx.de> Cc: qemu-stable@nongnu.org Signed-off-by: Helge Deller <deller@gmx.de>
2022-02-02hw/display/artist: rewrite vram access mode handlingSven Schnelle2-258/+166
When writing this code it was assumed that register 0x118000 is the buffer access mode for color map accesses. It turned out that this is wrong. Instead register 0x118000 sets both src and dst buffer access mode at the same time. This required a larger rewrite of the code. The good thing is that both the linear framebuffer and the register based vram access can now be combined into one function. This makes the linux 'stifb' framebuffer work, and both HP-UX 10.20 and HP-UX 11.11 are still working. Signed-off-by: Sven Schnelle <svens@stackframe.org> Signed-off-by: Helge Deller <deller@gmx.de> Cc: qemu-stable@nongnu.org Signed-off-by: Helge Deller <deller@gmx.de>
2022-02-02hppa: Add support for an emulated TOC/NMI button.Helge Deller8-4/+76
Almost all PA-RISC machines have either a button that is labeled with 'TOC' or a BMC/GSP function to trigger a TOC. TOC is a non-maskable interrupt that is sent to the processor. This can be used for diagnostic purposes like obtaining a stack trace/register dump or to enter KDB/KGDB in Linux. This patch adds support for such an emulated TOC button. It wires up the qemu monitor "nmi" command to trigger a TOC. For that it provides the hppa_nmi function which is assigned to the nmi_monitor_handler function pointer. When called it raises the EXCP_TOC hardware interrupt in the hppa_cpu_do_interrupt() function. The interrupt function then calls the architecturally defined TOC function in SeaBIOS-hppa firmware (at fixed address 0xf0000000). According to the PA-RISC PDC specification, the SeaBIOS firmware then writes the CPU registers into PIM (processor internal memmory) for later analysis. In order to write all registers it needs to know the contents of the CPU "shadow registers" and the IASQ- and IAOQ-back values. The IAOQ/IASQ values are provided by qemu in shadow registers when entering the SeaBIOS TOC function. This patch adds a new aritificial opcode "getshadowregs" (0xfffdead2) which restores the original values of the shadow registers. With this opcode SeaBIOS can store those registers as well into PIM before calling an OS-provided TOC handler. To trigger a TOC, switch to the qemu monitor with Ctrl-A C, and type in the command "nmi". After the TOC started the OS-debugger, exit the qemu monitor with Ctrl-A C. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-02hw/hppa: Allow up to 16 emulated CPUsHelge Deller1-2/+3
This brings the hppa_hardware.h file in sync with the copy in the SeaBIOS-hppa sources. In order to support up to 16 CPUs, it's required to move the HPA for MEMORY_HPA out of the address space of the new 16th CPU. The new address of 0xfffff000 worked well for Linux and HP-UX, while other addresses close to the former 0xfffbf000 area are used by the architecture for local and global broadcasts. The PIM_STORAGE_SIZE constant is used in SeaBIOS sources and is relevant for the TOC/NMI feature. Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-02seabios-hppa: Update SeaBIOS-hppa to VERSION 3Helge Deller2-0/+0
New firmware features and fixes: * Allow up to 16 CPUs * Add TOC button support: To trigger a TOC, execute "nmi" in the qemu monitor (Ctrl-A C) * New opt/hostid fw_cfg option to change hostid: -fw_cfg opt/hostid,string=334455 * Add opt/console fw_cfg option to select default console: -fw_cfg opt/console,string=serial -fw_cfg opt/console,string=graphics * Add Linux TER16x32 font to STI firmware: -fw_cfg opt/font,string=2 * Leave IRQs disabled after rendevouz Signed-off-by: Helge Deller <deller@gmx.de>
2022-02-02Merge remote-tracking branch 'remotes/bsdimp/tags/bsd-user-fix-pull-request' ↵Peter Maydell2-0/+10
into staging Pull request Fix FreeBSD 12 and 13 builds. # gpg: Signature made Tue 01 Feb 2022 21:58:37 GMT # gpg: using RSA key 2035F894B00AA3CF7CCDE1B76C1CD1287DB01100 # gpg: Good signature from "Warner Losh <wlosh@netflix.com>" [unknown] # gpg: aka "Warner Losh <imp@bsdimp.com>" [unknown] # gpg: aka "Warner Losh <imp@freebsd.org>" [unknown] # gpg: aka "Warner Losh <imp@village.org>" [unknown] # gpg: aka "Warner Losh <wlosh@bsdimp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 2035 F894 B00A A3CF 7CCD E1B7 6C1C D128 7DB0 1100 * remotes/bsdimp/tags/bsd-user-fix-pull-request: bsd-user/signal.c: Only copy the _capsicum for FreeBSD_version > 1400026 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-02-01bsd-user/signal.c: Only copy the _capsicum for FreeBSD_version > 1400026Warner Losh2-0/+10
The capsicum signal stuff is new with FreeBSD 14, rev 1400026, so only define QEMU_SI_CAPSICUM there. Only copy _capsicum when QEMU_SI_CAPSICUM is defined. Default to no info being passed for signals we make no guess about. Signed-off-by: Warner Losh <imp@bsdimp.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2022-02-01Merge remote-tracking branch 'remotes/kwolf-gitlab/tags/for-upstream' into ↵Peter Maydell10-34/+118
staging Block layer patches - rbd: fix handling of holes in .bdrv_co_block_status - Fix potential crash in bdrv_set_backing_hd() - vhost-user-blk export: Fix shutdown with requests in flight - FUSE export: Fix build failure on FreeBSD - Documentation improvements # gpg: Signature made Tue 01 Feb 2022 15:14:24 GMT # gpg: using RSA key DC3DEB159A9AF95D3D7456FE7F09B272C88F2FD6 # gpg: issuer "kwolf@redhat.com" # gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>" [full] # Primary key fingerprint: DC3D EB15 9A9A F95D 3D74 56FE 7F09 B272 C88F 2FD6 * remotes/kwolf-gitlab/tags/for-upstream: block/rbd: workaround for ceph issue #53784 block/rbd: fix handling of holes in .bdrv_co_block_status qemu-img: Unify [-b [-F]] documentation qsd: Document fuse's allow-other option block.h: remove outdated comment block/export/fuse: Fix build failure on FreeBSD block/export/fuse: Rearrange if-else-if ladder in fuse_fallocate() block/export: Fix vhost-user-blk shutdown with requests in flight block: bdrv_set_backing_hd(): use drained section qemu-storage-daemon: Fix typo in vhost-user-blk help Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-01 20:29:28 +0000