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2022-09-13target/xtensa: Honour -semihosting-config userspace=onPeter Maydell1-3/+4
Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. xtensa semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-7-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/nios2: Honour -semihosting-config userspace=onPeter Maydell1-1/+2
Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. nios2 semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-6-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/mips: Honour -semihosting-config userspace=onPeter Maydell4-10/+11
Honour the commandline -semihosting-config userspace=on option, instead of always permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(). Note that this is a behaviour change: if the user wants to do semihosting calls from userspace they must now specifically enable them on the command line. MIPS semihosting is not implemented for linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-5-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/m68k: Honour -semihosting-config userspace=onPeter Maydell1-2/+1
Honour the commandline -semihosting-config userspace=on option, instead of never permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(), instead of manually checking and always forbidding semihosting if the guest is in userspace. (Note that target/m68k doesn't support semihosting at all in the linux-user build.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-4-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/arm: Honour -semihosting-config userspace=onPeter Maydell2-23/+5
Honour the commandline -semihosting-config userspace=on option, instead of never permitting userspace semihosting calls in system emulation mode, by passing the correct value to the is_userspace argument of semihosting_enabled(), instead of manually checking and always forbidding semihosting if the guest is in userspace and this isn't the linux-user build. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-3-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13semihosting: Allow optional use of semihosting from userspacePeter Maydell10-17/+36
Currently our semihosting implementations generally prohibit use of semihosting calls in system emulation from the guest userspace. This is a very long standing behaviour justified originally "to provide some semblance of security" (since code with access to the semihosting ABI can do things like read and write arbitrary files on the host system). However, it is sometimes useful to be able to run trusted guest code which performs semihosting calls from guest userspace, notably for test code. Add a command line suboption to the existing semihosting-config option group so that you can explicitly opt in to semihosting from guest userspace with -semihosting-config userspace=on (There is no equivalent option for the user-mode emulator, because there by definition all code runs in userspace and has access to semihosting already.) This commit adds the infrastructure for the command line option and adds a bool 'is_user' parameter to the function semihosting_userspace_enabled() that target code can use to check whether it should be permitting the semihosting call for userspace. It mechanically makes all the callsites pass 'false', so they continue checking "is semihosting enabled in general". Subsequent commits will make each target that implements semihosting honour the userspace=on option by passing the correct value and removing whatever "don't do this for userspace" checking they were doing by hand. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Acked-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220822141230.3658237-2-peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/m68k: Convert semihosting errno to gdb remote errnoRichard Henderson1-2/+31
The semihosting abi used by m68k uses the gdb remote protocol filesys errnos. Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/m68k: Use semihosting/syscalls.hRichard Henderson1-232/+49
This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Acked-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/nios2: Convert semihosting errno to gdb remote errnoRichard Henderson1-2/+31
The semihosting abi used by nios2 uses the gdb remote protocol filesys errnos. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-13target/nios2: Use semihosting/syscalls.hRichard Henderson1-246/+50
This separates guest file descriptors from host file descriptors, and utilizes shared infrastructure for integration with gdbstub. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-07Merge tag 'pull-qapi-2022-09-07' of git://repo.or.cz/qemu/armbru into stagingStefan Hajnoczi7-20/+37
QAPI patches patches for 2022-09-07 # -----BEGIN PGP SIGNATURE----- # # iQJGBAABCAAwFiEENUvIs9frKmtoZ05fOHC0AOuRhlMFAmMYp0sSHGFybWJydUBy # ZWRoYXQuY29tAAoJEDhwtADrkYZTtbUP/3bHyjF4xamMwlXHi/nY/zlNKkZyhMul # SdS+KVLBxufuYmlP2mPGqG/wnK4geWnduwprl/SCSd8NdymWDVxu6tUjdPAdW6S4 # 27WZUADZtXow2tOczcKFKMve4qBZXNKtv4W/eBTDMMpfje3dWBuEx70xN1HgpCWw # i/h3J5dKwwWmHnyqroFJAEUPTx0jEk9GhzZCQ4hey2CFXDc5sgywliJA+pKv+1sF # z1g2S0rq35jd7YZnPF0M3J2MdqQo6AaOsoPqRSJMpuma0Cfvwj0UmjzQAIeaahrD # 1uEP3YEGXeOQlocDv3zqA6VFympAyFv+Ljj4XW3dsu9waBvtg2FYXQOrizxDuj1Y # nAGJ6/xYrvZ+8Eb0tbdJYnxWv7MESbswhabJA+YfnjKOTD6TV5hmuHEzoR5c5Mly # RYT+68WANXveOZ+f4oiqHQ4Gxuvp9+rU2uHQ+MvMhScDmJE7E+Gg8zELwKiQWu2q # lU5vOv55fZTHhLt/gyOAEuNvFCnbfdYluV845GBaaqLRjBPMfSoNKBtswzQbCgKH # vy5R+omAxQjjXzEL9GO2Wm50xYk5Er14ad5vAQ1256/sx3zuzQ/O0jzvGsKNPIXG # Y/dnFg3e9eT18gQ+uDyZGpYf0XV5PKlUUcomIPikWogTiZvTXMdYNWz+gt2taatE # jbxTea7AU3ty # =L82X # -----END PGP SIGNATURE----- # gpg: Signature made Wed 07 Sep 2022 10:14:35 EDT # gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653 # gpg: issuer "armbru@redhat.com" # gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full] # gpg: aka "Markus Armbruster <armbru@pond.sub.org>" [full] # Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653 * tag 'pull-qapi-2022-09-07' of git://repo.or.cz/qemu/armbru: qapi: fix examples of events missing timestamp qapi: fix example of query-hotpluggable-cpus command qapi: fix examples of blockdev-add with qcow2 qapi: fix example of MEM_UNPLUG_ERROR event qapi: fix example of DEVICE_UNPLUG_GUEST_ERROR event qapi: fix example of NIC_RX_FILTER_CHANGED event qapi: fix example of BLOCK_JOB_READY event qapi: fix example of query-dump-guest-memory-capability command qapi: fix example of query-vnc command qapi: fix example of query-ballon command Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-09-07qapi: fix examples of events missing timestampVictor Toso1-4/+23
I've used real timestamp and changing them one by one so they would not be all equal. Problem was noticed when using the example as a test case for Go bindings. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-11-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of query-hotpluggable-cpus commandVictor Toso1-2/+2
The example return type has the wrong member name. Fix it. Problem was noticed when using the example as a test case for Go bindings. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-10-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix examples of blockdev-add with qcow2Victor Toso1-5/+5
The examples use "qcow2" driver with the wrong member name for BlockdevRef alternate type. This patch changes all wrong member names from "file" to "data-file" which is the correct member name in BlockdevOptionsQcow2 for the BlockdevRef field. Problem was noticed when using the example as a test case for Go bindings. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-9-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of MEM_UNPLUG_ERROR eventVictor Toso1-1/+1
Example output was missing ',' delimiter. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-8-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of DEVICE_UNPLUG_GUEST_ERROR eventVictor Toso1-2/+1
Example output is missing a ',' delimiter and it has an extra ending curly bracket. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-7-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of NIC_RX_FILTER_CHANGED eventVictor Toso1-1/+0
Example output has an extra ending curly bracket. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-6-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of BLOCK_JOB_READY eventVictor Toso1-1/+1
Example output is missing ',' delimiter. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-5-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of query-dump-guest-memory-capability commandVictor Toso1-1/+1
Example output is missing closing curly brackets. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-4-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of query-vnc commandVictor Toso1-2/+2
Example output has an extra ',' delimiter in member "websocket" and it lacks it in "family" member. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-3-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07qapi: fix example of query-ballon commandVictor Toso1-1/+1
Example output has an extra ',' delimiter. Fix it. Problem was noticed when trying to load the example into python's json library. Signed-off-by: Victor Toso <victortoso@redhat.com> Message-Id: <20220901085840.22520-2-victortoso@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
2022-09-07Merge tag 'pull-riscv-to-apply-20220907' of ↵Stefan Hajnoczi40-558/+2228
https://github.com/alistair23/qemu into staging First RISC-V PR for QEMU 7.2 * Update [m|h]tinst CSR in interrupt handling * Force disable extensions if priv spec version does not match * fix shifts shamt value for rv128c * move zmmul out of the experimental * virt: pass random seed to fdt * Add checks for supported extension combinations * Upgrade OpenSBI to v1.1 * Fix typo and restore Pointer Masking functionality for RISC-V * Add mask agnostic behaviour (rvv_ma_all_1s) for vector extension * Add Zihintpause support * opentitan: bump opentitan version * microchip_pfsoc: fix kernel panics due to missing peripherals * Remove additional priv version check for mcountinhibit * virt machine device tree improvements * Add xicondops in ISA entry * Use official extension names for AIA CSRs # -----BEGIN PGP SIGNATURE----- # # iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmMYUCUACgkQIeENKd+X # cFRpEQf/T1FFcGq3TZrEPmqMdFPUSb+SEJNgwYFfloqkNjB2HIFbd2tKWAE1Tgjr # esV00p7YPyox1Ct+fKdwSxDxRSN9OI56v+nI8ZFwluVu7vpChuTFmOHur8rNxl1T # 8MZgP2kMxMOJSnyHCS2iV9AUFdTExS65DbmlAKzi5fpBtt9jYTPSXsI49MP8+Ku/ # 1gdv5ZF5BXDJsGs7xHvE92dRzQEVN+As64IjlknFHHpmCM1b+Ah3GekXUbKmBuDG # /NaZyZNPCYxdRmPm/D7k0SOMZSJ9sLyhXTetZ0ZpBxG1ioClX37yS5wn4NLsCz/2 # fXrnML+MQFUKZ03AZ9lWvxcu7kXfWA== # =7mGD # -----END PGP SIGNATURE----- # gpg: Signature made Wed 07 Sep 2022 04:02:45 EDT # gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054 * tag 'pull-riscv-to-apply-20220907' of https://github.com/alistair23/qemu: (44 commits) target/riscv: Update the privilege field for sscofpmf CSRs hw/riscv: virt: Add PMU DT node to the device tree target/riscv: Add few cache related PMU events target/riscv: Simplify counter predicate function target/riscv: Add sscofpmf extension support target/riscv: Add vstimecmp support target/riscv: Add stimecmp support hw/intc: Move mtimer/mtimecmp to aclint target/riscv: Use official extension names for AIA CSRs target/riscv: Add xicondops in ISA entry hw/core: fix platform bus node name hw/riscv: virt: fix syscon subnode paths hw/riscv: virt: fix the plic's address cells hw/riscv: virt: fix uart node name target/riscv: Remove additional priv version check for mcountinhibit hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripherals hw/riscv: opentitan: bump opentitan version target/riscv: Fix priority of csr related check in riscv_csrrw_check hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec() target/riscv: Add Zihintpause support ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
2022-09-07target/riscv: Update the privilege field for sscofpmf CSRsAtish Patra1-30/+60
The sscofpmf extension was ratified as a part of priv spec v1.12. Mark the csr_ops accordingly. Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: virt: Add PMU DT node to the device treeAtish Patra3-0/+74
Qemu virt machine can support few cache events and cycle/instret counters. It also supports counter overflow for these events. Add a DT node so that OpenSBI/Linux kernel is aware of the virt machine capabilities. There are some dummy nodes added for testing as well. Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add few cache related PMU eventsAtish Patra1-0/+25
Qemu can monitor the following cache related PMU events through tlb_fill functions. 1. DTLB load/store miss 3. ITLB prefetch miss Increment the PMU counter in tlb_fill function. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Tested-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Simplify counter predicate functionAtish Patra1-101/+9
All the hpmcounters and the fixed counters (CY, IR, TM) can be represented as a unified counter. Thus, the predicate function doesn't need handle each case separately. Simplify the predicate function so that we just handle things differently between RV32/RV64 and S/HS mode. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add sscofpmf extension supportAtish Patra7-11/+623
The Sscofpmf ('Ss' for Privileged arch and Supervisor-level extensions, and 'cofpmf' for Count OverFlow and Privilege Mode Filtering) extension allows the perf to handle overflow interrupts and filtering support. This patch provides a framework for programmable counters to leverage the extension. As the extension doesn't have any provision for the overflow bit for fixed counters, the fixed events can also be monitoring using programmable counters. The underlying counters for cycle and instruction counters are always running. Thus, a separate timer device is programmed to handle the overflow. Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atish.patra@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221701.41932-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add vstimecmp supportAtish Patra6-6/+118
vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add stimecmp supportAtish Patra8-1/+235
stimecmp allows the supervisor mode to update stimecmp CSR directly to program the next timer interrupt. This CSR is part of the Sstc extension which was ratified recently. Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/intc: Move mtimer/mtimecmp to aclintAtish Patra6-30/+47
Historically, The mtime/mtimecmp has been part of the CPU because they are per hart entities. However, they actually belong to aclint which is a MMIO device. Move them to the ACLINT device. This also emulates the real hardware more closely. Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220824221357.41070-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Use official extension names for AIA CSRsAnup Patel6-26/+31
The arch review of AIA spec is completed and we now have official extension names for AIA: Smaia (M-mode AIA CSRs) and Ssaia (S-mode AIA CSRs). Refer, section 1.6 of the latest AIA v0.3.1 stable specification at https://github.com/riscv/riscv-aia/releases/download/0.3.1-draft.32/riscv-interrupts-032.pdf) Based on above, we update QEMU RISC-V to: 1) Have separate config options for Smaia and Ssaia extensions which replace RISCV_FEATURE_AIA in CPU features 2) Not generate AIA INTC compatible string in virt machine Signed-off-by: Anup Patel <apatel@ventanamicro.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220820042958.377018-1-apatel@ventanamicro.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add xicondops in ISA entryRahul Pathak1-0/+1
XVentanaCondOps is Ventana custom extension. Add its extension entry in the ISA Ext array Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220816045408.1231135-1-rpathak@ventanamicro.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/core: fix platform bus node nameConor Dooley1-1/+1
"platform" is not a valid name for a bus node in dt-schema, so warnings can be see in dt-validate on a dump of the riscv virt dtb: /stuff/qemu/qemu.dtb: platform@4000000: $nodename:0: 'platform@4000000' does not match '^([a-z][a-z0-9\\-]+-bus|bus|soc|axi|ahb|apb)(@[0-9a-f]+)?$' From schema: /home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml "platform-bus" is a valid name, so use that instead. CC: Rob Herring <robh@kernel.org> Fixes: 11d306b9df ("hw/arm/sysbus-fdt: helpers for platform bus nodes addition") Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-id: 20220810184612.157317-5-mail@conchuod.ie Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: virt: fix syscon subnode pathsConor Dooley1-2/+2
The reset and poweroff features of the syscon were originally added to top level, which is a valid path for a syscon subnode. Subsequently a reorganisation was carried out while implementing NUMA in which the subnodes were moved into the /soc node. As /soc is a "simple-bus", this path is invalid, and so dt-validate produces the following warnings: /stuff/qemu/qemu.dtb: soc: poweroff: {'value': [[21845]], 'offset': [[0]], 'regmap': [[4]], 'compatible': ['syscon-poweroff']} should not be valid under {'type': 'object'} From schema: /home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml /stuff/qemu/qemu.dtb: soc: reboot: {'value': [[30583]], 'offset': [[0]], 'regmap': [[4]], 'compatible': ['syscon-reboot']} should not be valid under {'type': 'object'} From schema: /home/conor/.local/lib/python3.9/site-packages/dtschema/schemas/simple-bus.yaml Move the syscon subnodes back to the top level and silence the warnings. Reported-by: Rob Herring <robh@kernel.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20220810184612.157317-4-mail@conchuod.ie Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Fixes: 18df0b4695 ("hw/riscv: virt: Allow creating multiple NUMA sockets") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: virt: fix the plic's address cellsConor Dooley2-0/+3
When optional AIA PLIC support was added the to the virt machine, the address cells property was removed leading the issues with dt-validate on a dump from the virt machine: /stuff/qemu/qemu.dtb: plic@c000000: '#address-cells' is a required property From schema: /stuff/linux/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml Add back the property to suppress the warning. Reported-by: Rob Herring <robh@kernel.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-id: 20220810184612.157317-3-mail@conchuod.ie Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Fixes: e6faee6585 ("hw/riscv: virt: Add optional AIA APLIC support to virt machine") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: virt: fix uart node nameConor Dooley1-1/+1
"uart" is not a node name that complies with the dt-schema. Change the node name to "serial" to ix warnings seen during dt-validate on a dtbdump of the virt machine such as: /stuff/qemu/qemu.dtb: uart@10000000: $nodename:0: 'uart@10000000' does not match '^serial(@.*)?$' From schema: /stuff/linux/Documentation/devicetree/bindings/serial/8250.yaml Reported-by: Rob Herring <robh@kernel.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Message-id: 20220810184612.157317-2-mail@conchuod.ie Link: https://lore.kernel.org/linux-riscv/20220803170552.GA2250266-robh@kernel.org/ Fixes: 04331d0b56 ("RISC-V VirtIO Machine") Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Remove additional priv version check for mcountinhibitAtish Patra1-8/+0
With .min_priv_version, additiona priv version check is uncessary for mcountinhibit read/write functions. Reviewed-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Atish Patra <atishp@rivosinc.com> Message-Id: <20220816232321.558250-7-atishp@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: microchip_pfsoc: fix kernel panics due to missing peripheralsConor Dooley2-7/+74
Booting using "Direct Kernel Boot" for PolarFire SoC & skipping u-boot entirely is probably not advisable, but it does at least show signs of life. Recent Linux kernel versions make use of peripherals that are missing definitions in QEMU and lead to kernel panics. These issues almost certain rear their head for other methods of booting, but I was unable to figure out a suitable HSS version that is recent enough to support these peripherals & works with QEMU. With these peripherals added, booting a kernel with the following hangs hangs waiting for the system controller's hwrng, but the kernel no longer panics. With the Linux driver for hwrng disabled, it boots to console. qemu-system-riscv64 -M microchip-icicle-kit \ -m 2G -smp 5 \ -kernel $(vmlinux_bin) \ -dtb $(dtb)\ -initrd $(initramfs) \ -display none -serial null \ -serial stdio More peripherals are added than strictly required to fix the panics in the hopes of avoiding a replication of this problem in the future. Some of the peripherals which are in the device tree for recent kernels are implemented in the FPGA fabric. The eMMC/SD mux, which exists as an unimplemented device is replaced by a wider entry. This updated entry covers both the mux & the remainder of the FPGA fabric connected to the MSS using Fabric Interrconnect (FIC) 3. Link: https://github.com/polarfire-soc/icicle-kit-reference-design#fabric-memory-map Link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/SupportingCollateral/V1_4_Register_Map.zip Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220813135127.2971754-1-mail@conchuod.ie> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: opentitan: bump opentitan versionWilfred Mallawa2-9/+14
The following patch updates opentitan to match the new configuration, as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c Note: with this patch we now skip the usage of the opentitan `boot_rom`. The Opentitan boot rom contains hw verification for devies which we are currently not supporting in qemu. As of now, the `boot_rom` has no major significance, however, would be good to support in the future. Tested by running utests from the latest tock [1] (that supports this version of OT). [1] https://github.com/tock/tock/pull/3056 Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220812005229.358850-1-wilfred.mallawa@opensource.wdc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Fix priority of csr related check in riscv_csrrw_checkWeiwei Li1-19/+25
Normally, riscv_csrrw_check is called when executing Zicsr instructions. And we can only do access control for existed CSRs. So the priority of CSR related check, from highest to lowest, should be as follows: 1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not 2) check whether csr is existed: raise RISCV_EXCP_ILLEGAL_INST if not 3) do access control: raise RISCV_EXCP_ILLEGAL_INST or RISCV_EXCP_VIRT_ INSTRUCTION_FAULT if not allowed The predicates contain parts of function of both 2) and 3), So they need to be placed in the middle of riscv_csrrw_check Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220803123652.3700-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07hw/riscv: remove 'fdt' param from riscv_setup_rom_reset_vec()Daniel Henrique Barboza6-9/+6
The 'fdt' param is not being used in riscv_setup_rom_reset_vec(). Simplify the API by removing it. While we're at it, remove the redundant 'return' statement at the end of function. Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Alistair Francis <alistair.francis@wdc.com> Cc: Bin Meng <bin.meng@windriver.com> Cc: Vijai Kumar K <vijai@behindbytes.com> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220728181926.2123771-1-danielhb413@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: Add Zihintpause supportDao Lu4-1/+25
Added support for RISC-V PAUSE instruction from Zihintpause extension, enabled by default. Tested-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Dao Lu <daolu@rivosinc.com> Message-Id: <20220725034728.2620750-2-daolu@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add option 'rvv_ma_all_1s' to enable optional mask ↵eopXD1-0/+1
agnostic behavior According to v-spec, mask agnostic behavior can be either kept as undisturbed or set elements' bits to all 1s. To distinguish the difference of mask policies, QEMU should be able to simulate the mask agnostic behavior as "set mask elements' bits to all 1s". There are multiple possibility for agnostic elements according to v-spec. The main intent of this patch-set tries to add option that can distinguish between mask policies. Setting agnostic elements to all 1s allows QEMU to express this. This commit adds option 'rvv_ma_all_1s' is added to enable the behavior, it is default as disabled. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-10@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vector permutation instructionsYueh-Ting (eop) Chen2-2/+25
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-9@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vector mask instructionsYueh-Ting (eop) Chen2-0/+14
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-8@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vector floating-point instructionsYueh-Ting (eop) Chen2-0/+38
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-7@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic ↵Yueh-Ting (eop) Chen1-10/+16
instructions Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-6@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer comparison instructionsYueh-Ting (eop) Chen2-0/+11
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-5@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vector integer shift instructionsYueh-Ting (eop) Chen2-0/+8
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-4@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07target/riscv: rvv: Add mask agnostic for vx instructionsYueh-Ting (eop) Chen2-0/+5
Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <165570784143.17634.35095816584573691-3@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
generated by cgit v1.1 at 2025-01-01 20:03:28 +0000