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2021-05-26cpu: Move CPUClass::write_elf* to SysemuCPUOpsPhilippe Mathieu-Daudé8-38/+43
The write_elf*() handlers are used to dump vmcore images. This feature is only meaningful for system emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-19-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Move CPUClass::get_crash_info to SysemuCPUOpsPhilippe Mathieu-Daudé5-5/+9
cpu_get_crash_info() is called on GUEST_PANICKED events, which only occur in system emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-18-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOpsPhilippe Mathieu-Daudé5-11/+14
VirtIO devices are only meaningful with system emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-17-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Move CPUClass::vmsd to SysemuCPUOpsPhilippe Mathieu-Daudé12-25/+22
Migration is specific to system emulation. - Move the CPUClass::vmsd field to SysemuCPUOps, - restrict VMSTATE_CPU() macro to sysemu, - vmstate_dummy is now unused, remove it. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-16-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Introduce SysemuCPUOps structurePhilippe Mathieu-Daudé22-0/+174
Introduce a structure to hold handler specific to sysemu. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-15-f4bug@amsat.org> [rth: Squash "restrict hw/core/sysemu-cpu-ops.h" patch] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Move AVR target vmsd field from CPUClass to DeviceClassPhilippe Mathieu-Daudé2-3/+3
See rationale in previous commit. Targets should use the vmsd field of DeviceClass, not CPUClass. As migration is not important on the AVR target, break the migration compatibility and set the DeviceClass vmsd field. To feel safer, increment the vmstate version. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210517105140.1062037-14-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Rename CPUClass vmsd -> legacy_vmsdPhilippe Mathieu-Daudé10-17/+17
Quoting Peter Maydell [*]: There are two ways to handle migration for a CPU object: (1) like any other device, so it has a dc->vmsd that covers migration for the whole object. As usual for objects that are a subclass of a parent that has state, the first entry in the VMStateDescription field list is VMSTATE_CPU(), which migrates the cpu_common fields, followed by whatever the CPU's own migration fields are. (2) a backwards-compatible mechanism for CPUs that were originally migrated using manual "write fields to the migration stream structures". The on-the-wire migration format for those is based on the 'env' pointer (which isn't a QOM object), and the cpu_common part of the migration data is elsewhere. cpu_exec_realizefn() handles both possibilities: * for type 1, dc->vmsd is set and cc->vmsd is not, so cpu_exec_realizefn() does nothing, and the standard "register dc->vmsd for a device" code does everything needed * for type 2, dc->vmsd is NULL and so we register the vmstate_cpu_common directly to handle the cpu-common fields, and the cc->vmsd to handle the per-CPU stuff You can't change a CPU from one type to the other without breaking migration compatibility, which is why some guest architectures are stuck on the cc->vmsd form. New targets should use dc->vmsd. To avoid new targets to start using type (2), rename cc->vmsd as cc->legacy_vmsd. The correct field to implement is dc->vmsd (the DeviceClass one). See also commit b170fce3dd0 ("cpu: Register VMStateDescription through CPUState") for historic background. [*] https://www.mail-archive.com/qemu-devel@nongnu.org/msg800849.html Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210517105140.1062037-13-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Assert DeviceClass::vmsd is NULL on user emulationPhilippe Mathieu-Daudé3-3/+8
Migration is specific to system emulation. Restrict current DeviceClass::vmsd to sysemu using #ifdef'ry, and assert in cpu_exec_realizefn() that dc->vmsd not set under user emulation. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-12-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Directly use get_memory_mapping() fallback handlers in placePhilippe Mathieu-Daudé2-16/+13
No code uses CPUClass::get_memory_mapping() outside of hw/core/cpu.c: $ git grep -F -- '->get_memory_mapping' hw/core/cpu.c:87: cc->get_memory_mapping(cpu, list, errp); hw/core/cpu.c:439: k->get_memory_mapping = cpu_common_get_memory_mapping; target/i386/cpu.c:7422: cc->get_memory_mapping = x86_cpu_get_memory_mapping; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-11-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Directly use get_paging_enabled() fallback handlers in placePhilippe Mathieu-Daudé2-13/+11
No code uses CPUClass::get_paging_enabled() outside of hw/core/cpu.c: $ git grep -F -- '->get_paging_enabled' hw/core/cpu.c:74: return cc->get_paging_enabled(cpu); hw/core/cpu.c:438: k->get_paging_enabled = cpu_common_get_paging_enabled; target/i386/cpu.c:7418: cc->get_paging_enabled = x86_cpu_get_paging_enabled; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-10-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Directly use cpu_write_elf*() fallback handlers in placePhilippe Mathieu-Daudé2-63/+44
No code directly accesses CPUClass::write_elf*() handlers out of hw/core/cpu.c (the rest are assignation in target/ code): $ git grep -F -- '->write_elf' hw/core/cpu.c:157: return (*cc->write_elf32_qemunote)(f, cpu, opaque); hw/core/cpu.c:171: return (*cc->write_elf32_note)(f, cpu, cpuid, opaque); hw/core/cpu.c:186: return (*cc->write_elf64_qemunote)(f, cpu, opaque); hw/core/cpu.c:200: return (*cc->write_elf64_note)(f, cpu, cpuid, opaque); hw/core/cpu.c:440: k->write_elf32_qemunote = cpu_common_write_elf32_qemunote; hw/core/cpu.c:441: k->write_elf32_note = cpu_common_write_elf32_note; hw/core/cpu.c:442: k->write_elf64_qemunote = cpu_common_write_elf64_qemunote; hw/core/cpu.c:443: k->write_elf64_note = cpu_common_write_elf64_note; target/arm/cpu.c:2304: cc->write_elf64_note = arm_cpu_write_elf64_note; target/arm/cpu.c:2305: cc->write_elf32_note = arm_cpu_write_elf32_note; target/i386/cpu.c:7425: cc->write_elf64_note = x86_cpu_write_elf64_note; target/i386/cpu.c:7426: cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote; target/i386/cpu.c:7427: cc->write_elf32_note = x86_cpu_write_elf32_note; target/i386/cpu.c:7428: cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; target/ppc/translate_init.c.inc:10891: cc->write_elf64_note = ppc64_cpu_write_elf64_note; target/ppc/translate_init.c.inc:10892: cc->write_elf32_note = ppc32_cpu_write_elf32_note; target/s390x/cpu.c:522: cc->write_elf64_note = s390_cpu_write_elf64_note; Check the handler presence in place and remove the common fallback code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-9-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Introduce cpu_virtio_is_big_endian()Philippe Mathieu-Daudé4-9/+20
Introduce the cpu_virtio_is_big_endian() generic helper to avoid calling CPUClass internal virtio_is_big_endian() one. Similarly to commit bf7663c4bd8 ("cpu: introduce CPUClass::virtio_is_big_endian()"), we keep 'virtio' in the method name to hint this handler shouldn't be called anywhere but from the virtio code. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-8-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrsPhilippe Mathieu-Daudé2-29/+36
To be able to later extract the cpu_get_phys_page_debug() and cpu_asidx_from_attrs() handlers from CPUClass, un-inline them from "hw/core/cpu.h". Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-7-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Split as cpu-common / cpu-sysemuPhilippe Mathieu-Daudé3-18/+36
The current cpu.c contains sysemu-specific methods. To avoid building them in user-mode builds, split the current cpu.c as cpu-common.c / cpu-sysemu.c. Start by moving cpu_get_crash_info(). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-6-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26cpu: Remove duplicated 'sysemu/hw_accel.h' headerPhilippe Mathieu-Daudé1-1/+0
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210517105140.1062037-5-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26tcg/aarch64: Fix tcg_out_rotlYasuo Kuwahara1-3/+2
The last argument of tcg_out_extr() must be in the range 0-31 if ext==0. Before the fix, when m==0 it becomes 32 and it crashes with an Illegal instruction on Apple Silicon. After the fix, it will be 0. If m is in the range 1-31, it is the same as before. Signed-off-by: Yasuo Kuwahara <kwhr00@gmail.com> Message-Id: <CAHfJ0vSXnmnTLmT0kR=a8ACRdw_UsLYOhStzUzgVEHoH8U-7sA@mail.gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26replay: fix watchpoint processing for reverse debuggingPavel Dovgalyuk1-0/+10
This patch enables reverse debugging with watchpoints. Reverse continue scans the execution to find the breakpoints and watchpoints that should fire. It uses helper function replay_breakpoint() for that. But this function needs to access icount, which can't be correct in the middle of TB. Therefore, in case of watchpoint, we have to retranslate the block to allow this access. Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Message-Id: <162072430303.827403.7379783546934958566.stgit@pasha-ThinkPad-X280> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26accel/tcg: Keep TranslationBlock headers local to TCGPhilippe Mathieu-Daudé8-9/+8
Only the TCG accelerator uses the TranslationBlock API. Move the tb-context.h / tb-hash.h / tb-lookup.h from the global namespace to the TCG one (in accel/tcg). Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210524170453.3791436-3-f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26accel/tcg: Reduce 'exec/tb-context.h' inclusionPhilippe Mathieu-Daudé5-2/+3
Only 2 headers require "exec/tb-context.h". Instead of having all files including "exec/exec-all.h" also including it, directly include it where it is required: - accel/tcg/cpu-exec.c - accel/tcg/translate-all.c For plugins/plugin.h, we were implicitly relying on exec/exec-all.h -> exec/tb-context.h -> qemu/qht.h which is now included directly. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210524170453.3791436-2-f4bug@amsat.org> [rth: Fix plugins/plugin.h compilation] Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26exec/memory: Use correct type sizePhilippe Mathieu-Daudé1-1/+1
Use uint8_t for (unsigned) byte. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210518183655.1711377-7-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26exec/memory_ldst_cached: Use correct type sizePhilippe Mathieu-Daudé1-2/+2
Use uint16_t for (unsigned) 16-bit word. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210518183655.1711377-6-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26exec/memory_ldst_phys: Use correct type sizesPhilippe Mathieu-Daudé1-8/+8
Use uint8_t for (unsigned) byte, and uint16_t for (unsigned) 16-bit word. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210518183655.1711377-5-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26exec/memory_ldst: Use correct type sizesPhilippe Mathieu-Daudé2-18/+18
Use uint8_t for (unsigned) byte, and uint16_t for (unsigned) 16-bit word. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210518183655.1711377-4-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26exec/memory_ldst_phys: Sort declarationsPhilippe Mathieu-Daudé1-36/+36
To ease the file review, sort the declarations by the size of the access (8, 16, 32). Simple code movement, no logical change. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210518183655.1711377-3-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-26exec/memory_ldst_cached: Sort declarationsPhilippe Mathieu-Daudé1-20/+20
To ease the file review, sort the declarations by the size of the access (8, 16, 32). Simple code movement, no logical change. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20210518183655.1711377-2-philmd@redhat.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-05-25Merge remote-tracking branch ↵Peter Maydell5-184/+297
'remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2' into staging Testing, gdbstub and plugin updates - ensure gitlab references master registry - add special rule for hexagon image - clean-up gdbstub's argument handling - fix replay HMP commands to accept long icount - minor re-factor of gdbstub replay handling - update syscall plugin to be more useful # gpg: Signature made Tue 25 May 2021 16:55:16 BST # gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44 # gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full] # Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44 * remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2: plugins/syscall: Added a table-like summary output gdbstub: tidy away reverse debugging check into function hmp-commands: expand type of icount to "l" in replay commands gdbstub: Replace GdbCmdContext with plain g_array() gdbstub: Constify GdbCmdParseEntry gitlab: add special rule for the hexagon container gitlab: explicitly reference the upstream registry Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25plugins/syscall: Added a table-like summary outputMahmoud Mandour1-5/+93
Added a table-like output which contains the total number of calls for each used syscall along with the number of errors that occurred. Per-call tracing is still available through supplying the argument ``print`` to the plugin. Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210519032409.3041-1-ma.mandourr@gmail.com> Message-Id: <20210520174303.12310-9-alex.bennee@linaro.org>
2021-05-25gdbstub: tidy away reverse debugging check into functionAlex Bennée1-2/+11
In theory we don't need an actual record/replay to enact reverse debugging on a purely deterministic system (i.e one with no external inputs running under icount). Tidy away the logic into a little function. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210520174303.12310-8-alex.bennee@linaro.org>
2021-05-25hmp-commands: expand type of icount to "l" in replay commandsAlex Bennée1-2/+2
This is not a 32 bit number, it can (and most likely will) be quite a big one. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210520174303.12310-7-alex.bennee@linaro.org>
2021-05-25gdbstub: Replace GdbCmdContext with plain g_array()Alex Bennée1-168/+154
Instead of jumping through hoops let glib deal with both tracking the number of elements and auto freeing the memory once we are done. This allows is to drop the usage of ALLOCA(3) which the man-page mentions its "use is discouraged". Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210520174303.12310-6-alex.bennee@linaro.org>
2021-05-25gdbstub: Constify GdbCmdParseEntryPhilippe Mathieu-Daudé1-4/+4
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210505170055.1415360-3-philmd@redhat.com> Message-Id: <20210520174303.12310-5-alex.bennee@linaro.org>
2021-05-25gitlab: add special rule for the hexagon containerAlex Bennée2-1/+32
The hexagon container is always manually built but of course not everyone will be building it themselves and pushing to their registries. We still need to create a "local" registry copy for the actual gitlab tests to run. We don't build it in this case, just pull it across from the upstream registry. We disable this rule from running on the qemu-project itself so it doesn't accidentally wipe out our master copy. Fixes: 910c40ee94 ("gitlab: add build-user-hexagon test") Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Cornelia Huck <cohuck@redhat.com> Reviewed-by: Willian Rampazzo <willianr@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: Cornelia Huck <cohuck@redhat.com> Message-Id: <20210520174303.12310-4-alex.bennee@linaro.org>
2021-05-25Merge remote-tracking branch ↵Peter Maydell33-1258/+8233
'remotes/pmaydell/tags/pull-target-arm-20210525' into staging target-arm queue: * Implement SVE2 emulation * Implement integer matrix multiply accumulate * Implement FEAT_TLBIOS * Implement FEAT_TLBRANGE * disas/libvixl: Protect C system header for C++ compiler * Use correct SP in M-profile exception return * AN524, AN547: Correct modelling of internal SRAMs * hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic * hw/arm/smmuv3: Another range invalidation fix # gpg: Signature made Tue 25 May 2021 16:02:25 BST # gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE # gpg: issuer "peter.maydell@linaro.org" # gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@gmail.com>" [ultimate] # gpg: aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate] # Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE * remotes/pmaydell/tags/pull-target-arm-20210525: (114 commits) target/arm: Enable SVE2 and related extensions linux-user/aarch64: Enable hwcap bits for sve2 and related extensions target/arm: Implement integer matrix multiply accumulate target/arm: Implement aarch32 VSUDOT, VUSDOT target/arm: Split decode of VSDOT and VUDOT target/arm: Split out do_neon_ddda target/arm: Fix decode for VDOT (indexed) target/arm: Remove unused fpst from VDOT_scalar target/arm: Split out do_neon_ddda_fpst target/arm: Implement aarch64 SUDOT, USDOT target/arm: Implement SVE2 fp multiply-add long target/arm: Move endian adjustment macros to vec_internal.h target/arm: Implement SVE2 bitwise shift immediate target/arm: Implement 128-bit ZIP, UZP, TRN target/arm: Implement SVE2 LD1RO target/arm: Tidy do_ldrq target/arm: Share table of sve load functions target/arm: Implement SVE2 FLOGB target/arm: Implement SVE2 FCVTXNT, FCVTX target/arm: Implement SVE2 FCVTLT ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Enable SVE2 and related extensionsRichard Henderson3-0/+16
Disable I8MM again for !have_neon during realize. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-93-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25linux-user/aarch64: Enable hwcap bits for sve2 and related extensionsRichard Henderson1-0/+10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-92-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement integer matrix multiply accumulateRichard Henderson7-0/+169
This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE, and V{S,U,US}MMLA.S8 for AArch32 NEON. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-91-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement aarch32 VSUDOT, VUSDOTRichard Henderson3-0/+38
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-90-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Split decode of VSDOT and VUDOTRichard Henderson2-11/+28
Now that we have a common helper, sharing decode does not save much. Also, this will solve an upcoming naming problem. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-89-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Split out do_neon_dddaRichard Henderson1-52/+38
Split out a helper that can handle the 4-register format for helpers shared with SVE. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-88-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Fix decode for VDOT (indexed)Richard Henderson2-3/+3
We were extracting the M register twice, once incorrectly as M:vm and once correctly as rm. Remove the incorrect name and remove the incorrect decode. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-87-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Remove unused fpst from VDOT_scalarRichard Henderson1-3/+0
Cut and paste error from another pattern. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-86-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Split out do_neon_ddda_fpstRichard Henderson1-55/+43
Split out a helper that can handle the 4-register format for helpers shared with SVE. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-85-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement aarch64 SUDOT, USDOTRichard Henderson2-0/+30
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-84-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement SVE2 fp multiply-add longStephen Long4-0/+141
Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-83-richard.henderson@linaro.org Message-Id: <20200504171240.11220-1-steplong@quicinc.com> [rth: Rearrange to use float16_to_float32_by_bits.] Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Move endian adjustment macros to vec_internal.hRichard Henderson3-28/+24
We have two copies of these, one set of which is not complete. Move them to a common header. Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-82-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement SVE2 bitwise shift immediateStephen Long4-0/+133
Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stephen Long <steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-81-richard.henderson@linaro.org Message-Id: <20200430194159.24064-1-steplong@quicinc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement 128-bit ZIP, UZP, TRNRichard Henderson4-8/+90
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-80-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Implement SVE2 LD1RORichard Henderson2-0/+97
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-79-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Tidy do_ldrqRichard Henderson1-9/+4
Use tcg_constant_i32 for passing the simd descriptor, as this hashed value does not need to be freed. Rename dofs to doff to match poff. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-78-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-05-25target/arm: Share table of sve load functionsRichard Henderson1-128/+126
The table used by do_ldrq is a subset of the table used by do_ld_zpa; we can share them by passing dtype instead of msz to do_ldrq. The lack of MTE handling in do_ldrq was a bug, fixed by this change. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210525010358.152808-77-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
generated by cgit v1.1 at 2025-01-15 10:23:08 +0000