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2021-02-08gdbstub: Fix handle_query_xfer_auxvRichard Henderson1-5/+12
The main problem was that we were treating a guest address as a host address with a mere cast. Use the correct interface for accessing guest memory. Do not allow offset == auxv_len, which would result in an empty packet. Fixes: 51c623b0de1 ("gdbstub: add support to Xfer:auxv:read: packet") Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210128201831.534033-1-richard.henderson@linaro.org> Message-Id: <20210202134001.25738-11-alex.bennee@linaro.org>
2021-02-08tests/tcg: don't silently skip the gdb testsAlex Bennée1-1/+4
Otherwise people won't know what they are missing. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210202134001.25738-10-alex.bennee@linaro.org>
2021-02-08configure: bump the minimum gdb version for check-tcg to 9.1Alex Bennée1-1/+1
For SVE, currently the bulk of the GDB TCG tests, we need at least GDB 9.1 to support the "ieee_half" data type we report. This only affects when GDB tests are run; users can still use lower versions of gdb as long as they aren't talking to an SVE enabled model. The work around is to either get a newer gdb or disable SVE for their CPU model. Reported-by: Claudio Fontana <cfontana@suse.de> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Cc: Luis Machado <luis.machado@linaro.org> Message-Id: <20210202134001.25738-9-alex.bennee@linaro.org>
2021-02-08configure: make version_ge more tolerant of shady version inputAlex Bennée1-2/+2
When checking GDB versions we have to tolerate all sorts of random distro extensions to the version string. While we already attempt to do some of that before we call version_ge is makes sense to try and regularise the first input by stripping extraneous -'s. While we at it convert the old-style shell quoting into a cleaner form t shut up my editors linter lest it confuse me by underlining the whole line. Suggested-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Eric Blake <eblake@redhat.com> Message-Id: <20210202134001.25738-8-alex.bennee@linaro.org>
2021-02-08tests/docker: add a docker-exec-copy-testAlex Bennée3-2/+33
This provides test machinery for checking the QEMU copying logic works properly. It takes considerably less time to run than starting a debootstrap only for it to fail later. I considered adding a remove command to docker.py but figured that might be gold plating given the relative size of the containers compared to the ones with actual stuff in them. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210202134001.25738-7-alex.bennee@linaro.org>
2021-02-08tests/docker: alias docker-help target for consistencyAlex Bennée2-2/+4
We have a bunch of -help targets so this will save some cognitive dissonance. Keep the original for those with muscle memory. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210202134001.25738-6-alex.bennee@linaro.org>
2021-02-08tests/docker: preserve original name when copying libsAlex Bennée1-3/+4
While it is important we chase down the symlinks to copy the correct data we can confuse the kernel by renaming the interpreter to what is in the binary. Extend _copy_with_mkdir to preserve the original name of the file when asked. Fixes: 5e33f7fead ("tests/docker: better handle symlinked libs") Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210202134001.25738-5-alex.bennee@linaro.org>
2021-02-08tests/docker: make _copy_with_mkdir accept missing filesAlex Bennée1-1/+6
Depending on the linker/ldd setup we might get a file with no path. Typically this is the psuedo library linux-vdso.so which doesn't actually exist on the disk. Rather than try and catch these distro specific edge cases just shout about it and try and continue. Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210202134001.25738-4-alex.bennee@linaro.org>
2021-02-08tests/docker: Fix typo in help messagePhilippe Mathieu-Daudé1-1/+1
To have the variable properly passed, we need to set it, ie. NOUSER=1. Fix the message displayed by 'make docker'. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210119052120.522069-1-f4bug@amsat.org> Message-Id: <20210202134001.25738-3-alex.bennee@linaro.org>
2021-02-08tests/docker: Fix _get_so_libs() for docker-binfmt-imagePhilippe Mathieu-Daudé1-1/+1
Fix a variable rename mistake from commit 5e33f7fead5: Traceback (most recent call last): File "./tests/docker/docker.py", line 710, in <module> sys.exit(main()) File "./tests/docker/docker.py", line 706, in main return args.cmdobj.run(args, argv) File "./tests/docker/docker.py", line 489, in run _copy_binary_with_libs(args.include_executable, File "./tests/docker/docker.py", line 149, in _copy_binary_with_libs libs = _get_so_libs(src) File "./tests/docker/docker.py", line 123, in _get_so_libs libs.append(s.group(1)) NameError: name 's' is not defined Fixes: 5e33f7fead5 ("tests/docker: better handle symlinked libs") Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210119050149.516910-1-f4bug@amsat.org> Message-Id: <20210202134001.25738-2-alex.bennee@linaro.org>
2021-02-08tests/acceptance: Increase the timeout in the replay testsThomas Huth1-1/+1
Our gitlab-CI just showed a failed test_ppc_mac99 since it was apparently killed some few seconds before the test finished. Allow it some more time to complete. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> Acked-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210127065222.48650-1-thuth@redhat.com>
2021-02-05Merge remote-tracking branch 'remotes/rth-gitlab/tags/pull-tcg-20210205' ↵Peter Maydell108-1064/+1564
into staging TCGCPUOps cleanups (claudio) tcg/s390 compare fix (phil) tcg/aarch64 rotli_vec fix tcg/tci cleanups and fixes # gpg: Signature made Fri 05 Feb 2021 22:55:10 GMT # gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F # gpg: issuer "richard.henderson@linaro.org" # gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>" [full] # Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F * remotes/rth-gitlab/tags/pull-tcg-20210205: (46 commits) accel: introduce AccelCPUClass extending CPUClass accel: replace struct CpusAccel with AccelOpsClass accel: extend AccelState and AccelClass to user-mode cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClass cpu: move debug_check_watchpoint to tcg_ops cpu: move adjust_watchpoint_address to tcg_ops physmem: make watchpoint checking code TCG-only cpu: move do_unaligned_access to tcg_ops cpu: move cc->transaction_failed to tcg_ops cpu: move cc->do_interrupt to tcg_ops target/arm: do not use cc->do_interrupt for KVM directly cpu: Move debug_excp_handler to tcg_ops cpu: Move tlb_fill to tcg_ops cpu: Move cpu_exec_* to tcg_ops cpu: Move synchronize_from_tb() to tcg_ops accel/tcg: split TCG-only code from cpu_exec_realizefn target/riscv: remove CONFIG_TCG, as it is always TCG cpu: Introduce TCGCpuOperations struct tcg/tci: Remove TCG_CONST tcg/tci: Fix TCG_REG_R4 misusage ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2021-02-05accel: introduce AccelCPUClass extending CPUClassClaudio Fontana4-0/+87
add a new optional interface to CPUClass, which allows accelerators to extend the CPUClass with additional accelerator-specific initializations. This will allow to separate the target cpu code that is specific to each accelerator, and register it automatically with object hierarchy lookup depending on accelerator code availability, as part of the accel_init_interfaces() initialization step. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-19-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel: replace struct CpusAccel with AccelOpsClassClaudio Fontana44-163/+361
This will allow us to centralize the registration of the cpus.c module accelerator operations (in accel/accel-softmmu.c), and trigger it automatically using object hierarchy lookup from the new accel_init_interfaces() initialization step, depending just on which accelerators are available in the code. Rename all tcg-cpus.c, kvm-cpus.c, etc to tcg-accel-ops.c, kvm-accel-ops.c, etc, matching the object type names. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-18-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel: extend AccelState and AccelClass to user-modeClaudio Fontana24-53/+125
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> [claudio: rebased on Richard's splitwx work] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-17-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: tcg_ops: move to tcg-cpu-ops.h, keep a pointer in CPUClassClaudio Fontana36-306/+582
we cannot in principle make the TCG Operations field definitions conditional on CONFIG_TCG in code that is included by both common_ss and specific_ss modules. Therefore, what we can do safely to restrict the TCG fields to TCG-only builds, is to move all tcg cpu operations into a separate header file, which is only included by TCG, target-specific code. This leaves just a NULL pointer in the cpu.h for the non-TCG builds. This also tidies up the code in all targets a bit, having all TCG cpu operations neatly contained by a dedicated data struct. Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-16-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move debug_check_watchpoint to tcg_opsClaudio Fontana5-17/+12
commit 568496c0c0f1 ("cpu: Add callback to check architectural") and commit 3826121d9298 ("target-arm: Implement checking of fired") introduced an ARM-specific hack for cpu_check_watchpoint. Make debug_check_watchpoint optional, and move it to tcg_ops. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-15-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move adjust_watchpoint_address to tcg_opsClaudio Fontana4-9/+10
commit 40612000599e ("arm: Correctly handle watchpoints for BE32 CPUs") introduced this ARM-specific, TCG-specific hack to adjust the address, before checking it with cpu_check_watchpoint. Make adjust_watchpoint_address optional and move it to tcg_ops. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-14-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05physmem: make watchpoint checking code TCG-onlyClaudio Fontana1-69/+72
cpu_check_watchpoint, watchpoint_address_matches are TCG-only. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-13-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move do_unaligned_access to tcg_opsClaudio Fontana14-19/+23
make it consistently SOFTMMU-only. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: make the field presence in cpu.h unconditional, removing the ifdefs] Message-Id: <20210204163931.7358-12-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->transaction_failed to tcg_opsClaudio Fontana12-29/+34
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: wrap target code around CONFIG_TCG and !CONFIG_USER_ONLY] avoiding its use in headers used by common_ss code (should be poisoned). Note: need to be careful with the use of CONFIG_USER_ONLY, Message-Id: <20210204163931.7358-11-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: move cc->do_interrupt to tcg_opsClaudio Fontana27-42/+41
Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-10-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05target/arm: do not use cc->do_interrupt for KVM directlyClaudio Fontana2-4/+6
cc->do_interrupt is in theory a TCG callback used in accel/tcg only, to prepare the emulated architecture to take an interrupt as defined in the hardware specifications, but in reality the _do_interrupt style of functions in targets are also occasionally reused by KVM to prepare the architecture state in a similar way where userspace code has identified that it needs to deliver an exception to the guest. In the case of ARM, that includes: 1) the vcpu thread got a SIGBUS indicating a memory error, and we need to deliver a Synchronous External Abort to the guest to let it know about the error. 2) the kernel told us about a debug exception (breakpoint, watchpoint) but it is not for one of QEMU's own gdbstub breakpoints/watchpoints so it must be a breakpoint the guest itself has set up, therefore we need to deliver it to the guest. So in order to reuse code, the same arm_do_interrupt function is used. This is all fine, but we need to avoid calling it using the callback registered in CPUClass, since that one is now TCG-only. Fortunately this is easily solved by replacing calls to CPUClass::do_interrupt() with explicit calls to arm_do_interrupt(). Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Cc: Peter Maydell <peter.maydell@linaro.org> Message-Id: <20210204163931.7358-9-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move debug_excp_handler to tcg_opsEduardo Habkost7-9/+9
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-8-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move tlb_fill to tcg_opsEduardo Habkost26-38/+42
[claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-7-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move cpu_exec_* to tcg_opsEduardo Habkost25-42/+54
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20210204163931.7358-6-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Move synchronize_from_tb() to tcg_opsEduardo Habkost13-22/+30
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: wrapped target code in CONFIG_TCG, reworded comments] Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-5-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05accel/tcg: split TCG-only code from cpu_exec_realizefnClaudio Fontana5-40/+77
move away TCG-only code, make it compile only on TCG. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> [claudio: moved the prototypes from hw/core/cpu.h to exec/cpu-all.h] Signed-off-by: Claudio Fontana <cfontana@suse.de> Message-Id: <20210204163931.7358-4-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05target/riscv: remove CONFIG_TCG, as it is always TCGClaudio Fontana1-2/+1
for now only TCG is allowed as an accelerator for riscv, so remove the CONFIG_TCG use. Signed-off-by: Claudio Fontana <cfontana@suse.de> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-3-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05cpu: Introduce TCGCpuOperations structEduardo Habkost25-30/+48
The TCG-specific CPU methods will be moved to a separate struct, to make it easier to move accel-specific code outside generic CPU code in the future. Start by moving tcg_initialize(). The new CPUClass.tcg_opts field may eventually become a pointer, but keep it an embedded struct for now, to make code conversion easier. Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> [claudio: move TCGCpuOperations inside include/hw/core/cpu.h] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-Id: <20210204163931.7358-2-cfontana@suse.de> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TCG_CONSTRichard Henderson4-194/+89
Restrict all operands to registers. All constants will be forced into registers by the middle-end. Removing the difference in how immediate integers were encoded will allow more code to be shared between 32-bit and 64-bit operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Fix TCG_REG_R4 misusageRichard Henderson2-10/+5
This was removed from tcg_target_reg_alloc_order and tcg_target_call_iarg_regs on the assumption that it was the stack. This was incorrectly copied from i386. For tci, the stack is R15. By adding R4 back to tcg_target_call_iarg_regs, adjust the other entries so that 6 (or 12) entries are still present in the array, and adjust the numbers in the interpreter. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Restrict TCG_TARGET_NB_REGS to 16Richard Henderson2-53/+5
As noted in several comments, 8 regs is not enough for 32-bit to perform calls, as currently implemented. Shortly, we will rearrange the encoding which will make 32 regs impossible. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove TODO as unusedRichard Henderson1-8/+0
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Implement 64-bit divisionRichard Henderson3-11/+25
Trivially implemented like other arithmetic. Tested via check-tcg and the ppc64 target. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Remove dead code for TCG_TARGET_HAS_div2_*Richard Henderson2-20/+0
We do not simultaneously support div and div2 -- it's one or the other. TCI is already using div, so remove div2. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Use g_assert_not_reachedRichard Henderson1-8/+7
Three TODO instances are never happen cases. Other uses of tcg_abort are also indicating unreachable cases. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_{st_i32,st32_i64}Richard Henderson1-6/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Move stack bounds check to compile-timeRichard Henderson2-2/+13
The existing check was incomplete: (1) Only applied to two of the 7 stores, and not to the loads at all. (2) Only checked the upper, but not the lower bound of the stack. Doing this at compile time means that we don't need to do it at runtime as well. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_st16_{i32,i64}Richard Henderson1-7/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_st8_{i32,i64}Richard Henderson1-7/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_{ld_i32,ld32u_i64}Richard Henderson1-6/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld16s_{i32,i64}Richard Henderson1-4/+1
Eliminating a TODO for ld16s_i64. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld16u_{i32,i64}Richard Henderson1-8/+5
Eliminating a TODO for ld16u_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld8s_{i32,i64}Richard Henderson1-8/+5
Eliminating a TODO for ld8s_i32. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Merge INDEX_op_ld8u_{i32,i64}Richard Henderson1-7/+13
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg64 into 64-bit callersRichard Henderson1-33/+27
Note that we had two functions of the same name: a 32-bit version which took two register numbers and a 64-bit version which was a no-op wrapper for tcg_write_reg. After this, we are left with only the 32-bit version. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg32 into all callersRichard Henderson1-36/+30
For a 64-bit TCI, the upper bits of a 32-bit operation are undefined (much like a native ppc64 32-bit operation). It simplifies everything if we don't force-extend the result. Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg16 into the only callerRichard Henderson1-9/+1
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-02-05tcg/tci: Inline tci_write_reg8 into its callersRichard Henderson1-7/+2
Tested-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
generated by cgit v1.1 at 2025-01-13 10:11:10 +0000