riscv-gnu-toolchain/qemu.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2020-06-22	hw/rx: RX62N microcontroller (MCU)	Yoshinori Sato	6	-0/+339
2020-06-22	hw/char: RX62N serial communication interface (SCI)	Yoshinori Sato	5	-0/+407
2020-06-22	hw/timer: RX62N compare match timer (CMT)	Yoshinori Sato	5	-2/+329
2020-06-22	hw/timer: RX62N 8-Bit timer (TMR)	Yoshinori Sato	5	-0/+538
2020-06-22	hw/intc: RX62N interrupt controller (ICUa)	Yoshinori Sato	5	-0/+483
2020-06-22	hw/timer/sh_timer: Remove unused 'qemu/timer.h' include	Philippe Mathieu-Daudé	1	-1/+0
2020-06-22	hw/sh4: Extract timer definitions to 'hw/timer/tmu012.h'	Philippe Mathieu-Daudé	4	-9/+26
2020-06-22	hw/sh4: Use MemoryRegion typedef	Philippe Mathieu-Daudé	1	-3/+2
2020-06-22	MAINTAINERS: Add an entry for common Renesas peripherals	Philippe Mathieu-Daudé	1	-1/+8
2020-06-22	MAINTAINERS: Cover sh_intc files in the R2D/Shix machine sections	Philippe Mathieu-Daudé	1	-0/+3
2020-06-22	Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200...	Peter Maydell	26	-182/+1350
2020-06-22	target/xtensa: drop gen_io_end call	Max Filippov	1	-3/+0
2020-06-21	tests/acceptance: record/replay tests with advcal images	Pavel Dovgalyuk	1	-0/+108
2020-06-21	tests/acceptance: add record/replay test for m68k	Pavel Dovgalyuk	1	-0/+18
2020-06-21	tests/acceptance: add record/replay test for ppc64	Pavel Dovgalyuk	1	-0/+16
2020-06-21	tests/acceptance: add record/replay test for arm	Pavel Dovgalyuk	1	-0/+48
2020-06-21	tests/acceptance: add record/replay test for aarch64	Pavel Dovgalyuk	1	-0/+19
2020-06-21	tests/acceptance: add kernel record/replay test for x86_64	Pavel Dovgalyuk	1	-0/+18
2020-06-21	tests/acceptance: add base class record/replay kernel tests	Pavel Dovgalyuk	2	-0/+74
2020-06-21	MAINTAINERS: Add an entry to review Avocado based acceptance tests	Philippe Mathieu-Daudé	1	-0/+8
2020-06-19	Merge remote-tracking branch 'remotes/kraxel/tags/audio-20200619-pull-request...	Peter Maydell	3	-37/+40
2020-06-19	qht: Fix threshold rate calculation	Richard Henderson	1	-1/+2
2020-06-19	hw/riscv: sifive_u: Add a dummy DDR memory controller device	Bin Meng	2	-0/+5
2020-06-19	hw/riscv: sifive_u: Sort the SoC memmap table entries	Bin Meng	1	-2/+2
2020-06-19	hw/riscv: sifive_u: Support different boot source per MSEL pin state	Bin Meng	2	-8/+37
2020-06-19	hw/riscv: sifive: Change SiFive E/U CPU reset vector to 0x1004	Bin Meng	3	-15/+17
2020-06-19	target/riscv: Rename IBEX CPU init routine	Bin Meng	1	-2/+2
2020-06-19	hw/riscv: sifive_u: Add a new property msel for MSEL pin state	Bin Meng	2	-0/+8
2020-06-19	hw/riscv: sifive_u: Rename serial property get/set functions to a generic name	Bin Meng	1	-6/+8
2020-06-19	hw/riscv: sifive_u: Add reset functionality	Bin Meng	1	-1/+23
2020-06-19	hw/riscv: sifive_gpio: Do not blindly trigger output IRQs	Bin Meng	1	-1/+3
2020-06-19	hw/riscv: sifive_u: Hook a GPIO controller	Bin Meng	2	-2/+60
2020-06-19	hw/riscv: sifive_gpio: Add a new 'ngpio' property	Bin Meng	2	-11/+22
2020-06-19	hw/riscv: sifive_gpio: Clean up the codes	Bin Meng	2	-11/+9
2020-06-19	hw/riscv: sifive_u: Generate device tree node for OTP	Bin Meng	1	-0/+11
2020-06-19	hw/riscv: sifive_u: Simplify the GEM IRQ connect code a little bit	Bin Meng	1	-6/+1
2020-06-19	hw/riscv: opentitan: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-15/+14
2020-06-19	hw/riscv: sifive_e: Remove the riscv_ prefix of the machine* and soc* functions	Bin Meng	1	-12/+12
2020-06-19	target/riscv: Use a smaller guess size for no-MMU PMP	Alistair Francis	1	-5/+9
2020-06-19	riscv/opentitan: Connect the UART device	Alistair Francis	2	-2/+36
2020-06-19	riscv/opentitan: Connect the PLIC device	Alistair Francis	2	-2/+15
2020-06-19	hw/intc: Initial commit of lowRISC Ibex PLIC	Alistair Francis	4	-0/+327
2020-06-19	hw/char: Initial commit of Ibex UART	Alistair Francis	5	-0/+609
2020-06-19	riscv/opentitan: Fix the ROM size	Alistair Francis	1	-1/+2
2020-06-19	target/riscv: Implement checks for hfence	Alistair Francis	3	-26/+24
2020-06-19	target/riscv: Move the hfence instructions to the rvh decode	Alistair Francis	4	-41/+63
2020-06-19	target/riscv: Report errors validating 2nd-stage PTEs	Alistair Francis	1	-2/+7
2020-06-19	target/riscv: Set access as data_load when validating stage-2 PTEs	Alistair Francis	1	-1/+1
2020-06-19	riscv: Keep the CPU init routine names consistent	Bin Meng	1	-4/+4
2020-06-19	riscv: Generalize CPU init routine for the imacu CPU	Bin Meng	1	-21/+10